Commit graph

17307 commits

Author SHA1 Message Date
Peng Fan
5f2953eb6b imx9: use parameter freq when set_arm_clk
The freq parameter was ignored, should use it when configuring ARM PLL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
a6b36e9970 imx9: add more PLL settings
Add more PLL settings for A55 and Display

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
69326a7f20 imx9: configure M33 systick to 24M
The M33 systick should be 24M per reference mannual, so correct it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
99ac6c769f imx: move imx8 sci header file to include/firmware/imx
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21 16:54:32 +02:00
Peng Fan
be0ad00409 imx: spl_imx_romapi: typo fix
Unknow->Unknown

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Peng Fan
6490c1271a imx8ulp: build ahab
The ahab was missed to be compiled, so add it back.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Fabio Estevam
0aea5dda29 ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation
Commit 1a7904fdfa ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
flags to set host caps") exposed the following SD card error:

U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)

CPU:   Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM:  1 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Card did not respond to voltage
select! : -110
*** Warning - No block device, using default environment

The reason of the problem, as explained by Ye Li:

"When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
not configure pad for VSELECT, also the data pad should be set to
100Mhz/200Mhz pin states."

Apply these changes into u-boot.dtsi for now. When these changes
reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.

This fixes UHS mode on the imx7d-sdb board.

Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Marek Vasut
eb1e370a9b thermal: imx_tmu: Move architecture code into driver
Stop polluting the architecture directory with driver specific code,
move it into driver where it should be. Split the code slightly so
the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout
and programming are in their separate functions, and called in case
of matching SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-21 13:48:52 +02:00
Fedor Ross
b1d20ae5a6 ARM: imx: Fix parsing of ROM log event IDs on iMX8M
It seems like the ROM log events for the iMX8M are not fully covered by
AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
ID 0x82 seems to use parameter0 which stops the parsing because the end
of list is detected too early.

This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
parsed.

Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log")

Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Jonas Karlman
fd6e425be2 rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1492992 bytes read in 129 ms (11 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x16c800
  1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s

The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-19 08:50:44 +08:00
Jonas Karlman
61ff869fd2 rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhci
Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:05 +08:00
Jonas Karlman
153c87be48 rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch Kconfig
Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:05 +08:00
Jonas Karlman
64f79f88a7 rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.

Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1384448 bytes read in 119 ms (11.1 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x152000
  1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:05 +08:00
Jonas Karlman
674803fe86 rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
41cb87be06 rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
1bf49d5a4a rockchip: rk3566-radxa-cm3-io: Update defconfig
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
dc27b4a1af rockchip: rk356x-u-boot: Add xin24m clock node to SPL
Add bootph-all prop to xin24m clock node, it is referenced by cru node.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Christopher Obbard
bfbef68ae1 ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy
Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.

Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
[eugen.hristev@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Joseph Chen
ec8242cceb ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
6e2b8344d6 rockchip: rock-pi-4: Use SDMA to boost eMMC performance
Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 10000000 2000 10000

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
cf777572ca rockchip: rockpro64: Use SDMA to boost eMMC performance
Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 10000000 2000 10000

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:34:45 +08:00
Jonas Karlman
3b804b370d mmc: rockchip_sdhci: Disable DMA mode using a device tree property
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:

  ## Checking hash(es) for Image atf-2 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-2' image node
  spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.

In commit 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.

Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-18 08:34:45 +08:00
Eugen Hristev
bb52f1c604 reset: rockchip: implement rk3588 lookup table
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.

This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")

Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.

Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
cec4f82f11 ARM: dts: rk3588-rock-5b-u-boot: add bootph-all to pinctrl for sdmmc
To be able to initialize the pinctrl correctly at SPL level and read
u-boot proper from SD-Card, the pinctrl must be initialized.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
9ceef3d9a7 ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
Add USB 2.0 host nodes and PHYs.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 09:53:32 +08:00
Tom Rini
c21fc9e152 Xilinx changes for v2023.07-rc3
.mailmap
 - Fix Xilinx IDs
 
 ZynqMP:
 - Fix R5 split boot mode
 - DT fixes - sync with Linux
 
 Xilinx:
 - Enable virtio and RNG support
 - Enable ADI ethernet phy
 
 SPI/Zynq:
 - Fix dummy byte calculation
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZGM+/gAKCRDKSWXLKUoM
 Id6XAKCEfBfLOxuya8r8jdh8N5QCjTj0FACfXAZQYVX67bUr00PHRlHmSppV65Q=
 =Thv+
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2023.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.07-rc3

.mailmap
- Fix Xilinx IDs

ZynqMP:
- Fix R5 split boot mode
- DT fixes - sync with Linux

Xilinx:
- Enable virtio and RNG support
- Enable ADI ethernet phy

SPI/Zynq:
- Fix dummy byte calculation
2023-05-16 09:10:57 -04:00
Michal Simek
b250bd6139 arm64: zynqmp: Fix User MTD partition size
The commit c8630167e0 ("arm64: zynqmp: Add mtd partition for secure OS
storage area") didn't update User partition size that's why size was beyond
actual device size.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Ashok Reddy Soma
66e8b8128b arm64: zynqmp: Fix issue of apps executing from R5 core 1
In current implementation, applications can execute only on R5 core 0.
The boot address for R5 core 1 is not supplied. Pass TCM address for
R5 core 1 based on the argument to fix the issue.

Remove incomplete comment.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
9b4d52b2e1 ARM: zynq: Sync Microzed board with Linux kernel
Fix model name, node locations and also add pinctrl description for usb.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
0da6d5a9e2 ARM: zynq: Switch from earlyprintk to earlycon
Switch to earlycon which is preffered over earlyprintk.
It is also sync with Linux kernel (zynq-microzed).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Neal Frager
d58acf644f arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode
The "zynqmp tcminit split" command should halt both cores and not just RPU1
when configuring the TCM memory for split mode.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:32:49 +02:00
Ralph Siemsen
e87c869db3 board: schneider: add RZN1 board support
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.

The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Ralph Siemsen
2156327846 ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:

* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD

Add basic support for this family, modeled on the existing RZA1.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Ralph Siemsen
4647a84b6c ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Ralph Siemsen
54232a7057 ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7ee ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Simon Glass
55171aedda dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.

With this, chromebook_link64 makes it through SPL.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Troy Kisky
d975da6363 arm: mach-imx: use CONFIG_$(SPL_)SATA instead of CONFIG_SATA
This avoid an error with enable_sata_clock when
defined(CONFIG_SATA) is changed to CONFIG_IS_ENABLED(SATA).

Signed-off-by: Troy Kisky <troykiskyboundary@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-10 16:45:42 -04:00
John Keeping
35c275065c rockchip: handle peripheral as well as otg dr_mode
The OTG port is identified by inspecting the "dr_mode" property which is
expected to be "otg" for this port.  But it will work just as well as a
device controller when dr_mode is set to "peripheral", which may be
required if the mode detection pin is not set up correctly and the
device controller needs to be programmed to override this.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
John Keeping
51c54080ff rockchip: use standard dr_mode parsing function
Instead of duplicating the string values here, use usb_get_dr_mode() to
handle the property lookup and converting the values to an enum.

This is implemented with a switch in preparation for the next patch
which adds extra handling for peripheral mode.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
afb4f55565 arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-order
use common one defined in rk356x-u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
74f162a1ea arm: dts: rk356x: Makefile: sort
sort alphanumerically.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
71a95e2efd arm: dts: rockchip: add Radxa ROCK 4C+
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+

Add support for Radxa ROCK 4C+ SBC.

Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec

Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.

Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
d0e62eeda8 arm: dts: rockchip: rock-pi-4: sync with Linux 6.3
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.

because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 20:30:12 +08:00
Tianling Shen
7000a60947 rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.

The device tree is taken from the kernel linux-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 18:58:25 +08:00
Chris Morgan
6cf6fe2537 board: rockchip: add Anbernic RGXX3 Series Devices
The Anbernic RGxx3 is a "pseudo-device" that encompasses the following
devices:

 - Anbernic RG353M
 - Anbernic RG353P
 - Anbernic RG353V
 - Anbernic RG353VS
 - Anbernic RG503

The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.

Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.

The common specifications for each device are:

 - Rockchip RK3566 SoC
 - 2 external SDMMC slots
 - 1 USB-C host port, 1 USB-C peripheral port
 - 1 mini-HDMI output
 - MIPI-DSI based display panel
 - ADC controlled joysticks with a GPIO mux
 - GPIO buttons
 - A PWM controlled vibrator
 - An ADC controlled button

All of the common features are defined in the devicetree synced from
upstream Linux.

TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:45:05 +08:00
Johan Jonker
55cd74d691 arm: stm32mp: spl: fix function with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
84404d8165 drivers: fix debug string with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
a12a73b664 drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
66a1d38c98 rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
The Rockchip SoC rk3288 has 2 types of device trees floating around.
A 64bit reg size when synced from Linux and a 32bit for U-boot.
A pre-probe function in the syscon class driver assumes only 32bit.
For other odd reg structures the regmap must be defined in the individual
syscon driver. Store rk3288 platdata in a regmap before pre-probe
during bind.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Tom Rini
eb59ece520 Merge tag 'fsl-qoirq-2023-5-5' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
fsl-ls1088a device tree update
enable DM_SERIAL for ten64
check for crypto node first in fdt_fixup_remove_jr
2023-05-05 09:33:29 -04:00
Mathew McBride
fb9df2c7c5 arm: dts: ten64: fix header typo and update copyright
Somehow, I managed to typo our company name in the U-Boot
and Linux kernel submissions.

Fix this and update the copyright year at the same time.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
7219c22e7f arm: dts: ten64: syncronise device tree with Linux
This synchronises the Linux device tree with U-Boot
(cp linux/..../fsl-ls1088a-ten64.dts uboot/..../fsl-ls1088a-ten64.dts),
as of Linux v6.2-rc5.

Missing from the U-Boot copy previously was the
Ethernet PCS definitions (required for linking with PHY in
Linux but not used by U-Boot) and various upstream
fixes and formatting changes.

The board microcontroller (which doesn't have a Linux driver)
has been moved to the -u-boot.dtsi, as well as the
spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux).

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
51b9254e02 arm: dts: fsl-ls1088a: copy all missing bindings from Linux
This is effectively:

cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \
   u-boot/arch/arm/dts/fsl-ls1088a.dtsi

Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
fd4f7b0158 arm: dts: fsl-ls1088a: move and sync existing bindings to be under /soc
Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under
the top level, until the DM_SERIAL implementation recently.

In this commit, remove any remaining devices (that were in U-Boot,
but not touched by previous patches in this series) to be under /soc,
updating to their upstream (Linux) bindings.

The bindings have been copied closest to their relative positions
in the Linux version, so the eventual result is that the U-Boot
and Linux fsl-ls1088a.dtsi will be identical.

The next commit will add the hardware bindings that were not
in U-Boot.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
1574500139 arm: dts: fsl-ls1088a: syncronise fsl-mc definition with Linux
This moves the fsl-mc device tree definition under the /soc
node, as well as adding interrupt and IOMMU definitions that
were not in U-Boot before.

There are slight differences between the two bindings
as we add a "simple-mfd" compatible to function
under U-Boot's driver model.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
ad558eff32 arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with Linux
Synchronise the MDIO controller definitions with Linux, so
the controllers will be usable when passing U-Boot's
control FDT to Linux.

This also adds the PCS (internal controller) definitions
which are not used by U-Boot.

Caveat: The kernel definition uses "fsl,fman-memac-mdio",
as with other members of the Layerscape family, but
U-Boot uses a different driver for the DPAA2
Family devices (LS1088/LS2088/LX2160). So
we use "fsl,ls-mdio" as the first compatible string
for these devices.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
10ff7e6b04 arm: dts: fsl-ls1088a: sync usb controller nodes with Linux
Synchronise the USB device tree definition with Linux, allowing
the U-Boot control FDT to be used to boot a Linux system with
working USB.

An extra compatible string, "fsl,layerscape-dwc3" is needed
for special handling in U-Boot, so has been added to the
-u-boot.dtsi file. It might be better to add this to the
Linux source bindings.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
38976a0666 arm: dts: fsl-ls1088a: move I2C nodes under "soc" and syncronize with Linux
U-Boot's definition for the I2C controllers did not contain any
clock information. This resulted in the I2C not functioning when
the U-Boot control FDT was passed to Linux.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
e8ab9840b5 arm: dts: fsl-ls1088a: move GPIO controller under "soc" per Linux
Move the GPIO controller definitions under the "soc" and in
the same relative position as the Linux kernel fsl-ls1088a.dtsi.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
2d6fce16c6 arm: dts: fsl-ls1088a: import CPU definition from Linux kernel
This is required for Linux to boot using the same FDT as
U-Boot (such as passing the control FDT to bootefi).

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
843f60b4e8 arm: dts: fsl-ls1088a: match Linux FDT by disabling PCIe by default
The Linux kernel fsl-ls1088a.dtsi disables (status="disabled")
all PCIe controllers by default, with the bootloader (i.e U-Boot)
enabling the appropriate controllers (specified by the board
reset control word/RCW) by FDT fixup.

However, U-Boot needs these controllers to be enabled
to be usable, which we can add in the u-boot only dtsi.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
f365e3cc91 arm: dts: fsl-ls1088a: sync PCIe controller definition with Linux
This moves the PCIe controller definitions under /soc and adopts
the same bindings (fsl,ls1088a-pcie) as Linux. Previously,
the format was different between the two versions.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
c2509a36d3 arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux
To synchronise the device tree in U-Boot with Linux, the GIC
(Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised
before changing any dependent components like PCIe and DPAA2/fsl-mc.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
d8a8b63397 arm: dts: fsl-ls1088a: move memory node into U-Boot specific file
The top-level "memory" node does not exist in the Linux
version of the fsl-ls1088a.dtsi file. Move it to the U-Boot
"tweak" file, so we can have an identical copy of
fsl-ls1088a.dtsi between the projects in the end.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
2591487865 arm: dts: fsl-ls1088a: move u-boot bootph tags into u-boot only files
This moves the bootph-all tags that were added in commit a593c1fec5
("arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all")
into a u-boot only include.

Due to the way the U-Boot device tree "tweak" system is setup[1],
we need to have a per-board <boardname>-u-boot.dtsi, which will
include the "fsl-ls1088a-u-boot.dtsi" tweaks.

By doing so, future updates to fsl-ls1088a.dtsi from upstream
(Linux kernel) can just be copied directly into the U-Boot tree,
without worrying about any extra data local to U-Boot.

Signed-off-by: Mathew McBride <matt@traverse.com.au>

[1] - https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#adding-tweaks-for-u-boot
The CONFIG_SYS_SOC, CONFIG_SYS_CPU and CONFIG_SYS_VENDOR
values are the same for the entire Layerscape family,
meaning there is no ability to create a LS1088A only
file here. But we will be adding per-board tweaks
later in any case.
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
8586a93868 armv8: fsl-layerscape: check for crypto node first in fdt_fixup_remove_jr
This a problem I found while updating the U-Boot fsl-ls1088a.dtsi
to match the Linux version.

fdt_fixup_remove_jr did not check whether there was a "crypto"
alias in the device tree before calling more fdt_* functions,
which resulted in a crash.

Fixes: a797f274
("ARMv8/sec_firmware : Update chosen/kaslr-seed with random number")

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Neha Malcom Francis
1e666512fb arm: dts: k3-j7200: ddr: Update to 0.6 version of DDR config tool
Update the DDR settings to those generated using 0.6 version of
Jacinto 7 DDRSS Register Configuration tool.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-05-04 19:51:59 -04:00
Neha Malcom Francis
b99d710fe0 arm: dts: k3-j721e: ddr: Update to 0.9.1 version of DDR config tool
Update the DDR settings to those generated using 0.9.1 version of
Jacinto 7 DDRSS Register Configuration tool.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-05-04 19:51:59 -04:00
Manorit Chawdhry
30a7ee87fd Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
On K3 HS-SE devices all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.

The K3 MCU Scratchpad for j721s2 was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.

Old map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c61f20 (approx)
│                STACK                │
├─────────────────────────────────────┤ 0x41c65f20
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x10000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41c76000)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
├─────────────────────────────────────┤ (0x41c80000)
│               DM DATA               │
├─────────────────────────────────────┤ (0x41c84130) (approx)
│                EMPTY                │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
				        (0x41cffbfc)

New map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c61f20 (approx)
│                STACK                │
├─────────────────────────────────────┤ 0x41c65f20
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x10000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41c76000)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
├─────────────────────────────────────┤ (0x41c80000)
│               DM DATA               │
├─────────────────────────────────────┤ (0x41c84130) (approx)
│                EMPTY                │
├─────────────────────────────────────┤ SYS_K3_MCU_SCRATCHPAD_BASE
│              SCRATCHPAD             │ (0x41cff9fc)
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200  │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
				        (0x41cffbfc)

Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-04 13:06:22 -04:00
Jan Kiszka
fca76cda28 arm: dts: iot2050: Include u-boot specific bits implicitly
Create *-u-boot.dtsi files for each target dtb of the IOT2050 series so
that we can drop the #include deviations from upstream dts[i] files
here.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-05-04 13:03:54 -04:00
Tom Rini
2440719d25 u-boot-imx-20230503
-------------------
 
 - Fixes for : pico-imx6ul, smegw01
 - new boards: DMSSE20, Reform 2
 - fix: get_boot_device, PLL video rate
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZFJGmw8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76ZirwCggyjQaqPg7dm0OAzfgD2gEoR/058AoI9jLtVd
 JaM9K5RoIu0V1AjBKXQe
 =l+ri
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20230503' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20230503
-------------------

- Fixes for : pico-imx6ul, smegw01
- new boards: DMSSE20, Reform 2
- fix: get_boot_device, PLL video rate

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211
2023-05-03 13:15:12 -04:00
Dzmitry Sankouski
a2612d7c55 starqltechn: use button keyboard driver
Button keyboard driver used to navigate bootmenu entries.

Add gpio buttons, button keyboard driver.
Add gpio keys dts bindings.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-03 09:05:24 -04:00
Yang Xiwen
33f19038cc arm: histb: hi3798mv200: add initial support for Hi3798MV200 HC2910-2AGHD05 board
A board with Hi3798MV200 SoC and various peripherals. Details are in the
board README.md.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-05-03 09:05:24 -04:00
Yang Xiwen
e90711f0e9 arm: add support for Hisilicon HiSTB family SoCs
First supported chip is hi3798mv200 (which is similar to Hi3798cv200
used by poplar).

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-05-03 09:05:24 -04:00
Tom Rini
7a3ee61f55 arm: Remove omap5_uevm board
This platform is unsupported by TI and was never widely distributed.  As
this is untested for a long while and missing some DM conversions,
remove it and related device tree files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-03 09:05:24 -04:00
Nitin Yadav
4d03f476a7 arm: mach-k3: Workaround errata ID i2331
Errata doc: https://www.ti.com/lit/pdf/sprz457
Errata ID i2331 CPSW: Device lockup when reading CPSW registers

Details: A device lockup can occur during the second read of any CPSW
subsystem register after any MAIN domain power on reset (POR). A MAIN
domain POR occurs using the hardware MCU_PORz signal, or via software
using CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR.
After these resets, the processor and internal bus structures may get
into a state which is only recoverable with full device reset using
MCU_PORz.
Due to this errata, Ethernet boot should not be used on this device.

Workaround(s): To avoid the lockup, a warm reset should be issued after
a MAIN domain POR and before any access to the CPSW registers. The warm
reset realigns internal clocks and prevents the lockup from happening.
Workaround above errata by calling do_reset() in case of cold boot in
order to trigger warm reset. This needs enabling SYSRESET driver in R5
SPL to enable TI SCI reset driver.

Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-05-03 09:05:24 -04:00
Daniel Golle
d7bb109900 board: mediatek: add Bananapi-R3 devicetree
Add board specific devicetree for Bananapi R3 SBC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2023-05-03 09:05:24 -04:00
Aradhya Bhatia
28e5e95bf8 arm: mach-k3: am62a7: Enable QoS for DSS
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.

The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.

With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.

The am62a qos files are auto generated from the k3 resource partitioning
tool.

Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, and section-14.1, "System Interconnect
Registers", provides the register descriptions.

[1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16

Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
2023-05-03 09:05:24 -04:00
Manorit Chawdhry
4b6e3d39cf arm: mach-k3: j7200: Fix firewall warnings at boot time
J721E and J7200 have same file j721e_init.c which had the firewall
configs for J721E being applied on J7200 causing the warnings. Split the
firewalls for both the boards to remove those warnings.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-03 09:05:24 -04:00
Manorit Chawdhry
b8ebf24e7f arm: mach-k3: common: don't reconfigure background firewalls
K3 devices have some firewalls set up by ROM that we usually remove so
that the development is easy in HS devices.

While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.

Since the background regions configured by ROM are in such a manner
that they allow all transactions, don't touch the background regions at
all.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-02 14:24:36 -04:00
Vignesh Raghavendra
fdb051ba3f arm: mach-k3: common: Default to non fitImage boot on HS-FS
Allow non fitImage bootflow on Field Securable (HS-FS) devices in
addition to GP, force fitImage boot only on Security enforced (HS-SE)
devices where signed images are necessary to maintain chain of trust.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-02 14:23:59 -04:00
Vladimir Zapolskiy
0e889a7c1b arm: dts: msm: add GENI SE QUP device tree node
On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.

The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
2023-05-02 14:23:59 -04:00
Konrad Dybcio
aa539d89e1 serial: msm-geni: Use upstream Linux bindings
The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.

[vzapolskiy: removed a ready change in the driver]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
2023-05-02 14:23:58 -04:00
Linus Walleij
6f63c296fe board: Add new Broadcom Northstar board
This adds a simple Northstar "BRCMNS" board to be used with
the BCM4708x and BCM5301x chips.

The main intention is to use this with the D-Link DIR-890L
and DIR-885L routers for loading the kernel into RAM from
NAND memory using the BCH-1 ECC and using the separately
submitted SEAMA load command, so we are currently not adding
support for things such as networking.

The DTS file is a multiplatform NorthStar board, designed to
be usable with several NorthStar designs by avoiding any
particulars not related to the operation of U-Boot.

If other board need other ECC for example, they need to
create a separate DTS file and augment the code, but I don't
know if any other users will turn up.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-02 14:23:58 -04:00
Linus Walleij
d3d9cd8ee1 arm: Add support for the Broadcom Northstar SoCs
The original Northstar is an ARM SoC series that comprise
BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
global timer and a few other things.

This series should not be confused with North Star Plus
(NSP) which is partly supported by U-Boot already.

The SoC is well supported by the Linux kernel and OpenWrt
as it is used in many routers.

Since we currently don't need any chip-specific quirks
and can get the system up from just the device tree, a
mach-* directory doesn't even need to be added, just
some small Kconfig fragments.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-02 14:23:58 -04:00
Linus Walleij
8a5122bfd3 arm: dts: Import device tree for Broadcom Northstar
This brings in the main SoC device tree used by the
Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
This is taken from the v6.3 Linux kernel.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-02 14:23:58 -04:00
Hugo Villeneuve
feb710b381 arm: imx8m: remove unused and obsolete board_fix_fdt() in SOC context
It doesn't seem appropriate for arch/SOC to use a board-level
functionality (CONFIG_OF_BOARD_FIXUP), because this prevents boards
that need to do FDT fixup from using that feature.

Also, this code is completely dead and useless (from comments by
Rasmus Villemoes on the mailing list):

  - No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP
  - The nodes which that function wants to disable don't even exist in
    the U-Boot copy of imx8mp.dtsi.

This code was introduced in commit 35bb60787b. It seems to be some
random import of code from downstream NXP U-Boot, with a commit
message that makes no sense in upstream context.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-05-02 10:57:32 +02:00
Tim Harvey
a48a824dba imx: fix get_boot_device() for imx8
commit 787f04bb6a ("imx: add USB2_BOOT type") broke get_boot_device()
for IMX8 which affects booting from SDP due to boot_instance being
non-zero.

Fix this by only using boot_instance for imx8ulp and imx9.

Fixes: 787f04bb6a ("imx: add USB2_BOOT type")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-05-02 10:57:32 +02:00
Dario Binacchi
1490292a07 imx6: clock: print real pixel clock rate
Add debug messages to print the real pixel clock rate, which may not be
the requested one.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-05-02 10:57:32 +02:00
Dario Binacchi
82863a99c0 imx6: clock: add support to get LCD pixel clock rate
Add the get_lcd_clk() function to get the LCD pixel clock rate.

The patch has been tested on imx6ul platform.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-05-02 10:57:32 +02:00
Dario Binacchi
41d7a7da80 imx6: clock: improve calculations to get the PLL video rate
During some tests to check the pixel clock rate in the transition from
U-Boot to the Linux kernel, I noticed that with the same configuration
of the registers the debug messages reported different rates.

The same Linux kernel calculations are now used to get the PLL video
rate.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-02 10:57:32 +02:00
Oliver Graute
3bc6257e80 imx: support i.MX8QM DMSSE20 a1 board
Add i.MX8QM DMSSE20 a1 board support

U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200)

Model: Advantech iMX8QM DMSSE20
Board: DMS-SE20A1 8GB
Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363
Boot:  USB
DRAM:  8 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:   eth0: ethernet@5b040000
Warning: ethernet@5b050000 (eth1) using random MAC address - 32:05:0c:f9:5e:10
, eth1: ethernet@5b050000
Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2023-05-02 10:57:32 +02:00
Heinrich Schuchardt
76ce66408d imx8mn: buffer overflow in low_drive_gpu_freq()
Avoid a buffer overflow if assigned-clock-rates has less than two elements.

Fixes: 98bcdf1635 ("imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-02 10:57:32 +02:00
Patrick Wildt
ebe2e0c309 board: mntre: imx8mq: Add MNT Reform 2 board support
The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-02 10:57:22 +02:00
Samuel Holland
09cbd3858f gpio: axp/sunxi: Remove virtual VBUS detection GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28 01:30:24 +01:00
Samuel Holland
9a4aa31ad5 sunxi: binman: Fix U-Boot offset when SPL is not 32 KiB
On sunxi boards, SPL looks for U-Boot at a 32 KiB offset, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL. See
the logic in spl_mmc_get_uboot_raw_sector() and spl_spi_load_image().

In two cases, the existing binman description mismatches the SPL code.
For 64-bit boards, binman would place U-Boot immediately following SPL,
even if SPL is smaller than 32 KiB. This can happen when SPL MMC support
is disabled (i.e. when booting from SPI flash).

In contrast, for 32-bit boards, binman would place U-Boot at 32 KiB,
even if SPL is larger than that. This happens because the 'offset'
property does not consider the size of previous entries.

Fix both issues by setting a minimum size for the SPL entry, which
exactly matches the logic in the SPL code. Unfortunately, this size must
be provided as a magic number, since none of the relevant config symbols
(SPL_PAD_TO, SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, and SYS_SPI_U_BOOT_OFFS)
are guaranteed to be defined in all cases.

Fixes: cfa3db602c ("sunxi: Convert 64-bit boards to use binman")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28 01:06:57 +01:00
Abdellatif El Khlifi
da458bcae5 corstone1000: add NVM XIP QSPI device tree node
add QSPI flash device node for block storage access

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2023-04-27 17:01:15 -04:00
Simon Glass
7755dc58af rockchip: Move to standard boot
Drop the distro-boot scripts and use standard boot instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-26 08:43:05 -04:00
Pali Rohár
7add47959e arm: omap3: Directly use SMC #1 in lowlevel_init.S
Since commit de39dc7162 ("arm: armv7-a: Compile and tune for armv7-a
instead of armv5") is used -march=armv7-a option for Omap3 platforms.

With directive ".arch_extension sec" it is possible for -march=armv7-a to
directly use ARM SMC instruction.

So enable ".arch_extension sec" in Omap3 lowlevel_init.S and replace hand
assembled ".word 0xe1600071" by "SMC #1".

Since commit 51d0638650 ("arm: omap-common: add secure smc entry") same
pattern is already used in arch/arm/cpu/armv7/omap-common/lowlevel_init.S.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-25 15:31:28 -04:00
Michal Simek
44cd761ad6 xen: Fix Kconfig dependencies
XEN config can be enabled by other platforms (even it doesn't need to make
sense) that's why fix dependencies. XEN (xenbus.c) requires sscanf (also
pvblock needs it). And PVBLOCK is inside drivers/xen folder which requires
XEN to be enabled.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-25 15:31:28 -04:00
Tom Rini
b5fc9f99d0 armv7: Use isb/dsb directly in start.S
Toolchains which do not directly support using "isb" and "dsb" directly
are no longer functionally supported in U-Boot. Furthermore, clang has
for a long time warned about using the alternate form that we were.
Update the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-25 15:31:27 -04:00
Tom Rini
a27c8ea7f7 arm: Centralize fixed register logic
When building for ARM64, we need to pass -ffixed-x18 and otherwise pass
-ffixed-r9. Rather than having this logic in two places, we can do this
once in arch/arm/config.mk. Further, while gcc will ignore being passed
both -ffixed-r9 and -ffixed-x18 and simply use -ffixed-x18, clang will
note that -ffixed-r9 is not used. Remove this duplication to also remove
the warning.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-25 15:31:27 -04:00
Tom Rini
c2e5eea38a arm: Only support ARM64_CRC32 when using GCC
Today, only gcc has __builtin_aarch64_crc32b (clang-16 does not, for
example). Make this option depend on CC_IS_GCC.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-25 15:31:27 -04:00
Pavel Skripkin
de0095b400 arm64: interrupts: print FAR_ELx on sync exceptions
Default synchronous exceptions handler prints only esr and register
dump. Sometimes it requiers to see an address which caused exceptions
to understand what's going on

ARM ARM in section D13.2.41 states that FAR_EL2 will contain meanfull
value in case of ESR.EC holds 0x20, 0x21, 0x24, 0x25, 0x22, 0x34 or
0x35. Same applies for EL1.

This patch adds function whivh determine current EL, gets correct FAR
register and prints it on panic.

Signed-off-by: Pavel Skripkin <paskripkin@gmail.com>
2023-04-25 15:31:27 -04:00
Jayesh Choudhary
2e43ba7805 arch: mach-k3: j721s2_init: Disable the firewalls
Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-25 15:31:27 -04:00
meitao
c1da6fdb5c armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present
u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does.
otherwise it will hang when enable mmu, that is what we encounter
in our SOC.

Signed-off-by: meitao <meitaogao@asrmicro.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 3bf38943ae
2023-04-25 15:31:27 -04:00
Marc Zyngier
836b8d4b20 arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present
In order to make invalidation by VA more efficient, set the largest
block mapping to 2MB, mapping it onto level-2. This has no material
impact on u-boot's runtime performance, and allows a huge speedup
when cleaning the cache.

Signed-off-by: Marc Zyngier <maz@kernel.org>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 417a73581a
2023-04-25 15:31:27 -04:00
Marc Zyngier
6cdf6b7a34 arm64: Use FEAT_HAFDBS to track dirty pages when available
Some recent arm64 cores have a facility that allows the page
table walker to track the dirty state of a page. This makes it
really efficient to perform CMOs by VA as we only need to look
at dirty pages.

Signed-off-by: Marc Zyngier <maz@kernel.org>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 3c433724e6
2023-04-25 15:31:27 -04:00
Christian Gmeiner
c0c56f64b3 arm: mach-k3: am642: move do_dt_magic() after sysfw loading
Makes it possible to use e.g mcu_spi0 for custom board detection.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-04-24 13:18:49 -04:00
Manorit Chawdhry
1e00e9be62 arm: mach-k3: common: re-locate authentication for atf/optee
For setting up the master firewalls present in the K3 SoCs, the arm64
clusters need to be powered on.

Re-locates the code for atf/optee authentication.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
53f02be32e arm: dts: k3-am625-r5-sk: add a53 cluster power
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
9a36735b0f arm: dts: k3-am62a7-r5-sk: add a53 cluster power domain node
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
3922cf6295 arm: dts: k3-am642-r5: add a53 cluster power domain node
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
7fe7920c5e arm: dts: k3-am642-r5-sk: add a53 cluster power domain node
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
dcdcbde2bb arm: dts: k3-j7200-r5: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
bdbd668853 arm: dts: k3-j721e-r5: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
ab3df39ffa arm: dts: k3-j721e-r5-sk: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
d363013e87 arm: dts: k3-j721s2-r5: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
f392860c2e arm: mach-k3: Remove empty sys_proto.h include
This header file is now empty, remove it.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
29627e81c6 arm: mach-k3: Move J721s2 SPL init functions to mach-k3
This matches AM64 and J721e and removes the need to forward
declare k3_spl_init(), k3_mem_init(), and check_rom_loaded_sysfw()
in sys_proto.h.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
ef538cc26e arm: mach-k3: Move sdelay() and wait_on_value() declaration
These probably should be in some system wide header given their use.
Until then move them out of K3 sys_proto.h so we can finish cleaning
that header out.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
ee12d64f2d arm: mach-k3: Remove unused fdt_disable_node()
This function is not used currently; remove it.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
e25fe5b275 arm: mach-k3: Add weak do_board_detect() to common file
This matches how it was done for pre-K3 TI platforms and it allows
us to move the forward declaration out of sys_proto.h.

It also removes the need for K3_BOARD_DETECT as one is free to simply
override the weak function in their board files as needed.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
f5e4944608 arm: mach-k3: Move sysfw-loader.h out of mach includes
This header is only used locally by K3 init files, no need to have it
up with the global mach includes. Move into local includes.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
2aee173ba0 arm: mach-k3: Make release_resources_for_core_shutdown() common
This function is the same for each device when it needs to shutdown
the R5 core. Move this to the common section and move the remaining
device specific ID list to the device hardware include.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
ca0973741d arm: mach-k3: Move J721e SoC detection out of common section
This belongs in the J721e specific file as it is the only place
this is used. Any board level users should use the SOC driver.

While here, move the J721e and J7200 SoC IDs out of sys_proto.h
and into hardware.h. Use a macro borrowed from Rockchip and add
the rest of the SoC IDs for completeness and later use.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
30e96a2401 arm: mach-k3: Move MSMC fixup to SoC level
The MSMC fixup is something we do based on SoC, not based on the board.
So this fixup does not belong in the board files. Move this to the
mach-k3 common file so that it does not have to be done in each board
that uses these SoCs.

We use ft_system_setup() here instead of ft_board_setup() since it is no
longer board level. Enable OF_SYSTEM_SETUP in the configurations that use
this to keep functionality the same.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
5cf850c162 Revert "arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes"
This reverts commit 5717294230. This
does not exist in upstream kernel.org and breaks boot on DRA7-EVMs.
Drop the same.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
db5a3bda50 arm: dts: keystone: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
a39f2a54dd arm: dts: omap: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
1fb69a07bc arm: dts: dm8x: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
f8ae3e605b arm: dts: dra7x: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
211b3d7263 arm: dts: am3x: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
1dfb028e04 arm: dts: am437x: Update to IOPAD to sync with v6.3-rc6
Several DTS files have been updated in the Linux kernel with a new
IOPAD macro. Sync for the same here.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
2657c52e08 arm: dts: am3x: Update IOPAD to PADCONF to sync with v6.3-rc6
Several DTS files have been updated in the Linux kernel with a new
PADCONF macro replacing the IOPAD version. Sync for the same here.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
25abf73466 arm: dts: keystone: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
5a6df00831 arm: dts: omap5x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
590f1d995a arm: dts: omap4x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
1346dc573b arm: dts: omap3x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
854d489e24 arm: dts: dra7x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
54efeef170 arm: dts: dm8x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
51b21c7985 arm: dts: am57x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
ad841299e7 arm: dts: am43x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
d30b2bf3b3 arm: dts: am3x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Tom Rini
328fdeb9c9 Merge tag 'u-boot-rockchip-20230421' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
2023-04-23 12:15:56 -04:00
Tom Rini
f2db24556f configs:
_ Add usb_pgood_delay for ST boards
 _ increase malloc size for pre-reloc for stm32mp15
 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15
 
 dts:
 _ Add QSPI support on STM32MP13x SoC family
 _ Add FMC support on STM32MP13x SoC family
 
 drivers/machine:
 _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
 _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
 _ rawnand: stm32_fmc2: remove unsupported EDO mode
 _ stm32mp: fix various array bounds checks
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmQ/s+kcHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pkQHEACnlVjvcMLuT+Fx9fA7
 sUfIoDnDQjRugyoEMts0tiAVabPps3rk2fVwuEG6LMRrF5qCTmexjB9HJ0zqIVZj
 FxOdP6fLL1629rJpRHQM1tGGmrzktxe/DRGH0VuVKhdH4MLtOWq/yC1XPfmeYh8/
 Lt+5uLIMIoBK0sZzNToDctN/KWPA6/UDrFZ7YmnIntL1F39dyiQ+jwvopZZVZ/+v
 uP/rwMDDCS7J0yCPa3WocSgOnhN3cE1amgFO7jJP43MBOntWsWmb4TWY+YVoxz1z
 PkZPRgQ2YHrFF3vtjL9rCiZSvelnRvSMaO+SZ7AmxNw6KR0ZC0SuCJY9glI257PA
 qHK6H7jzHW+Ti2+1NsY8bb8pG9Ewt0AtKc5nSmtbaCgikzdOfoFNOSBIKIZPhXp4
 7mxnRbPibK6a6TKIPFL82Ohxnt1hvr+ZD3V2yRdvx0ifMNB1J3F8Rpz4g5i1sPMQ
 PqKLAQB6cev8pfw+ItL0VDLhX8zAlCXyrXlxHT0osU88HecIt6ERpNpZZH9Gwp0c
 HbR8Sa3VYlG5EyMERmpsVZeA7pBGDtr3aKRRaqsTUrtltRkLOV8SBIXtGLLFiYFW
 eEShJO660+Lpb83WenV9A38I8f9qZS9AN+CSAE7EjBDGowAR21VyNcOStz09Yn9a
 a84w7wQygGm4mPQWlrOauq57XQ==
 =3Txq
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20230419' of https://source.denx.de/u-boot/custodians/u-boot-stm

configs:
_ Add usb_pgood_delay for ST boards
_ increase malloc size for pre-reloc for stm32mp15
_ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15

dts:
_ Add QSPI support on STM32MP13x SoC family
_ Add FMC support on STM32MP13x SoC family

drivers/machine:
_ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
_ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
_ rawnand: stm32_fmc2: remove unsupported EDO mode
_ stm32mp: fix various array bounds checks
2023-04-22 18:30:56 -04:00
FUKAUMI Naoki
7911f409ff arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb
enable regulators for usb host function

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 16:09:29 +08:00
Jonas Karlman
b564aa2740 rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported
mmc modes and pinctrl.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:55:29 +08:00
Jonas Karlman
72b05764c3 rockchip: rk3568-rock-3a: Enable support for more eMMC modes
Add supported mmc modes to rk3568-rock-3a device tree.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:55:29 +08:00
Chris Morgan
f89167bb74 ARM: dts: rockchip: rk3588s-u-boot: Add rng node
Add a node for the trng found on RK3588 SoCs.

Changes in V3:
 - Added Reviewed-By tag.

Changes in V2:
 - None

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2023-04-21 15:16:01 +08:00
Jonas Karlman
58c23015c9 rockchip: rk3588: Sync sdmmc node from linux-next
Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.

This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.

Fixes: 95c8656b72 ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
6737771600 rockchip: rk3588: Add support for sdmmc clocks in SPL
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.

The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.

This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.

Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
e1962a9efe rockchip: rk35xx: Enable fdtoverlay and kernel compression
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of
OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay
and kernel compression.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21 15:16:01 +08:00
Jonas Karlman
9f412347be rockchip: rk35xx: Fix boot with a large fdt blob
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
when it fails to parse the fdt blob being passed as the platform param.
An issue that was fixed in atf v2.4.

The vendor TF-A seem to suffer from a similar issue, and this prevents
booting when fdt blob is large enough to trigger this condition.

Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
NULL pointer instead of the fdt blob as the platform param.

This fixes booting Radxa ROCK 3A after recent sync of device tree.

Fixes: 073d911ae6 ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:01 +08:00
Jonas Karlman
f1e190a192 rockchip: rk3588-rock-5b: Fix sdmmc boot
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using
DMA and prints debug_uart messages.

  <debug_uart>

  <debug_uart>

  U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000)
  Trying to boot from MMC1
  ## Checking hash(es) for config config-1 ... OK
  ## Checking hash(es) for Image atf-1 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-1' image node
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and
remove DEBUG_UART_ANNOUNCE option to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
John Keeping
999680c4ed rockchip: misc: fix misc_read() return check
misc_read() is documented to return the number of bytes read or a
negative error value.  The Rockchip drivers currently do not implement
this correctly and instead return zero on success or a negative error
value.

In preparation for fixing the drivers, fix the condition here to only
error on negative values.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
98125086d6 arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4
Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
e16be4dd8b arm: dts: rockchip: rk3188-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3188-u-boot.dtsi
for now till a better method is found.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
fed814c088 arm: dts: rockchip: rk3066a-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi
for now till a better method is found.
Disable gpio6 as the driver gives an error code
on return as status.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
ba607e2b9a arm: dts: rockchip: rk3288: partial sync pwm nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
7c1ee7a848 arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
bf13676e0b arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
da5ae37fcd arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Johan Jonker
35e9e8aebf arm: dts: rockchip: rk3288: move io-domains nodes
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
John Keeping
24fea3f837 rockchip: rk3288: Use ft_system_setup instead of ft_board_setup
ft_board_setup() should be availble for use in board files but using it
in the rk3288 machine file blocks this functionality.

ft_system_setup() is the more appropriate function to use in a machine
definition.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Jonas Karlman
f7ad2912c6 rockchip: Use an external TPL binary on RK3588
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.

Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21 15:16:00 +08:00
Kever Yang
cf8658cdac board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.

Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel

dts Sync from Linux v6.2.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21 15:16:00 +08:00
Rasmus Villemoes
daf07215e8 stm32mp: fix various array bounds checks
In all these cases, the index on the LHS is immediately afterwards
used to access the array appearing in the ARRAY_SIZE() on the RHS - so
if that index is equal to the array size, we'll access
one-past-the-end of the array.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19 10:02:28 +02:00
Christophe Kerello
fa998c8aea ARM: dts: stm32: add FMC support on STM32MP13x SoC family
Add FMC support on STM32MP13x SoC family.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19 09:59:36 +02:00
Patrice Chotard
60edabc0a3 ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family
Add QSPI support on STM32MP13x SoC family

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19 09:51:49 +02:00
Karl Chan
00b3a0b872 ARM: dts: add support for Beelink GT1 Ultimate
Import the device-tree from linux-amlogic/for-next (Linux 6.3-rc1).

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Karl Chan <exxxxkc@getgoogleoff.me>
Link: https://lore.kernel.org/r/f5a8db4e-b2d0-e00a-cc4f-01a4f794c761@yahoo.com
[narmstrong: fixed imported dt file]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:08 +02:00
Christian Hewitt
67d5128df9 ARM: dts: add support for WeTek Hub and WeTek Play2
Import the dts files from linux-amlogic/for-next (Linux 6.4-rc1) and
add the old PHY reset bindings for dwmac to the u-boot.dtsi until we
support the new bindings in the PHY node. Without this the PHY is not
functional in u-boot or Linux.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-13-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:08 +02:00
Christian Hewitt
734ed0becc ARM: dts: add support for Radxa Zero2
Import the device-tree from linux-amlogic/for-next (Linux 6.4-rc1)
to support the Radxa-Zero2 board.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-10-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:08 +02:00
Christian Hewitt
a97e479120 ARM: dts: add support for BananaPi M2S
Import the device-tree from linux-amlogic/for-next (Linux 6.4-rc1)
and omit the NPU node from the A311D board variant dts as this is
not supported under U-Boot.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-7-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:08 +02:00
Christian Hewitt
7b95660dfc ARM: dts: add support for BananaPi M2-Pro
Import the board dts from the linux-amlogic/for-next (6.4-rc1)
branch. This involves spliting the BPI-M5 dts into a dtsi and
then reusing this for the M2-Pro.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323143142.780306-4-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:08 +02:00
Neil Armstrong
c1e1c1abdb ARM: meson: Add initial support for BPI-CM4 module with BPI-CM4IO baseboard
Add support for both the BananaPi BPI-CM4 module and the BananaPi
baseboard which is compatible with the RaspberryPi CM4IO baseboard.

The BananaPi BPI-CM4 module follows the CM4 specifications at [1],
but with a single HDMI port and a single DSI output.

The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.

[1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf

Link: https://lore.kernel.org/r/20230307-u-boot-cm4-v1-2-43f5a393cd37@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:07 +02:00
Neil Armstrong
02d138b7ca ARM: dts: import initial DT for BPI-CM4 module with BPI-CM4IO baseboard
Import initial support for BPI-CM4 module with BPI-CM4IO baseboard
from the Linux submission applied at [1].

The BananaPi BPI-CM4 module follows the CM4 specifications at [2],
but with a single HDMI port and a single DSI output.

The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.

[1] https://git.kernel.org/amlogic/c/0262f2736978b1763363224698f47112a148dab0
[2] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf

Link: https://lore.kernel.org/r/20230307-u-boot-cm4-v1-1-43f5a393cd37@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-04-17 11:06:07 +02:00
Tom Rini
12c1e57824 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Boot support for 4K Native disks (Pali)
- a38x: Perform DDR training sequence again for 2nd boot (Tony)
2023-04-14 10:50:55 -04:00
Pali Rohár
c62af15393 arm: mvebu: spl: Allow to build SATA kwbimage for 4K Native disks
Add a new config option CONFIG_MVEBU_SPL_SATA_BLKSZ for specifying block
size of SATA disk. This information is used during building of SATA
kwbimage and must be correctly set, otherwise BootROM does not load SPL.

For 4K Native disks CONFIG_MVEBU_SPL_SATA_BLKSZ must be set to 4096.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
2023-04-13 11:34:47 +02:00
Pali Rohár
fa06a6df65 arm: mvebu: spl: Do not hardcode SATA block size to 512
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13 11:34:24 +02:00
Andre Przywara
0a137ac501 sunxi: arm64: boot0.h: runtime check for RVBAR address
Some SoCs of the H616 family use a die variant, that puts some CPU power
and reset control registers at a different address. There are examples
of two instances of the same board, using different die revisions of the
otherwise same H313 SoC. We need to write to a register in that block
*very* early in the SPL boot, to switch the core to AArch64.

Since the devices are otherwise indistinguishable, let the SPL code read
that die variant and use the respective RVBAR address based on that.
That is a bit tricky, since we need to do that in hand-coded AArch32
machine language, shared by all 64-bit SoCs. To avoid build dependencies
in this mess, we always provide two addresses to choose from, and just
give identical values for all other SoCs. This allows the same code to
run on all 64-bit SoCs, and controls this switch behaviour purely from
Kconfig.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:22 +01:00
Andre Przywara
342abc1472 sunxi: boot0.h: allow RVBAR MMIO address customisation
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need
to program the 64-bit start code address into an MMIO mapped register
that shadows the architectural RVBAR register.
This address is SoC specific, with just two versions out there so far.
Now a third address emerged, on a *variant* of an existing SoC (H616).

Change the boot0.h start code to make this address a Kconfig
selectable option, to allow easier maintenance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:22 +01:00
Jernej Skrabec
deb77f18bf sunxi: Add TPR2 parameter for H616 DRAM driver
It turns out that some H616 and related SoCs (like H313) need TPR2
parameter for proper working. Add it.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:22 +01:00
Jernej Skrabec
4a967cb95f sunxi: Parameterize some of H616 DDR3 timings
Currently twr2rd, trd2wr and twtp are constants, but according to
vendor driver they are calculated from other values. Do that here too,
in preparation for later introduction of new parameter.

While at it, introduce constant for t_wr_lat, which was incorrectly
calculated from tcl before.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:22 +01:00
Jernej Skrabec
b3cb03cf79 sunxi: Parameterize "unknown feature" in H616 DRAM driver
Part of the code, previously known as "unknown feature", also doesn't
have constant values. They are derived from TPR0 parameter in vendor
DRAM code.

Let's move that code to separate function and introduce TPR0 parameter
here too, to ease adding new boards.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
ae6f66d5b5 sunxi: Parameterize bit delay code in H616 DRAM driver
These values are highly board specific and thus make sense to add
parameter for them. To ease adding support for new boards, let's make
them same as in vendor DRAM settings.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
83118bfa04 sunxi: Make bit delay function in H616 DRAM code void
Mentioned function result is always true and result isn't checked
anyway. Let's make it void.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
7742eac7af sunxi: Always configure ODT on H616 DRAM
Vendor H616 DRAM code always configure part which we call ODT
configuration. Let's reflect that here too.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
f221411caa sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
f35ec2105e sunxi: parameterize H616 DRAM ODT values
While ODT values for same memory type are similar, they are not
necessary the same. Let's parameterize them and make parameter same as
in vendor DRAM settings. That way it will be easy to introduce new board
support.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
cdb5aadd59 sunxi: cosmetic: Fix H616 DRAM driver code style
Fix code style for pointer declaration. This is just cosmetic change to
avoid checkpatch errors in later commits.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
7230bebfe3 sunxi: Fix write to H616 DRAM CR register
Vendor DRAM code actually writes to whole CR register and not just sets
bit 31 in mctl_ctrl_init().

Just to be safe, do that here too.

Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
f050069297 ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulator
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.

Update the device tree here because it does not exist in Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Tom Rini
187c7aba22 - fix building sandbox without SDL
- improve tegra DC driver to work with panel ops and implement
    native 180 degree panel rotation support
  - add T30 support to tegra DC driver
  - add DSI driver (based on mainline Linux one with minor
    adjustments, only T30 tested)
  - add get_display_timing ops to simple panel driver
  - extend simple panel driver to use it for MIPI DSI panels
    which do not require additional DSI commands for setup
 -----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCZDBwUw4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXL3+AJ9EkQKAWXZtlYdAOVl4/nzJnuTCAQCfY58zkDsw
 TnAlwmMGWFl3RF6yGXY=
 =uYUp
 -----END PGP SIGNATURE-----

Merge tag 'video-20230407' of https://source.denx.de/u-boot/custodians/u-boot-video

 - fix building sandbox without SDL
 - improve tegra DC driver to work with panel ops and implement
   native 180 degree panel rotation support
 - add T30 support to tegra DC driver
 - add DSI driver (based on mainline Linux one with minor
   adjustments, only T30 tested)
 - add get_display_timing ops to simple panel driver
 - extend simple panel driver to use it for MIPI DSI panels
   which do not require additional DSI commands for setup
2023-04-08 11:20:47 -04:00
Tom Rini
965f74b5b3 Merge branch 'master_sh/gen4/initial' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Initial R-Car Generation 4 support
2023-04-07 15:55:50 -04:00
Svyatoslav Ryhel
acbb871af5 video: tegra20: add DSI controller driver
Adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features
like ganged mode won't work. Driver is heavily based on
mainline Tegra DSI and re-uses much of its features.

Only T30 is supported for now but T20 support can be added
if any supported devices will be found.

Driver is wrapped as panel driver since Tegra DC driver supports
only panel drivers calls.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-04-07 19:52:54 +02:00
Svyatoslav Ryhel
a8f4f9f815 video: tegra-dc: pass DC regmap to internal devices
Internal video devices like DSI and HDMI controllers
require sending commands into DC register field.
To make this available, lets create platform data,
which is restricted to pass DC regmap only to
pre-defined devices.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-04-07 19:47:52 +02:00
Marcel Ziswiler
8dfeee651f tegra: lcd: video: integrate display driver for t30
On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-04-07 18:24:42 +02:00
Hai Pham
36b63c92c3 ARM: renesas: Add R8A779G0 V4H White Hawk board code
Add board code for R8A779G0 V4H White Hawk board.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
        Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
        Sort headers, use clrbits_le32(), use BIT macros where appropriate
        Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
2023-04-07 17:13:28 +02:00
Hai Pham
e4e242b296 ARM: renesas: Add R8A779G0 V4H Kconfig entry and PRR ID
Add Kconfig entry and PRR ID to support R8A779G0 V4H SoC.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update commit message]
2023-04-07 17:13:28 +02:00
Tho Vu
2ea98fc9f9 ARM: dts: renesas: Add R8A779G0 V4H White Hawk DTs
Add DTs for R8A779G0 V4H White Hawk CPU and BreakOut boards.

Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message
        Rename DTs to match Linux, which has dash between white-hawk]
2023-04-07 17:13:28 +02:00
Hai Pham
2ed192361e ARM: dts: renesas: Add R8A779G0 V4H DT extras
Add R8A779G0 V4H DT extras for U-Boot.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update compatible string to match latest upstream]
2023-04-07 17:13:28 +02:00
Phong Hoang
2c8941659d ARM: dts: renesas: Add R8A779G0 V4H DT
Add initial DT support for R8A779G0 (R-Car V4H). Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
2023-04-07 17:13:28 +02:00
Hai Pham
558d10620b ARM: renesas: Add R8A779F0 S4 Spider board code
Add board code for R8A779F0 S4 Spider board.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Synchronize configuration symbols which are now switched to Kconfig
        Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
	Sort headers, use clrbits_le32(), use BIT macros where appropriate
	Use CONFIG_SYS_CLK_FREQ for counter frequency instead of custom macro]
2023-04-07 17:13:28 +02:00
Hai Pham
8f098fd623 ARM: renesas: Add R8A779F0 S4 Kconfig entry and PRR ID
Add Kconfig entry and PRR ID to support R8A779F0 S4 SoC.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update commit message]
2023-04-07 17:13:28 +02:00
Hai Pham
d1bbe1bedd ARM: dts: renesas: Add R8A779F0 S4 Spider DTs
Add DTs for R8A779F0 S4 Spider CPU boards and Breakout boards.

Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
2023-04-07 17:13:28 +02:00
Hai Pham
d29bc87173 ARM: dts: renesas: Add R8A779F0 S4 DT extras
Add R8A779F0 S4 DT extras for U-Boot.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update compatible string to match latest upstream]
2023-04-07 17:13:28 +02:00
Hai Pham
b51f953053 ARM: dts: renesas: Add R8A779F0 S4 DT
Add initial DT for R8A779F0 S4 SoC. Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
2023-04-07 17:13:28 +02:00
Hai Pham
32e6893caf ARM: rmobile: Turn R-Car V3U into R-Car Gen4
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family [1]. Hence reflect this in related files, select appropriate
configuration options and split DT build into its own GEN4 entry.

[1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Deduplicate DTC_FLAGS addition using RCAR_64 symbol
        Update commit message]
2023-04-07 17:13:28 +02:00
Hai Pham
5a3b074255 ARM: rmobile: Add R-Car Generation 4 support
This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC.

In this version, reusing R-Car Gen3 lowlevel initialize routine [1]
and R-Car Gen3 memory map tables [2] .

[1] arch/arm/mach-rmobile/lowlevel_init_gen3.S
[2] arch/arm/mach-rmobile/memmap-gen3.c

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: - Enable DTO support by default
        - Sort the Kconfig lists
	- Select RCAR_64 Kconfig option to pull in all the shared
	  Kconfig options with Gen3, and use where applicable to
	  deduplicate entries.
	- Fix reference [2] typo in commit message
	- Drop config options moved to Kconfig, rename rest to CFG_
	  accordingly to synchronize with upstream changes. Drop
	  removed CONFIG_VERY_BIG_RAM.
        - Move board size limit to arch/Kconfig
	- Move GICR_BASE to headers instead of common config]
2023-04-07 14:33:46 +02:00
Francis Laniel
5ffcf7c590 arm: lib: add __gnu_thumb1_case_si
The assembly for __gnu_thumb1_case_si was taken from upstream gcc and adapted
as width suffix was removed for the add instruction [1].

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
[1] 4f181f9c7e/libgcc/config/arm/lib1funcs.S (L2156)
Acked-by: Pali Rohár <pali@kernel.org>
Acked-by:  Tony Dinh <mibodhi@gmail.com>
2023-04-06 19:10:08 -04:00
Tom Rini
b0b77fdf3d Merge tag 'fsl-qoriq-2023-4-6' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
convert NXP LS1028A RDB and QDS to DM_SERIAL
enable DM_SERIAL for ls1088a
sync serial nodes with linux for lx2160a/ls1088a
2023-04-05 22:19:57 -04:00
Tom Rini
0916377b83 u-boot-imx-next-20230404
------------------------
 
 CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15887
 
 - boards : DH-Electronics, Toradex, imx8mp-beacon-kit
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZCv6mg8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76ZIrACfVH9xA0tG8UO87Ap+7h2J4PJU3+gAnA9QhfwC
 vF42NNf2OlnNEVee1jGz
 =vlEI
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-next-20230404' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-next-20230404
------------------------

CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15887

- boards : DH-Electronics, Toradex, imx8mp-beacon-kit
2023-04-04 09:50:13 -04:00
Ioana Ciornei
f2ac9f6a17 arch: arm: dts: fsl-lx2160a.dtsi: tag serial nodes with bootph-all
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:47 +08:00
Ioana Ciornei
dea0f1a27f arch: arm: dts: fsl-lx2160a.dtsi: sync serial nodes with Linux
Sync the serial nodes of the LX2160A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Ioana Ciornei
853493b9f9 arch: arm: dts: fsl-lx2160a.dtsi: move the serial nodes under soc
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Ioana Ciornei
677fb95372 arch: arm: dts: fsl-lx2160a.dtsi: add an 'soc' node
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Ioana Ciornei
a593c1fec5 arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Ioana Ciornei
571c49789d arch: arm: dts: fsl-ls1088a.dtsi: sync serial nodes with Linux
Sync the serial nodes of the LS1088A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Ioana Ciornei
2b7d2c236b arch: arm: dts: fsl-ls1088a.dtsi: move the serial nodes under soc
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Ioana Ciornei
204d574fe4 arch: arm: dts: fsl-ls1088a.dtsi: add an 'soc' node
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-04 17:31:46 +08:00
Adam Ford
ab53bd43db arm64: imx: Add support for imx8mp-beacon-kit
Beacon Embedded has an i.MX8M Plus development kit which consists
of a SOM + baseboard.  The SOM includes Bluetooth, WiFi, QSPI, eMMC,
and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual
Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet
PHY.  The device trees are already queued for inclusion in Linux 6.3.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-04-04 09:40:25 +02:00
Marek Vasut
302f7e80b9 ARM: dts: imx: Add support for Data Modul i.MX8M Plus eDM SBC
Add support for Data Modul i.MX8M Plus eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR, USB.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-04-04 09:35:39 +02:00
Marek Vasut
240a274f0f ARM: dts: imx: Add WDT reboot bindings on DH i.MX6 DHSOM
Add WDT reboot bindings on DH i.MX6 DHSOM to permit the platform
to reboot via WDT in U-Boot. These are custom U-Boot bindings,
hence they are placed in -u-boot.dtsi .

Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-04-04 09:35:39 +02:00
Luca Ceresoli
95942f99a7 arm: imx: add u-boot-nand.imx to boot from NAND without SPL
U-Boot can be booted from NAND without SPL by prepending the DCD header to
the actual U-Boot binary. However this requires prepending 1024 bytes to
u-boot.imx (DCD + u-boot.bin).

There is already a similar target to build spl/u-boot-nand-spl.imx, add the
same option for no-SPL boot.

Tested on i.MX6ULL.

The resulting layout of u-boot-nand.imx is:

 - Offset 0x0000 (0 KiB): padding
 - Offset 0x0400 (1 KiB): DCD header
 - Offset 0x1000 (4 KiB): u-boot.bin

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2023-04-04 09:35:39 +02:00
Tom Rini
8ca4202595 mx6sx-udoo-neo-basic-u-boot.dtsi: Correct to bootph-all
Updating this was missed in the merge of the next branch back in to
master.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-04-03 20:48:24 -04:00
Tom Rini
288fe30a23 Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-04-03 16:45:41 -04:00
Sinthu Raja
1f77f9176e arm: dts: k3-j721e-sk-u-boot: fix boot on j721e SK
J721e SK has been broken since at least March 2022.

The main-navss and mcu-navss nodes were renamed and this caused the
A72 SPL to fail early in the boot even before the serial port was
enabled. Fix this.

A later patch series between v2022.07 and v2022.10 additionally broke
boot on this board by introducing hbmc nodes which are not present on
this board. The right fix is to disable these by default in the SOC
dtsi file, but for now we can also disable them in the u-boot dtsi.

With both these fixed, we can now boot the j721e SK board fully from
mainline u-boot.

Fixes: 58d61fb5a7 ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support")
Fixes: 297daac43a ("arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node")
Reported-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
[gadiyar@ti.com: update commit description]
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Cc: Bryan Brattlof <bb@ti.com>
2023-04-03 14:54:16 -04:00
Fabio Estevam
8b6de0545f pico-imx6: Pass the mmc alias to fix boot regression
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.

After the sync with Linux in commit d0399a46e7 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.

This causes a boot regression in which the eMMC card cannot be found anymore.

Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.

Fixes: d0399a46e7 ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-04-03 10:14:34 -04:00
Tom Rini
942ac73afc u-boot-imx-next-20230331 for next
---------------------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
 
 i.MX patches queued for next:
 
 - Conversions to DM_SERIAL
 - Fixes for Toradex boards
 - Gateworks Boards
 - i.MX8ULP
 - EQoS support / fixes, changes in boards
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZCaU0Q8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76YCKgCgk4OueoIggmes+Ccj8bu1BcQbrfYAoJAgMeKE
 It0hrVAifD62TPb2rmHt
 =hFVG
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-next-20230331' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

u-boot-imx-next-20230331 for next
---------------------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819

i.MX patches queued for next:

- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
2023-03-31 12:50:34 -04:00
Marek Vasut
f9cec6da28 arm64: imx8mm: imx8mn: imx8mp: Drop FEC GPR[1] board workaround
The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:51:55 +02:00
Marek Vasut
599474120a arm64: imx8mp: Drop EQoS GPR[1] board workaround
The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:51:33 +02:00
Marek Vasut
c7ea9612df arm64: dts: imx8mp: Drop EQoS clock workaround
The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:49:49 +02:00
Rasmus Villemoes
2f3cf91693 ARM: imx: imx8mp: fix enable_i2c_clk
In order for i2c_num==4 and 5 to stay invalid for non-imx8mp SOCs, the
i2c_ccgr[] array must be sized by the number of initializers present,
not with a hard-coded 6 which would implicitly initialize the last two
elements with zeroes.

Also, the bounds check is off-by-one.

Fixes: c92c3a4453 "ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP"
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-03-30 13:47:04 +02:00
Marek Vasut
4bdc3524d7 net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
f9e950b9bf net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:04 +02:00
Marek Vasut
158456089c net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.

The adjustment here is modeled after STM32MP15xx clock handling
in this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 13:47:03 +02:00
Andrejs Cainikovs
161be93a46 Revert "imx: imx8x: colibri: switch to binman"
This reverts commit bdadc140a1.

We do not want this, see [1].

[1] https://lore.kernel.org/all/56cf058164f331ce99ce75b0751b825ee2e07fc0.camel@toradex.com/

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-03-30 10:55:10 +02:00
Marek Vasut
3a125806f1 ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM on PDK3
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK3 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 08:40:27 +02:00
Marek Vasut
0a98696a0f arm64: dts: imx8mp: Do not delete PHY nodes on i.MX8MP DHCOM PDK2
The PHY nodes may be activated via DTO in case another SoM variant
is populated into the development kit. Do not delete the nodes.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 08:40:27 +02:00
Marek Vasut
4007103350 arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 08:40:27 +02:00
Marek Vasut
aa1de631e5 arm64: dts: imx8mp: Add EQoS RMII pin mux on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 08:40:27 +02:00
Marek Vasut
c46fa5d6c3 arm64: dts: imx8mp: Adjust EQoS PHY address on i.MX8MP DHCOM
The current variant of the SoM has LAN8740Ai PHY connected to EQoS
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 08:40:27 +02:00
Pali Rohár
babc1806c2 arm: mvebu: Define all options for AXP BOOT_FROM_* macros
Definitions are according to the MV78460 Hardware Specifications.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Pali Rohár
3ac1a064e7 arm: mvebu: Define all BOOTROM_ERR_MODE_* macros
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting), 0xA (parallel or SPI NAND booting), 0xB (SATA booting) and 0xE
(SD / eMMC booting).

Meaning of these values matches TRACE_* macros from Marvell soc_spec.h file:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/soc_spec.h

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Pali Rohár
4f67eba733 arm: mvebu: Define all options for A38x BOOT_FROM_* macros
Disassembling A385 BootROM binary reveal how BootROM interprets strapping
pins for Boot Device Mode. All possible options are:

0x00..0x07 -> Parallel NOR
0x08..0x15 -> Parallel NAND
0x16..0x17 -> Parallel NOR
0x18..0x25 -> Parallel NAND
0x26..0x27 -> SPI NAND
0x28..0x29 -> UART xmodem
0x2a..0x2b -> SATA
0x2c..0x2d -> PCI Express
0x2e..0x2f -> Parallel NOR
0x30..0x31 -> SD / eMMC
0x32..0x39 -> SPI NOR
0x3a..0x3c -> Parallel NOR
0x3d..0x3e -> UART debug console
0x3f       -> Invalid

Note that Boot Device Mode Options in A38x Hardware Specifications is
incomplete.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Pali Rohár
7ba084c7f8 arm: mvebu: Convert BOOT_FROM_* constants to function macros
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Pali Rohár
4642bb3e76 arm: mvebu: Remove A38x BOOT_FROM_SATA 0x22 constant
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Pali Rohár
2360409d9c arm: mvebu: Remove A38x BOOT_FROM_UART_ALT 0x3f constant
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.

Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051 ("ARM: mach-mvebu: handle fall-back to UART boot").

So there is no need to define BOOT_FROM_UART_ALT constant and special
handling for it anymore, remove it.

This change effectively revers commit f3a88e2ca1 ("arm: mvebu: fix boot
from UART on ClearFog Base").

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Pali Rohár
785f5379e0 arm: mvebu: Cleanup get_boot_device() code
Show correct information in debug() output and use correct names for variables.

No functional change.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Martin Rowe
c733fe91e4 arm: mvebu: clearfog: Detect MMC vs SDHC and fixup fdt
[upstream of vendor commit 19a96f7c40a8fc1d0a6546ac2418d966e5840a99]

The Clearfog devices have only one SDHC device. This is either eMMC if
it is populated on the SOM or SDHC if not. The Linux device tree assumes
the SDHC case. Detect if the device is an eMMC and fixup the device-tree
so it will be detected by Linux.

Ported from vendor repo at https://github.com/SolidRun/u-boot

Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Martin Rowe
e3104d81f6 arm: mvebu: clearfog: Fix MMC detection
A388 Clearfog MMC is either SD Card or eMMC with different behaviour for
both. Setting the device to non-removable in the u-boot.dtsi allows both
to correctly detect the device.

Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-30 07:05:20 +02:00
Ye Li
20ba9f252a imx: spl_imx_romapi: Get and print boot stage
Get and print boot stage through ROM API in SPL

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-30 00:45:39 +02:00
Fabio Estevam
5fddcbbdab pico-imx6: Pass the mmc alias to fix boot regression
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.

After the sync with Linux in commit d0399a46e7 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.

This causes a boot regression in which the eMMC card cannot be found anymore.

Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.

Fixes: d0399a46e7 ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-03-29 22:27:39 +02:00
Ye Li
569dab887b imx: ele_ahab: Remove OEM Secure World Closed print
The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9.
So remove it from lifecycle print.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
fe787f277d imx: ele_ahab: confirm lifecycle before closing the part
Before moving the lifecycle to OEM closed, confirm the lifecycle is
OEM open, otherwise cancel to move forward the lifecycle.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
040fc2be78 misc: sentinel: s400_api: Use new command request definitions
Remove legacy command definitions, change to use new ELE_xxx command
request.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
07816f086c imx: ahab: Move imx9 and imx8ulp AHAB support together
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since
both of them use same sentinel ELE APIs

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
619d0c2c18 imx93: ahab: Get and decode AHAB events
For ahab_status command, support to get and decode AHAB events

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
76c184fe3a misc: sentinel: s400_api: Add get_events API
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
74a39c15c3 imx8ulp_evk: Change to use DDR driver
Remove the DDR initialization codes from board and enable the iMX8ULP
DDR driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
f9288c60f4 imx: sentinel: Update S400 API get info message structure
From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
f2940f3e80 imx: imx8ulp: Update clocks to meet max rate restrictions
Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency
restrictions. Detail clock rate changes in the patch:

PLL3 PFD2: 389M -> 324M
PLL3 PFD3: 336M -> 389M
PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD)
PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD)

PLL4 PFD0: 792M -> 594M
PLL4 PFD2: 792M -> 316.8M

NIC_AP:    96M (ND) -> 192M,  48M (LD) -> 96M
NIC_LPAV:  198 (ND) -> 192M,  99M (LD) -> 96M

USDHC0:    PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD)
USDHC1:    PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
USDHC2:    PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
cf35290258 imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting.  So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.

We have to configure necessary PDAC and MSC for SPL before DDR
initialization.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Peng Fan
13a95dc81b imx: imx8ulp: upower: make code cleaner
To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Peng Fan
90e43bc136 imx: imx8ulp: upower: replace magic number with macro
The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.

Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
4e08a510d2 imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
e01d1b1e30 imx: imx8ulp: Reconfigure MRC3 for SRAM0 access
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
84f7da68e0 imx: imx8ulp: configure XRDC for DRAM access from S400
Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
8b956bdddd imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.

The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.

The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
aec9b5de44 imx: imx8ulp: Remove the TRDC configure from A35
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
237ce9b6c4 imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
bf9866d265 imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part
Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
f3272355cd imx: imx8ulp: Get chip revision from Sentinel
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:41 +02:00
Ye Li
9d89dcfcb1 imx: imx8ulp: Fix MU device probe failure
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
2023-03-29 20:15:41 +02:00
Christian Gmeiner
e44657ed74 arm: mach-k3: introduce generic board detction kconfig option
For non TI boards it is not possible to enable the do_board_detect()
call as TI_I2C_BOARD_DETECT is defined in board/ti/common/Kconfig.

I want to use do_board_detect() to dectect boards and properties based
on some SPI communication with a FPGA.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-03-29 13:30:28 -04:00
Jan Kiszka
352ed65df7 iot2050: Add support for configuring M.2 connector
The M.2 slots of the related IOT2050 variant need to be configured
according to the plugged cards. This tries to detect the card using the
M.2 configuration pins of the B-key slot. If that fails, a U-Boot
environment variable can be set to configure manually. This variable is
write-permitted also in secure boot mode as it is not able to undermine
the integrity of the booted system.

The configuration is then applied to mux the serdes and to fix up the
device tree passed to or loaded by the bootloader. The fix-ups are
coming from device tree overlays that are embedded into the firmware
image and there also integrity protected. The OS remains free to load
a device tree to which they do not apply: U-Boot will not fail to boot
in that case.

Based on original patch by Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-03-29 11:58:26 -04:00
chao zeng
ed57c40783 arm: dts: iot2050: Add support for M.2 variant
Add support for the M.2 board based on the iot2050 advanced board.
The board has two m.2 connectors, one is B-keyed, the other E-keyed.
The B-key slot can connect 5G/SSD devices, and E-key can be used for
WIFI/BT devices.

This variant is covered by PG2 firmware image.

Signed-off-by: chao zeng <chao.zeng@siemens.com>
[Jan: align DT to kernel, polish wording]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-03-29 11:58:26 -04:00
Jan Kiszka
367b1bf2ce arm: dts: iot2050: Optionally embed OTP programming data into image
Use external blob otpcmd.bin to replace the 0xff filled OTP programming
command block to create a firmware image that provisions the OTP on
first boot. This otpcmd.bin is generated from the customer keys using
steps described in the meta-iot2050 integration layer for the device.

Based on original patch by Baocheng Su.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-03-29 11:58:26 -04:00
Jan Kiszka
430e9f6666 arm: dts: iot2050: Allow verifying U-Boot proper by SPL
Add hashes and configuration signature stubs to prepare verified boot
of main U-Boot by SPL.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-29 11:58:26 -04:00
Jan Kiszka
6ac9131702 iot2050: Update firmware layout
The latest version of the binary-only firmware parts come in a combined
form of FSBL and sysfw containers. This implies some layout changes to
the generated firmware image but also makes handling of artifacts much
simpler (4 files less). The env locations will not change, just the
space reserved for U-Boot will shrink from 4 to 3 MB - still plenty of
space left in practice.

Adjust configuration and documentation accordingly.

Along this change, add a new reservation for update commands of the
user-controlled OTP part. A specific userspace tool will fill it, and
the FSBL will evaluate it during boot. This reservation will use 64K of
the former sysfw section.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-03-29 11:58:26 -04:00
Su Baocheng
ffbd5b29a4 arm: dts: iot2050: Use the auto generator nodes for fdt
Refactor according to the entry `fit: Entry containing a FIT` of
document tools/binman/README.entries.

As the generator uses the device tree name for the config description,
board_fit_config_name_match requires a small adjustment as well.

Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[Jan: re-add now required CONFIG_OF_LIST, update config matching]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-29 11:58:26 -04:00
Su Baocheng
ea0f45d187 board: siemens: iot2050: Split the build for PG1 and PG2
Due to different signature keys, the PG1 and the PG2 boards can no
longer use the same FSBL (tiboot3). This makes it impossible anyway to
maintaine a single flash.bin for both variants, so we can also split the
build.

A new target is added to indicates the build is for PG1 vs. PG2 boards.
Hence now the variants have separated defconfig files.

The runtime board_is_sr1() check does make no sense anymore, so remove
it and replace with build time check.

Documentation is updated accordingly. New binary artifacts are already
available via meta-iot2050.

Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[Jan: refactor config option into targets, tweak some wordings]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-03-29 11:58:25 -04:00
Fabio Estevam
565681e596 imx6sx-udoo-neo-basic: Introduce the u-boot.dtsi
After the conversion to DM_SERIAL in commit 01f372d8d6 ("udoo_neo:
Select DM_SERIAL and drop iomux board level init") the SPL log is gone
and the U-Boot proper log becomes incomplete:

Core:  80 devices, 18 uclasses, devicetree: separate
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial@2020000
Out:   serial@2020000
Err:   serial@2020000
Net:   eth0: ethernet@2188000
Hit any key to stop autoboot:  0

Introduce the u-boot.dtsi file that passes the u-boot,dm-pre-reloc
properties to the relevant nodes so that UART can be used early in SPL.

With this change, the complete SPL and U-Boot messages are seen again.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-03-28 10:58:16 -04:00
Tom Rini
82b896c1d0 Revert "rockchip: Fix early use of bootph props"
While this change is correct for v2023.04 it is not correct for next
(where this is right now) nor post-v2023.04.

This reverts commit 8653e5d3b7.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27 15:20:19 -04:00
Tom Rini
605bc145f9 Merge branch 'master' into next 2023-03-27 15:19:57 -04:00
Tom Rini
3be95cc292 rockchip: Use BOOTSTD_DEFAULTS if not DISTRO_DEFAULTS
When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd)
we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd
the general distro boot functionality will still work.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-27 11:16:04 -04:00
Simon Glass
2b9cc7845c rockchip: Disable DISTRO_DEFAULTS for rk3399 boards
These board have moved to standard boot but the old 'distro_bootcmd'
command is still active. Disable DISTRO_DEFAULTS to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
2023-03-27 11:16:04 -04:00
Tom Rini
78f67f11a9 Merge branch 'rpi-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
2023-03-24 17:00:41 -04:00
Vincent Fazio
85bdd28d2b mmc: bcm2835-host: let firmware manage the clock divisor
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.

Leverage this ability if the firmware supports it.

Adapted from the following raspberrypi Linux kernel commit:

  bcm2835-sdhost: Firmware manages the clock divisor
  08532d242d

Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-03-24 14:43:20 +00:00
Vincent Fazio
0a36afa823 arm: rpi: fallback to max clock rate for MMC clock
In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1,
the GET_CLOCK_RATE mailbox property was changed to return the last
value set by SET_CLOCK_RATE.

https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502

Due to this change in firmware behavior, bcm2835_get_mmc_clock now
returns a clock rate of zero since we do not issue SET_CLOCK_RATE.
This results in degraded MMC performance.

SET_CLOCK_RATE fixes the clock to a specific value and disables scaling
so is not an ideal solution.

Instead, fallback to GET_MAX_CLOCK_RATE in bcm2835_get_mmc_clock if
GET_CLOCK_RATE returns zero.

Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-03-24 14:43:20 +00:00
Pali Rohár
ae60fc6902 arm: kirkwood: Move internal registers in arch_very_early_init() function
Same change as was done for mvebu in commit 5bb2c550b1 ("arm: mvebu: Move
internal registers in arch_very_early_init() function") but for kirkwood.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-24 13:11:47 +01:00
Tony Dinh
21f622779f arm: mvebu: Set common SPI flash default speed and mode
CONFIG_SF_DEFAULT_SPEED is used in SPL SPI to configure and probe the
flash device during DM SPI uclass probing process, if the
spi-max-frequency is not available in the DTB. Currently the max
frequency is not available, because of the probing mechanism in SPI
uclass has not been fully updated to DM.

The CONFIG_SF_DEFAULT_SPEED is set to 1Mhz if a board defconfig
does not specify it. This speed is too slow and result in a few
seconds delay while the u-boot image is loaded from flash. Based on a
survey of the device tree specifications for MVEBU boards, a sane default
value should be 10Mhz. The default of 10Mhz enables an almost
instantaneously loading of the u-boot image.

Note that this patch depends on this patch series (has been merged to
u-boot-marvell/next):
https://lists.denx.de/pipermail/u-boot/2023-March/511038.html

- RESEND: correct spelling of SF_DEFAULT_MODE

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-24 08:43:42 +01:00
Tom Rini
16d82d7bfa spl: Add function prototype for spl_mmc_get_uboot_raw_sector
We did not add a prototype for spl_mmc_get_uboot_raw_sector to
include/spl.h before, so add and document one now. Correct the incorrect
prototype in board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c and
ensure that we have spl.h where we define a non-weak
spl_mmc_get_uboot_raw_sector as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-22 15:22:48 -04:00
Tom Rini
f5131e80fc arm: Correct cpu_reset function prototype on some platforms
Some platforms were not including <cpu_func.h> which sets the prototype
for reset_cpu, and in turn had it set wrong. Correct these cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-22 15:22:48 -04:00
Kamlesh Gurudasani
d3882531c3 arm: mach-k3: am62: move scratch board area to HSM RAM
On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.

So, move scratch board area to HSM RAM.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-03-22 12:51:09 -04:00
Tony Dinh
c5f4cdb8eb console: Use flush() before panic and reset
To make sure the panic and the reset messages will go out, console flush() should be used.
Sleep periods do not work in early u-boot phase when timer driver is not initialized yet.

Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-22 12:51:08 -04:00
Tom Rini
5e207b8517 - odroid-go-ultra: setup PMIC regulators at board init
-----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmQa3BYACgkQd9zb2sjI
 SdGVgg/+MFYKg2vZ0jtx193b19GkCp9K5FC91jYg+oJGtWDT59b1EGoZNMC/LOmk
 iaCr2Srm4hcTKadlNrUlj2C7c1CMHMzsLuXBtC36ia1zXZR34WW28xOaWltEFfB9
 js1ryME9fB00iMwUWloCWrccluAVpP7dcoDMA4cmTqMIFAUQr+MHQw+Rd2ogqXIo
 gzYfh3xshEZdi4oUqtkojTXgLx1PLZt5sgozHbJeAw+eY78Tk9PIaSoAh5Nzlh3I
 3agzTRFY+pDVQ1YBhnS0U/eV1oevtcXbASFJs1MR4g5bGPOF4HTyiEisUNdD6rQZ
 IMDNCNwo2lgCaTaWVZuxb6jfPshMru8koSgKqccIDnMS9D4yhNvmLmFKi4J/1zJl
 ofvA0vUuO3FoaJzGGky6gnLO4jDj4MR4J0RCrOMZQptSJMiV5LXwZIp48g2xsDJZ
 RS7CLqPfy0VQ0TlJpcOTrEyETEqXsUdEs0rsxvbLWpybFNnGGzpqaP7pVCTTV/Xp
 AKKZr/fCaR2Ud2UG5NUn9vTpdUuerZS7580N3v6WbCqkgm/2/LoA5YEH37PxsCR1
 qu1063/EH/sI3yxRtSUamngWuU17IARyQ9Xl2/1vI1QalfEtGZdDNWTNB9OZkM9U
 fDIAbvI57QSzECweTHzP4dNUowbP1C9sW/3r/M1rr5zM3kSh9Zg=
 =Vk9R
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20230322' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- odroid-go-ultra: setup PMIC regulators at board init
2023-03-22 09:21:41 -04:00
Johan Jonker
d35a1392c5 arm: dts: rockchip: rk3188-radxarock-u-boot: remove timer compatible replacement
The Rockchip timer driver has been renamed after the fall back compatible.
There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi
anymore, so remove.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 14:12:01 +08:00
Vasily Khoruzhick
9fe2e4ab93 Revert "arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates"
This reverts commit 5bec4b0de7851a254fb4447b3599a60f95550141.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 14:12:00 +08:00
Jonas Karlman
e259f39a12 rockchip: rk3588: Add boot device detection
Enable SPL on RK3588 to detect which device it was booted from.
Fixes use of same-as-spl in u-boot,spl-boot-order prop.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 13:20:21 +08:00
Jonas Karlman
073d911ae6 rockchip: rk3568-rock-3a: Sync device tree from linux
Running U-Boot from eMMC on a ROCK 3 Model A result in the following:

  U-Boot SPL 2023.04-rc3 (Mar 11 2023 - 17:24:48 +0000)
  Trying to boot from MMC1
  Card did not respond to voltage select! : -110
  spl: mmc init failed with error: -95
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

The sdhci node is missing in board device tree, sync device tree from
linux v6.3-rc1 to fix booting from eMMC. Also disable sdmmc2 and uart1
nodes related to using a WiFi and BT module in the M2 slot.

Fixes: b44c54f600 ("arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 13:17:28 +08:00
Jonas Karlman
42f67fb51c rockchip: rk3568: Fix boot device detection
The boot source node path for emmc is using the old sdhci name.
Replace with correct mmc name and also add same-as-spl to boot order.

Fixes: 0d61f8e5f1 ("rockchip: rk3568: add boot device detection")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 13:17:28 +08:00
Jonas Karlman
8653e5d3b7 rockchip: Fix early use of bootph props
Running U-Boot on a ROCK 3 Model A result in the following:

  No serial driver found
  resetting ...
  no sysreset
  ### ERROR ### Please RESET the board ###

Replace bootph- props with u-boot,dm- props to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19 13:17:28 +08:00
Marek Vasut
f54eb0bad6 ARM: rmobile: Split R-Car Gen3 into separate Kconfig from common 64bit options
There are multiple shared Kconfig options between R-Car Gen3 and Gen4.
Keep the common options in Kconfig.64 and move the R-Car Gen3 specific
options into separate Kconfig.rcar3 . The Kconfig.rcar3 contains SoC
and board list, which is limited to R-Car Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
ef72c1ef29 ARM: rmobile: Introduce CONFIG_RCAR_64 symbol
Introduce common Kconfig symbol for 64bit R-Car platforms and move
common configuration options into it. This is preparatory patch to
prevent duplication of Kconfig lists later on, when Gen4 is added.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
dec699bea7 ARM: rmobile: Factor out SYS_SOC Kconfig option
Pull the SYS_SOC Kconfig option to avoid duplication of this option
in Kconfig.{32,64,rza1} . The default value is the same, so just set
it in one location.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
6f152a713c ARM: rmobile: Sort R-Car Gen3 Kconfig lists
Sort the 'imply' and 'select' lists in R-Car Gen3 Kconfig options.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
7fe9d7d1ba ARM: rmobile: Convert ifdef in rmobile_get_prr() to IS_ENABLED()
Switch ifdef in rmobile_get_prr() to IS_ENABLED() macro.
The CONFIG_RCAR_GEN3 will never have SPL counterpart, so
the IS_ENABLED() macro is the right one here. No functional
change, except for improved build test coverage.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
143bd4e315 ARM: renesas: Enable DTO support by default on R-Car Gen3
All R-Car Gen3 defconfigs present in U-Boot do enable DTO support,
enable it for all of R-Car Gen3 by default in Kconfig instead, so
that no new boards would miss this functionality.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 11:59:45 +01:00
Tom Rini
cefd0449d6 Xilinx changes for v2023.07-rc1
cmd:
 - Print results in hex instead of dec in smc command
 
 firmware:
 - Cover missing ZYNQMP_FIRMWARE dependencies
 
 fpga:
 - fix loads for unencrypted use case
 
 relocation
 - Add support for BE systems
 
 spi:
 - Fix xilinx_spi init reset sequence
 
 arasan nand:
 - Remove hardcoded bbt option
 - Set ofnode value
 
 xilinx:
 - Enable SMC command
 - Fix some sparse issues
 
 zynqmp:
 - Remove cdns,zynq-gem compatible string
 - Add optee node
 - Some DT cleanups
 
 zynq:
 - Some DT cleanups
 
 microblaze
 - Remove MANUAL_RELOC option
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZBHCfAAKCRDKSWXLKUoM
 ITcJAKCF8qmG8QPZptsoMj4dcceoaSJnyACfSGgH4ytUY8QkP8Yp0Z5U8HoY6a8=
 =eAAF
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2023.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.07-rc1

cmd:
- Print results in hex instead of dec in smc command

firmware:
- Cover missing ZYNQMP_FIRMWARE dependencies

fpga:
- fix loads for unencrypted use case

relocation
- Add support for BE systems

spi:
- Fix xilinx_spi init reset sequence

arasan nand:
- Remove hardcoded bbt option
- Set ofnode value

xilinx:
- Enable SMC command
- Fix some sparse issues

zynqmp:
- Remove cdns,zynq-gem compatible string
- Add optee node
- Some DT cleanups

zynq:
- Some DT cleanups

microblaze
- Remove MANUAL_RELOC option
2023-03-16 12:18:30 -04:00
Tom Rini
e63828bf35 Merge tag 'fsl-qoriq-next-2023-3-14' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Enable DM_SERIAL for freescale ls2080a
Drop non DM_ETH code for freescale:
  lx2160a/ls2080rdb/ls2080aqds/ls1088a
2023-03-16 12:17:48 -04:00
Tom Rini
016d414682 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Per Andre:

[T]hese two patches containing just devicetree updates for
Allwinner boards.
I was still hoping for a review, since we cannot import the files from
the Linux tree verbatim, but managed to write some filter script that
convinced me that the changes are fine.
The files are from Linux v6.2-rc2, but are identical to the v6.2
release.
2023-03-15 12:01:55 -04:00
Tom Rini
a5faa4a9eb Prepare v2023.04-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmQPxXsACgkQFHw5/5Y0
 tyzRWgwAlpwF0u0Xtfs+isnwy/2wb1uMKSeZTiMWkP8he48DX/+db1LHyxnb5apX
 5ULLLKnxZGDviFNw6F/Vuq/BlL8aK+K6wJm+HxdN4Df+sQZgP0kZVnZH1DcDGyJ7
 2I5mYxXCQiRfl3lG8uHdfQyGT5BOm1ZYTIBgXPzpdp/PS6Es74aIHfHS4UdsnpZ2
 dw5APUHnXsSeycbvgiZZEAQphRGplTgSmEDLZTCHD6+oIFoyJVMRr4QWc+KjYPR8
 MgfykqaITO7xKg1V2GwEWJA7LpU4L3HrK+8upSjdx0kfKw4jZoBTU5LE3dnk+6fz
 rgisMfyDGZ+w467uk9BSAO9smRRRI7GFMSkvi+kMQtVCFWCSaddkfYPlpFu1PND7
 nHfxkzoIjxeEOG8yIFF8P199w2lEorKTxlXuNBStfozvAz1wfhgq3o3WQGpvDmqF
 E+FoC7t73qVu6DVMiCXCOyUYNyI7d1tFlUhlbZPVCelVL8RX3JjMF/0uhLsOSDMc
 s4z/6fVq
 =xK+J
 -----END PGP SIGNATURE-----

Merge tag 'v2023.04-rc4' into next

Prepare v2023.04-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-14 12:06:35 -04:00
Ioana Ciornei
5a2416fd99 arch: arm: dst: fsl-ls2080a.dts: tag serial nodes with bootph-all
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
1d37e4a18b arch: arm: dst: fsl-ls2080a.dts: sync serial nodes with Linux
Sync the serial nodes of the LS208XA RDB/QDS boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
853c3124cd arch: arm: dst: fsl-ls2080a.dtsi: move the serial nodes under soc
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
c445af6d23 arch: arm: dst: fsl-ls2080a.dtsi: add an 'soc' node
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
73ba0371a1 arm: dts: ls1088a-rdb: replace 'xgmii' with '10gbase-r'
When the first device tree description was added for the ethernet nodes,
the 2 10G ports on the LS1088ARDB were wrongly described as 'xgmii'.

Fix this by replacing the two last occurrences of 'xgmii' in the device
trees of the Layerscape DPAA2 devices.

Fixes: 68c7c008e8 ("arm: dts: ls1088ardb: add DPMAC and PHY nodes")
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:27 +08:00
Neil Armstrong
de58694f0d ARM: meson: odroid-go-ultra: setup PMIC regulators are board init
The Odroid Go Ultra has 2 chained PMICs RK818 and RK818, and needs
an adjustment on the BUCK and LDO values.

Add the initial regulators values in -u-boot.dtsi & run the initial
regulator setup in a new odroid-go-ultra board.

Proper OTG and BOOST regulators are still missing to have USB-A
host properly working.

Link: https://lore.kernel.org/r/20230210-u-boot-odroid-go-ultra-pmics-setup-v1-1-1f16d62b76af@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-03-14 09:03:16 +01:00
Tam Nguyen
ae08097faa ARM: dts: renesas: Enable sysinfo on R-Car D3 Draak
Enable support for sysinfo on R-Car D3 Draak board. The sysinfo is used
e.g. to access and decode board-specific information and then in turn
used by board-info to print those information.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77995.dtsi already.
        Drop status = "okay" from EEPROM node.
	Add dts: tag.
	Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10 17:46:09 +01:00
Tam Nguyen
c8eaebb426 ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-I
Add new sysinfo IDs for R-Car V3H Condor/Condor-I .

Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is
used e.g. to access and decode board-specific information and then in
turn used by board-info to print those information.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already.
        Drop status = "okay" from EEPROM node.
	Add dts: tag.
	Update the commit message, note the new sysinfo IDs.
	Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10 17:46:09 +01:00
Algapally Santosh Sagar
cc24fd7859 xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Ashok Reddy Soma
9b669ef059 arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default
By default enable nand-on-flash-bbt DT flag, so that driver always refers
to the bad block table(bbt) present on the flash device.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Ashok Reddy Soma
9207c48491 arm64: dts: zynqmp: Fix nand dt node
DC3 nand node is not correct, it is showing all partitions under
controller node directly. Create two sub nand nodes with partitions for
each.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
dd0ebfe8a4 arm64: zynqmp: Remove comment about gem spec in kv260
The latest SOM specification doesn't enforce certain MIO lines allocated
for ethernet or ethernet controller itself. That's why remove comment about
it which is likely there from early version of specification.
Also removed the same comment from pinctrl node. It is clear that it has to
be defined for different carrier cards.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9406377bf2c391ac0200670511bd6b0edb097c96.1676880543.git.michal.simek@amd.com
2023-03-09 13:15:00 +01:00
Ilias Apalodimas
89f0f14fe2 arm64: zynqmp: Add an OP-TEE node to the device tree
Since the zynqmp boards can run upstream OP-TEE, and having the DT node
present doesn't cause any side effects add it in case someone tries to
load OP-TEE.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Link: https://lore.kernel.org/r/20230216133921.866786-1-ilias.apalodimas@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
cfa39857de ARM: zynq: Comment interrupt names IRQs for pl330
pl330 DT yaml description doesn't define interrupt-names property that's
why comment it but keep it as comment.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8e5a921c16efe09030fda036340186c11dd990bf.1672908030.git.michal.simek@amd.com
2023-03-09 13:15:00 +01:00
Krzysztof Kozlowski
89c3a5151c ARM: dts: zynq-7000: drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a chance of
mistakes) in DTS is pointless.  Additionally the DTS used always wrong
property names which causes DT schema check failures - the bindings
documented 'dma-channels' and 'dma-requests' properties without leading
hash sign.

Reported-by: Rob Herring <robh@kernel.org>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220430121902.59895-2-krzysztof.kozlowski@linaro.org
2023-03-09 13:15:00 +01:00
Krzysztof Kozlowski
4837ff416d ARM: dts: xilinx: align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220616005333.18491-31-krzysztof.kozlowski@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
5331845db4 ARM: zynq: Use recommended dma-controller name instead of dmac
Use standard name for dma controller. Issue is reported by dtbs_check as
dmac@f8003000: $nodename:0: 'dmac@f8003000' does not match
'^dma-controller(@.*)?$'

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5637d7e3464fbc1b2b269a7df35e24edc2c8d4ac.1672908080.git.michal.simek@amd.com
2023-03-09 13:15:00 +01:00
Michael Grzeschik
06ba3c252f arm64: zynqmp: Enable hs termination flag for USB dwc3 controller
Since we need to support legacy phys with the dwc3 controller,
we enable this quirk on the zynqmp platforms.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Link: https://lore.kernel.org/r/20221023215649.221726-1-m.grzeschik@pengutronix.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Krzysztof Kozlowski
b4b2f7bb5f arm64: dts: xilinx: align LED node names with dtschema
The node names should be generic and DT schema expects certain pattern:

  xilinx/zynqmp-zcu100-revC.dtb: leds: 'vbus-det' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221125144136.477171-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
a09d9278a5 xilinx: dts: Remove cdns,zynq-gem
cdns prefix was deprecated and replaced by xlnx one in upstream Linux. Also
U-Boot driver has been updated to support new compatible string that's why
it is time to remove it and deprecate it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:14:59 +01:00
Andre Przywara
29c579a249 arm: semihosting: replace inline assembly with assembly file
So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about one instruction, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
  to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
  we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
  those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
  pointer land in the right registers.

This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembly file.
This is much more readable and robust.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-03-06 17:06:17 -05:00
Devarsh Thakkar
885198536d am62a7: dts: Enable full 4GB LPDDR4
AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
but only 2GB was enabled early.

Enable full 4GB memory by updating the latter 2GB memory region
which gets mapped to 0x0880000000 i.e. DDR16SS0_SDRAM as referred in
Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].

[1] : https://www.ti.com/lit/zip/spruj16
Logs: https://gist.github.com/devarsht/e85b6af89c01ddadb3a62f3e5f196af8

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
2023-03-06 17:06:17 -05:00
Kunihiko Hayashi
051451ad83 ARM: dts: uniphier: Sync DT with Linux v6.2
Synchronize devicetree sources with Linux v6.2.

- Use GIC interrupt definitions
- Add reg properties in USB-glue and SoC-glue node
- Fix node names to follow the generic names list in DT specification
- Add L2 cache and AHCI nodes
- Update nand and pcie nodes
- And some trivial fixes

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
2023-03-06 17:05:40 -05:00
Kunihiko Hayashi
e800263d56 ARM: dts: uniphier: Switch USB node to the original
UniPhier DT applies its own USB node for U-Boot due to the USB driver
constrains. After solving this issue, u-boot allows the original USB node.

After switching USB node, synchronization of USB node with Linux becomes
possible.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
2023-03-06 17:05:40 -05:00
Patrick Delaunay
c6c2fe9936 ARM: remove SPEAR entry in makefile
As the lastest spear directories are removed, delete the associated entry
in Makefile.

Fixes: 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-06 17:03:56 -05:00
Marc Zyngier
94d30f476f arm64: Reduce PT size estimation complexity
count_required_pts()'s complexity is high if mappings are not using the
largest possible block size (due to some other requirement such as tracking
dirty pages, for example).

Let's switch to a method that follows the pattern established with
the add_map() helper, and make it almost instantaneous instead of
taking a large amount of time if 2MB mappings are in use instead of
1GB.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
  upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 5d756d147e
Link: 6be9330601
2023-03-06 17:03:56 -05:00
Marc Zyngier
41e2787f5e arm64: Reduce add_map() complexity
In the add_map() function, for each level it populates, it iterates from
the root of the PT tree, making it ineficient if a mapping needs to occur
past level 1.

Instead, replace it with a recursive (and much simpler) algorithm
that keeps the complexity as low as possible. With this, mapping
512GB at level 2 goes from several seconds down to not measurable
on an A55 machine.

We keep the block mappings at level 1 for now though.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
  upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 96ad729cf4
Link: 6be9330601
2023-03-06 17:03:56 -05:00
Pierre-Clément Tosi
c55c2a8565 arm64: Initialize TLB memory if CMO_BY_VA_ONLY
Memory used to hold the page tables is allocated from the top of RAM
with no prior initialization and could therefore hold invalid data. As
invalidate_dcache_all() will be called before the MMU has been
initialized and as that function relies indirectly on the page tables
when using CMO_BY_VA_ONLY, these must be in a valid state from their
allocation.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased
  to the upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: e3ceef4230
2023-03-06 17:03:55 -05:00
Marc Zyngier
46dc542870 arm: cpu: Add optional CMOs by VA
Exposing set/way cache maintenance to a virtual machine is unsafe, not
least because the instructions are not permission-checked but also
because they are not broadcast between CPUs. Consequently, KVM traps and
emulates such maintenance in the host kernel using by-VA operations and
looping over the stage-2 page-tables. However, when running under
protected KVM, these instructions are not able to be emulated and will
instead result in an exception being delivered to the guest.

Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select
this option and perform by-VA cache maintenance instead of using the
set/way instructions.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <willdeacon@google.com>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some
  checkpatch warnings. Rebased to upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: db5507f47f
Link: 2baf54e743
2023-03-06 17:03:55 -05:00
Andre Przywara
8e2c0ee3ba sunxi: dts: arm64: update devicetree files from Linux v6.2-rc2
Sync the devicetree files from the Linux kernel repo, v6.2-rc2.
This is covering the 64-bit SoCs, from arch/arm64/boot/dts/allwinner.

This enables GPU power management in the kernel for the H6, enables
Bluetooth on the Pinebook, and adds USB to the H616 devices (just
for newer Linux kernels at the moment, U-Boot support is pending).

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-05 23:33:14 +00:00
Andre Przywara
6621cc85f7 sunxi: dts: arm: update devicetree files from Linux v6.2-rc2
Sync the devicetree files from the Linux kernel repo, v6.2-rc2.
This is covering the 32-bit SoCs, from arch/arm/boot/dts.

This enables some new devices for the F1C100s family, though this is of
little relevance to U-Boot itself.
The H3 gains the "phys" property for the first USB controller, which
prevents an error message when U-Boot's USB stack comes up, and allows
using this port in host mode.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-05 23:33:13 +00:00
Simon Glass
06a1edda6c freescale: Drop old pre-DM_ETH code
This is used by ls1021atwr_sdcard_ifc_SECURE_BOOT with split config, but
is not needed anymore, since Ethernet migration is complete. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-03 09:49:02 -05:00
Tom Rini
f4ee45e2a0 s5p: Remove empty arch_misc_init
We don't need to provide an empty arch_misc_init function here, we can
just not enable the hook.

Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2023-03-02 15:32:25 -05:00
Tom Rini
1df23b405a mvebu: Drop empty arch_misc_init
If this hooks is needed later, it should be added and populated for
real.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-02 15:32:25 -05:00
Tom Rini
f47c765dbe mvebe: Drop ARCH_MISC_INIT from alleycat 5
In this platform, arch_misc_init doesn't perform any real function. The
call to get_soc_type_rev has no lasting side effects.

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2023-03-02 15:32:25 -05:00
Tom Rini
cfc4c0c2f3 imx9: Remove ARCH_MISC_INIT
We don't need an empty function, we can just not enable the hook we
don't use.

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-02 15:32:25 -05:00