mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
arm: dts: k3-j721e: ddr: Update to 0.9.1 version of DDR config tool
Update the DDR settings to those generated using 0.9.1 version of Jacinto 7 DDRSS Register Configuration tool. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Neha Malcom Francis
Tom Rini
parent
bebe2f66f5
commit
b99d710fe0
1 changed files with 75 additions and 74 deletions
|
|
@ -1,11 +1,12 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
|
||||
* This file was generated on 09/25/2020
|
||||
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
|
||||
* This file was generated on 07/17/2022
|
||||
*/
|
||||
|
||||
#define DDRSS_PLL_FHS_CNT 10
|
||||
#define DDRSS_PLL_FREQUENCY_0 27500000
|
||||
#define DDRSS_PLL_FREQUENCY_1 1066500000
|
||||
#define DDRSS_PLL_FREQUENCY_2 1066500000
|
||||
|
||||
|
|
@ -16,10 +17,10 @@
|
|||
#define DDRSS_CTL_04_DATA 0x00000000
|
||||
#define DDRSS_CTL_05_DATA 0x00000000
|
||||
#define DDRSS_CTL_06_DATA 0x00000000
|
||||
#define DDRSS_CTL_07_DATA 0x00002710
|
||||
#define DDRSS_CTL_08_DATA 0x000186A0
|
||||
#define DDRSS_CTL_07_DATA 0x00002AF8
|
||||
#define DDRSS_CTL_08_DATA 0x0001ADAF
|
||||
#define DDRSS_CTL_09_DATA 0x00000005
|
||||
#define DDRSS_CTL_10_DATA 0x00000064
|
||||
#define DDRSS_CTL_10_DATA 0x0000006E
|
||||
#define DDRSS_CTL_11_DATA 0x000681C8
|
||||
#define DDRSS_CTL_12_DATA 0x004111C9
|
||||
#define DDRSS_CTL_13_DATA 0x00000005
|
||||
|
|
@ -32,11 +33,11 @@
|
|||
#define DDRSS_CTL_20_DATA 0x02011001
|
||||
#define DDRSS_CTL_21_DATA 0x02010000
|
||||
#define DDRSS_CTL_22_DATA 0x00020100
|
||||
#define DDRSS_CTL_23_DATA 0x0000000A
|
||||
#define DDRSS_CTL_24_DATA 0x00000019
|
||||
#define DDRSS_CTL_23_DATA 0x0000000B
|
||||
#define DDRSS_CTL_24_DATA 0x0000001C
|
||||
#define DDRSS_CTL_25_DATA 0x00000000
|
||||
#define DDRSS_CTL_26_DATA 0x00000000
|
||||
#define DDRSS_CTL_27_DATA 0x02020200
|
||||
#define DDRSS_CTL_27_DATA 0x03020200
|
||||
#define DDRSS_CTL_28_DATA 0x00005656
|
||||
#define DDRSS_CTL_29_DATA 0x00100000
|
||||
#define DDRSS_CTL_30_DATA 0x00000000
|
||||
|
|
@ -53,7 +54,7 @@
|
|||
#define DDRSS_CTL_41_DATA 0x1B60008B
|
||||
#define DDRSS_CTL_42_DATA 0x2000422B
|
||||
#define DDRSS_CTL_43_DATA 0x000A0A09
|
||||
#define DDRSS_CTL_44_DATA 0x040006DB
|
||||
#define DDRSS_CTL_44_DATA 0x0400078A
|
||||
#define DDRSS_CTL_45_DATA 0x1E161104
|
||||
#define DDRSS_CTL_46_DATA 0x10012458
|
||||
#define DDRSS_CTL_47_DATA 0x1E161110
|
||||
|
|
@ -61,7 +62,7 @@
|
|||
#define DDRSS_CTL_49_DATA 0x02030410
|
||||
#define DDRSS_CTL_50_DATA 0x2C040500
|
||||
#define DDRSS_CTL_51_DATA 0x082D2C2D
|
||||
#define DDRSS_CTL_52_DATA 0x14000D0A
|
||||
#define DDRSS_CTL_52_DATA 0x14000E0A
|
||||
#define DDRSS_CTL_53_DATA 0x04010A0A
|
||||
#define DDRSS_CTL_54_DATA 0x01010004
|
||||
#define DDRSS_CTL_55_DATA 0x04585808
|
||||
|
|
@ -69,15 +70,15 @@
|
|||
#define DDRSS_CTL_57_DATA 0x00003131
|
||||
#define DDRSS_CTL_58_DATA 0x00010100
|
||||
#define DDRSS_CTL_59_DATA 0x03010000
|
||||
#define DDRSS_CTL_60_DATA 0x00000E08
|
||||
#define DDRSS_CTL_61_DATA 0x000000BB
|
||||
#define DDRSS_CTL_60_DATA 0x00001008
|
||||
#define DDRSS_CTL_61_DATA 0x000000CE
|
||||
#define DDRSS_CTL_62_DATA 0x00000256
|
||||
#define DDRSS_CTL_63_DATA 0x00002073
|
||||
#define DDRSS_CTL_64_DATA 0x00000256
|
||||
#define DDRSS_CTL_65_DATA 0x00002073
|
||||
#define DDRSS_CTL_66_DATA 0x00000005
|
||||
#define DDRSS_CTL_67_DATA 0x00030000
|
||||
#define DDRSS_CTL_68_DATA 0x00950010
|
||||
#define DDRSS_CTL_67_DATA 0x00040000
|
||||
#define DDRSS_CTL_68_DATA 0x00950012
|
||||
#define DDRSS_CTL_69_DATA 0x00950408
|
||||
#define DDRSS_CTL_70_DATA 0x00400408
|
||||
#define DDRSS_CTL_71_DATA 0x00120103
|
||||
|
|
@ -88,7 +89,7 @@
|
|||
#define DDRSS_CTL_76_DATA 0x041E100B
|
||||
#define DDRSS_CTL_77_DATA 0x100B0401
|
||||
#define DDRSS_CTL_78_DATA 0x0001041E
|
||||
#define DDRSS_CTL_79_DATA 0x000F000F
|
||||
#define DDRSS_CTL_79_DATA 0x00100010
|
||||
#define DDRSS_CTL_80_DATA 0x02660266
|
||||
#define DDRSS_CTL_81_DATA 0x02660266
|
||||
#define DDRSS_CTL_82_DATA 0x03050505
|
||||
|
|
@ -111,13 +112,13 @@
|
|||
#define DDRSS_CTL_99_DATA 0x00000000
|
||||
#define DDRSS_CTL_100_DATA 0x00040005
|
||||
#define DDRSS_CTL_101_DATA 0x00000000
|
||||
#define DDRSS_CTL_102_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_103_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_104_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_105_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_106_DATA 0x00002EC0
|
||||
#define DDRSS_CTL_102_DATA 0x00003380
|
||||
#define DDRSS_CTL_103_DATA 0x00003380
|
||||
#define DDRSS_CTL_104_DATA 0x00003380
|
||||
#define DDRSS_CTL_105_DATA 0x00003380
|
||||
#define DDRSS_CTL_106_DATA 0x00003380
|
||||
#define DDRSS_CTL_107_DATA 0x00000000
|
||||
#define DDRSS_CTL_108_DATA 0x0000051D
|
||||
#define DDRSS_CTL_108_DATA 0x000005A2
|
||||
#define DDRSS_CTL_109_DATA 0x00081CC0
|
||||
#define DDRSS_CTL_110_DATA 0x00081CC0
|
||||
#define DDRSS_CTL_111_DATA 0x00081CC0
|
||||
|
|
@ -173,9 +174,9 @@
|
|||
#define DDRSS_CTL_161_DATA 0x00000000
|
||||
#define DDRSS_CTL_162_DATA 0x00000000
|
||||
#define DDRSS_CTL_163_DATA 0x00000000
|
||||
#define DDRSS_CTL_164_DATA 0x000A0000
|
||||
#define DDRSS_CTL_165_DATA 0x000D0005
|
||||
#define DDRSS_CTL_166_DATA 0x000D0404
|
||||
#define DDRSS_CTL_164_DATA 0x000B0000
|
||||
#define DDRSS_CTL_165_DATA 0x000E0006
|
||||
#define DDRSS_CTL_166_DATA 0x000E0404
|
||||
#define DDRSS_CTL_167_DATA 0x00D601AB
|
||||
#define DDRSS_CTL_168_DATA 0x10100216
|
||||
#define DDRSS_CTL_169_DATA 0x01AB0216
|
||||
|
|
@ -190,15 +191,15 @@
|
|||
#define DDRSS_CTL_178_DATA 0x56000000
|
||||
#define DDRSS_CTL_179_DATA 0x27270056
|
||||
#define DDRSS_CTL_180_DATA 0x0F0F0000
|
||||
#define DDRSS_CTL_181_DATA 0x00000000
|
||||
#define DDRSS_CTL_182_DATA 0x00840606
|
||||
#define DDRSS_CTL_181_DATA 0x16000000
|
||||
#define DDRSS_CTL_182_DATA 0x00841616
|
||||
#define DDRSS_CTL_183_DATA 0x3FF43FF4
|
||||
#define DDRSS_CTL_184_DATA 0x33333300
|
||||
#define DDRSS_CTL_185_DATA 0x00000000
|
||||
#define DDRSS_CTL_186_DATA 0x00565600
|
||||
#define DDRSS_CTL_187_DATA 0x00002727
|
||||
#define DDRSS_CTL_188_DATA 0x00000F0F
|
||||
#define DDRSS_CTL_189_DATA 0x06060000
|
||||
#define DDRSS_CTL_189_DATA 0x16161600
|
||||
#define DDRSS_CTL_190_DATA 0x00000020
|
||||
#define DDRSS_CTL_191_DATA 0x00000000
|
||||
#define DDRSS_CTL_192_DATA 0x00000001
|
||||
|
|
@ -238,17 +239,17 @@
|
|||
#define DDRSS_CTL_226_DATA 0x00000000
|
||||
#define DDRSS_CTL_227_DATA 0x15110000
|
||||
#define DDRSS_CTL_228_DATA 0x00040C18
|
||||
#define DDRSS_CTL_229_DATA 0x00000000
|
||||
#define DDRSS_CTL_230_DATA 0x00000000
|
||||
#define DDRSS_CTL_229_DATA 0xF000C000
|
||||
#define DDRSS_CTL_230_DATA 0x0000F000
|
||||
#define DDRSS_CTL_231_DATA 0x00000000
|
||||
#define DDRSS_CTL_232_DATA 0x00000000
|
||||
#define DDRSS_CTL_233_DATA 0x00000000
|
||||
#define DDRSS_CTL_234_DATA 0x00000000
|
||||
#define DDRSS_CTL_233_DATA 0xC0000000
|
||||
#define DDRSS_CTL_234_DATA 0xF000F000
|
||||
#define DDRSS_CTL_235_DATA 0x00000000
|
||||
#define DDRSS_CTL_236_DATA 0x00000000
|
||||
#define DDRSS_CTL_237_DATA 0x00000000
|
||||
#define DDRSS_CTL_238_DATA 0x00000000
|
||||
#define DDRSS_CTL_239_DATA 0x00000000
|
||||
#define DDRSS_CTL_238_DATA 0xF000C000
|
||||
#define DDRSS_CTL_239_DATA 0x0000F000
|
||||
#define DDRSS_CTL_240_DATA 0x00000000
|
||||
#define DDRSS_CTL_241_DATA 0x00000000
|
||||
#define DDRSS_CTL_242_DATA 0x00030000
|
||||
|
|
@ -267,7 +268,7 @@
|
|||
#define DDRSS_CTL_255_DATA 0x00000000
|
||||
#define DDRSS_CTL_256_DATA 0x00000000
|
||||
#define DDRSS_CTL_257_DATA 0x01000200
|
||||
#define DDRSS_CTL_258_DATA 0x00320040
|
||||
#define DDRSS_CTL_258_DATA 0x00370040
|
||||
#define DDRSS_CTL_259_DATA 0x00020008
|
||||
#define DDRSS_CTL_260_DATA 0x00400100
|
||||
#define DDRSS_CTL_261_DATA 0x00400855
|
||||
|
|
@ -276,7 +277,7 @@
|
|||
#define DDRSS_CTL_264_DATA 0x00000040
|
||||
#define DDRSS_CTL_265_DATA 0x006B0003
|
||||
#define DDRSS_CTL_266_DATA 0x0100006B
|
||||
#define DDRSS_CTL_267_DATA 0x00000000
|
||||
#define DDRSS_CTL_267_DATA 0x03030303
|
||||
#define DDRSS_CTL_268_DATA 0x01010000
|
||||
#define DDRSS_CTL_269_DATA 0x00000202
|
||||
#define DDRSS_CTL_270_DATA 0x00000FFF
|
||||
|
|
@ -398,13 +399,13 @@
|
|||
#define DDRSS_CTL_386_DATA 0x00000000
|
||||
#define DDRSS_CTL_387_DATA 0x3A3A1B00
|
||||
#define DDRSS_CTL_388_DATA 0x000A0000
|
||||
#define DDRSS_CTL_389_DATA 0x00000176
|
||||
#define DDRSS_CTL_389_DATA 0x0000019C
|
||||
#define DDRSS_CTL_390_DATA 0x00000200
|
||||
#define DDRSS_CTL_391_DATA 0x00000200
|
||||
#define DDRSS_CTL_392_DATA 0x00000200
|
||||
#define DDRSS_CTL_393_DATA 0x00000200
|
||||
#define DDRSS_CTL_394_DATA 0x00000462
|
||||
#define DDRSS_CTL_395_DATA 0x00000E9C
|
||||
#define DDRSS_CTL_394_DATA 0x000004D4
|
||||
#define DDRSS_CTL_395_DATA 0x00001018
|
||||
#define DDRSS_CTL_396_DATA 0x00000204
|
||||
#define DDRSS_CTL_397_DATA 0x000040E6
|
||||
#define DDRSS_CTL_398_DATA 0x00000200
|
||||
|
|
@ -431,7 +432,7 @@
|
|||
#define DDRSS_CTL_419_DATA 0x00000000
|
||||
#define DDRSS_CTL_420_DATA 0x00000000
|
||||
#define DDRSS_CTL_421_DATA 0x00030000
|
||||
#define DDRSS_CTL_422_DATA 0x0006001E
|
||||
#define DDRSS_CTL_422_DATA 0x0007001F
|
||||
#define DDRSS_CTL_423_DATA 0x001B0033
|
||||
#define DDRSS_CTL_424_DATA 0x001B0033
|
||||
#define DDRSS_CTL_425_DATA 0x00000000
|
||||
|
|
@ -632,14 +633,14 @@
|
|||
#define DDRSS_PI_160_DATA 0x00000000
|
||||
#define DDRSS_PI_161_DATA 0x00010000
|
||||
#define DDRSS_PI_162_DATA 0x00000000
|
||||
#define DDRSS_PI_163_DATA 0x2B2B0100
|
||||
#define DDRSS_PI_163_DATA 0x2B2B0200
|
||||
#define DDRSS_PI_164_DATA 0x00000034
|
||||
#define DDRSS_PI_165_DATA 0x00000064
|
||||
#define DDRSS_PI_166_DATA 0x00020064
|
||||
#define DDRSS_PI_167_DATA 0x02000200
|
||||
#define DDRSS_PI_168_DATA 0x48120C04
|
||||
#define DDRSS_PI_169_DATA 0x000E4812
|
||||
#define DDRSS_PI_170_DATA 0x000000BB
|
||||
#define DDRSS_PI_169_DATA 0x00104812
|
||||
#define DDRSS_PI_170_DATA 0x000000CE
|
||||
#define DDRSS_PI_171_DATA 0x00000256
|
||||
#define DDRSS_PI_172_DATA 0x00002073
|
||||
#define DDRSS_PI_173_DATA 0x00000256
|
||||
|
|
@ -657,14 +658,14 @@
|
|||
#define DDRSS_PI_185_DATA 0x15040000
|
||||
#define DDRSS_PI_186_DATA 0x0E0E0215
|
||||
#define DDRSS_PI_187_DATA 0x00040402
|
||||
#define DDRSS_PI_188_DATA 0x000C8034
|
||||
#define DDRSS_PI_188_DATA 0x000D0035
|
||||
#define DDRSS_PI_189_DATA 0x00218049
|
||||
#define DDRSS_PI_190_DATA 0x00218049
|
||||
#define DDRSS_PI_191_DATA 0x01010101
|
||||
#define DDRSS_PI_192_DATA 0x0004000D
|
||||
#define DDRSS_PI_192_DATA 0x0004000E
|
||||
#define DDRSS_PI_193_DATA 0x00040216
|
||||
#define DDRSS_PI_194_DATA 0x01000216
|
||||
#define DDRSS_PI_195_DATA 0x000E000E
|
||||
#define DDRSS_PI_195_DATA 0x000F000F
|
||||
#define DDRSS_PI_196_DATA 0x02170100
|
||||
#define DDRSS_PI_197_DATA 0x01000217
|
||||
#define DDRSS_PI_198_DATA 0x02170217
|
||||
|
|
@ -677,7 +678,7 @@
|
|||
#define DDRSS_PI_205_DATA 0x00C01000
|
||||
#define DDRSS_PI_206_DATA 0x00C01000
|
||||
#define DDRSS_PI_207_DATA 0x00021000
|
||||
#define DDRSS_PI_208_DATA 0x0024000D
|
||||
#define DDRSS_PI_208_DATA 0x0024000E
|
||||
#define DDRSS_PI_209_DATA 0x00240216
|
||||
#define DDRSS_PI_210_DATA 0x00110216
|
||||
#define DDRSS_PI_211_DATA 0x32000056
|
||||
|
|
@ -688,7 +689,7 @@
|
|||
#define DDRSS_PI_216_DATA 0x3212005B
|
||||
#define DDRSS_PI_217_DATA 0x09000301
|
||||
#define DDRSS_PI_218_DATA 0x04010504
|
||||
#define DDRSS_PI_219_DATA 0x0400062B
|
||||
#define DDRSS_PI_219_DATA 0x040006C9
|
||||
#define DDRSS_PI_220_DATA 0x0A032001
|
||||
#define DDRSS_PI_221_DATA 0x2C31110A
|
||||
#define DDRSS_PI_222_DATA 0x00002D1C
|
||||
|
|
@ -698,43 +699,43 @@
|
|||
#define DDRSS_PI_226_DATA 0x00002D1C
|
||||
#define DDRSS_PI_227_DATA 0x6001071C
|
||||
#define DDRSS_PI_228_DATA 0x1E202008
|
||||
#define DDRSS_PI_229_DATA 0x00017616
|
||||
#define DDRSS_PI_230_DATA 0x00000E9C
|
||||
#define DDRSS_PI_229_DATA 0x00019C16
|
||||
#define DDRSS_PI_230_DATA 0x00001018
|
||||
#define DDRSS_PI_231_DATA 0x000040E6
|
||||
#define DDRSS_PI_232_DATA 0x000288FC
|
||||
#define DDRSS_PI_233_DATA 0x000040E6
|
||||
#define DDRSS_PI_234_DATA 0x000288FC
|
||||
#define DDRSS_PI_235_DATA 0x0266000F
|
||||
#define DDRSS_PI_235_DATA 0x02660010
|
||||
#define DDRSS_PI_236_DATA 0x03030266
|
||||
#define DDRSS_PI_237_DATA 0x00271003
|
||||
#define DDRSS_PI_238_DATA 0x000186A0
|
||||
#define DDRSS_PI_237_DATA 0x002AF803
|
||||
#define DDRSS_PI_238_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_239_DATA 0x00000005
|
||||
#define DDRSS_PI_240_DATA 0x00000064
|
||||
#define DDRSS_PI_241_DATA 0x0000000F
|
||||
#define DDRSS_PI_240_DATA 0x0000006E
|
||||
#define DDRSS_PI_241_DATA 0x00000010
|
||||
#define DDRSS_PI_242_DATA 0x000681C8
|
||||
#define DDRSS_PI_243_DATA 0x000186A0
|
||||
#define DDRSS_PI_243_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_244_DATA 0x00000005
|
||||
#define DDRSS_PI_245_DATA 0x000010A9
|
||||
#define DDRSS_PI_246_DATA 0x00000266
|
||||
#define DDRSS_PI_247_DATA 0x000681C8
|
||||
#define DDRSS_PI_248_DATA 0x000186A0
|
||||
#define DDRSS_PI_248_DATA 0x0001ADAF
|
||||
#define DDRSS_PI_249_DATA 0x00000005
|
||||
#define DDRSS_PI_250_DATA 0x000010A9
|
||||
#define DDRSS_PI_251_DATA 0x01000266
|
||||
#define DDRSS_PI_252_DATA 0x00320040
|
||||
#define DDRSS_PI_252_DATA 0x00370040
|
||||
#define DDRSS_PI_253_DATA 0x00010008
|
||||
#define DDRSS_PI_254_DATA 0x08550040
|
||||
#define DDRSS_PI_255_DATA 0x00010040
|
||||
#define DDRSS_PI_256_DATA 0x08550040
|
||||
#define DDRSS_PI_257_DATA 0x00000340
|
||||
#define DDRSS_PI_258_DATA 0x006B006B
|
||||
#define DDRSS_PI_259_DATA 0x00040404
|
||||
#define DDRSS_PI_259_DATA 0x08040404
|
||||
#define DDRSS_PI_260_DATA 0x00000055
|
||||
#define DDRSS_PI_261_DATA 0x55003C5A
|
||||
#define DDRSS_PI_261_DATA 0x55083C5A
|
||||
#define DDRSS_PI_262_DATA 0x5A000000
|
||||
#define DDRSS_PI_263_DATA 0x0055003C
|
||||
#define DDRSS_PI_263_DATA 0x0055083C
|
||||
#define DDRSS_PI_264_DATA 0x3C5A0000
|
||||
#define DDRSS_PI_265_DATA 0x00005500
|
||||
#define DDRSS_PI_265_DATA 0x00005508
|
||||
#define DDRSS_PI_266_DATA 0x0C3C5A00
|
||||
#define DDRSS_PI_267_DATA 0x080F0E0D
|
||||
#define DDRSS_PI_268_DATA 0x000B0A09
|
||||
|
|
@ -802,8 +803,8 @@
|
|||
#define DDRSS_PHY_29_DATA 0x00000808
|
||||
#define DDRSS_PHY_30_DATA 0x0F000000
|
||||
#define DDRSS_PHY_31_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_32_DATA 0x10200000
|
||||
#define DDRSS_PHY_33_DATA 0x0C002007
|
||||
#define DDRSS_PHY_32_DATA 0x10400000
|
||||
#define DDRSS_PHY_33_DATA 0x0C002006
|
||||
#define DDRSS_PHY_34_DATA 0x00000000
|
||||
#define DDRSS_PHY_35_DATA 0x00000000
|
||||
#define DDRSS_PHY_36_DATA 0x55555555
|
||||
|
|
@ -878,7 +879,7 @@
|
|||
#define DDRSS_PHY_105_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_106_DATA 0x01000140
|
||||
#define DDRSS_PHY_107_DATA 0x0C000420
|
||||
#define DDRSS_PHY_108_DATA 0x00000322
|
||||
#define DDRSS_PHY_108_DATA 0x00000198
|
||||
#define DDRSS_PHY_109_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_110_DATA 0x00030200
|
||||
#define DDRSS_PHY_111_DATA 0x02800000
|
||||
|
|
@ -1058,8 +1059,8 @@
|
|||
#define DDRSS_PHY_285_DATA 0x00000808
|
||||
#define DDRSS_PHY_286_DATA 0x0F000000
|
||||
#define DDRSS_PHY_287_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_288_DATA 0x10200000
|
||||
#define DDRSS_PHY_289_DATA 0x0C002007
|
||||
#define DDRSS_PHY_288_DATA 0x10400000
|
||||
#define DDRSS_PHY_289_DATA 0x0C002006
|
||||
#define DDRSS_PHY_290_DATA 0x00000000
|
||||
#define DDRSS_PHY_291_DATA 0x00000000
|
||||
#define DDRSS_PHY_292_DATA 0x55555555
|
||||
|
|
@ -1134,7 +1135,7 @@
|
|||
#define DDRSS_PHY_361_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_362_DATA 0x01000140
|
||||
#define DDRSS_PHY_363_DATA 0x0C000420
|
||||
#define DDRSS_PHY_364_DATA 0x00000322
|
||||
#define DDRSS_PHY_364_DATA 0x00000198
|
||||
#define DDRSS_PHY_365_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_366_DATA 0x00030200
|
||||
#define DDRSS_PHY_367_DATA 0x02800000
|
||||
|
|
@ -1314,8 +1315,8 @@
|
|||
#define DDRSS_PHY_541_DATA 0x00000808
|
||||
#define DDRSS_PHY_542_DATA 0x0F000000
|
||||
#define DDRSS_PHY_543_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_544_DATA 0x10200000
|
||||
#define DDRSS_PHY_545_DATA 0x0C002007
|
||||
#define DDRSS_PHY_544_DATA 0x10400000
|
||||
#define DDRSS_PHY_545_DATA 0x0C002006
|
||||
#define DDRSS_PHY_546_DATA 0x00000000
|
||||
#define DDRSS_PHY_547_DATA 0x00000000
|
||||
#define DDRSS_PHY_548_DATA 0x55555555
|
||||
|
|
@ -1390,7 +1391,7 @@
|
|||
#define DDRSS_PHY_617_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_618_DATA 0x01000140
|
||||
#define DDRSS_PHY_619_DATA 0x0C000420
|
||||
#define DDRSS_PHY_620_DATA 0x00000322
|
||||
#define DDRSS_PHY_620_DATA 0x00000198
|
||||
#define DDRSS_PHY_621_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_622_DATA 0x00030200
|
||||
#define DDRSS_PHY_623_DATA 0x02800000
|
||||
|
|
@ -1570,8 +1571,8 @@
|
|||
#define DDRSS_PHY_797_DATA 0x00000808
|
||||
#define DDRSS_PHY_798_DATA 0x0F000000
|
||||
#define DDRSS_PHY_799_DATA 0x00000F0F
|
||||
#define DDRSS_PHY_800_DATA 0x10200000
|
||||
#define DDRSS_PHY_801_DATA 0x0C002007
|
||||
#define DDRSS_PHY_800_DATA 0x10400000
|
||||
#define DDRSS_PHY_801_DATA 0x0C002006
|
||||
#define DDRSS_PHY_802_DATA 0x00000000
|
||||
#define DDRSS_PHY_803_DATA 0x00000000
|
||||
#define DDRSS_PHY_804_DATA 0x55555555
|
||||
|
|
@ -1646,7 +1647,7 @@
|
|||
#define DDRSS_PHY_873_DATA 0x0F0C3701
|
||||
#define DDRSS_PHY_874_DATA 0x01000140
|
||||
#define DDRSS_PHY_875_DATA 0x0C000420
|
||||
#define DDRSS_PHY_876_DATA 0x00000322
|
||||
#define DDRSS_PHY_876_DATA 0x00000198
|
||||
#define DDRSS_PHY_877_DATA 0x0A0000D0
|
||||
#define DDRSS_PHY_878_DATA 0x00030200
|
||||
#define DDRSS_PHY_879_DATA 0x02800000
|
||||
|
|
@ -2080,7 +2081,7 @@
|
|||
#define DDRSS_PHY_1307_DATA 0x01200F02
|
||||
#define DDRSS_PHY_1308_DATA 0x00194280
|
||||
#define DDRSS_PHY_1309_DATA 0x00000004
|
||||
#define DDRSS_PHY_1310_DATA 0x00050000
|
||||
#define DDRSS_PHY_1310_DATA 0x00052000
|
||||
#define DDRSS_PHY_1311_DATA 0x00000000
|
||||
#define DDRSS_PHY_1312_DATA 0x00000000
|
||||
#define DDRSS_PHY_1313_DATA 0x00000000
|
||||
|
|
|
|||
Loading…
Reference in a new issue