mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
arm64: imx: Add support for imx8mp-beacon-kit
Beacon Embedded has an i.MX8M Plus development kit which consists of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC, and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet PHY. The device trees are already queued for inclusion in Linux 6.3. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Adam Ford
Stefano Babic
parent
58ec2711fd
commit
ab53bd43db
18 changed files with 3578 additions and 0 deletions
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@ -995,6 +995,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mn-beacon-kit.dtb \
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imx8mq-mnt-reform2.dtb \
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imx8mq-phanbell.dtb \
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imx8mp-beacon-kit.dtb \
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imx8mp-data-modul-edm-sbc.dtb \
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imx8mp-dhcom-pdk2.dtb \
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imx8mp-dhcom-pdk3.dtb \
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216
arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
Normal file
216
arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
Normal file
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@ -0,0 +1,216 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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bootph-pre-ram;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-pre-ram;
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};
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&crypto {
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bootph-pre-ram;
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};
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&eqos {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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ðphy0 {
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&flexspi {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-pre-ram;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&pca6416 {
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compatible = "ti,tca6416";
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label = "exp4";
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};
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&pca6416_1 {
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compatible = "ti,tca6416";
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label = "exp4";
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};
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&pca6416_3 {
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compatible = "ti,tca6416";
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label = "exp2";
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};
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&pinctrl_i2c1 {
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bootph-pre-ram;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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u-boot,off-on-delay-us = <20000>;
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};
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&sec_jr0 {
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bootph-pre-ram;
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};
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&sec_jr1 {
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bootph-pre-ram;
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};
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&sec_jr2 {
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bootph-pre-ram;
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};
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&tpm {
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compatible = "tcg,tpm_tis-spi";
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};
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&uart2 {
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bootph-pre-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usb3_0 {
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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/delete-property/ power-domains;
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};
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&usb3_1 {
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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/delete-property/ power-domains;
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};
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&usb_dwc3_0 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usb_dwc3_1 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usdhc1 {
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status = "disabled";
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};
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&wdog1 {
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bootph-pre-ram;
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};
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550
arch/arm/dts/imx8mp-beacon-kit.dts
Normal file
550
arch/arm/dts/imx8mp-beacon-kit.dts
Normal file
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@ -0,0 +1,550 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
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*/
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mp.dtsi"
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#include "imx8mp-beacon-som.dtsi"
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/ {
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model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";
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compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
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aliases {
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ethernet0 = &eqos;
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ethernet1 = &fec;
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};
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chosen {
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stdout-path = &uart2;
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};
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hs_ep: endpoint {
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remote-endpoint = <&usb3_hs_ep>;
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};
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};
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port@1 {
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reg = <1>;
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ss_ep: endpoint {
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remote-endpoint = <&hd3ss3220_in_ep>;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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button-0 {
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label = "btn0";
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linux,code = <BTN_0>;
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gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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wakeup-source;
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};
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button-1 {
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label = "btn1";
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linux,code = <BTN_1>;
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gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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wakeup-source;
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};
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button-2 {
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label = "btn2";
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linux,code = <BTN_2>;
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gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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wakeup-source;
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};
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button-3 {
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label = "btn3";
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linux,code = <BTN_3>;
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gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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wakeup-source;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led3>;
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led-0 {
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label = "gen_led0";
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gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-1 {
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label = "gen_led1";
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gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-2 {
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label = "gen_led2";
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gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-3 {
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label = "heartbeat";
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gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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pcie0_refclk: clock-pcie {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <20000>;
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};
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reg_usb1_host_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1_host_vbus";
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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tpm: tpm@0 {
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compatible = "infineon,slb9670";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tpm>;
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reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <18500000>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@3 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <3>;
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reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <150000>;
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interrupt-parent = <&gpio4>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&gpio2 {
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usb-mux-hog {
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gpio-hog;
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gpios = <20 0>;
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output-low;
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line-name = "USB-C Mux En";
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};
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};
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&i2c2 {
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clock-frequency = <384000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pca6416_3: gpio@20 {
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compatible = "nxp,pcal6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&i2c3 {
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/* Connected to USB Hub */
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usb-typec@52 {
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compatible = "nxp,ptn5110";
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reg = <0x52>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec>;
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interrupt-parent = <&gpio4>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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power-role = "source";
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data-role = "host";
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source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
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};
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};
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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clock-frequency = <384000>;
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status = "okay";
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pca6416: gpio@20 {
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compatible = "nxp,pcal6416";
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reg = <0x20>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcal6414>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pca6416_1: gpio@21 {
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compatible = "nxp,pcal6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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usb-hub-hog {
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gpio-hog;
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gpios = <7 0>;
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output-low;
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line-name = "USB Hub Enable";
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};
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};
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usb-typec@47 {
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compatible = "ti,hd3ss3220";
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reg = <0x47>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hd3ss3220>;
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interrupt-parent = <&gpio4>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hd3ss3220_in_ep: endpoint {
|
||||
remote-endpoint = <&ss_ep>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hd3ss3220_out_ep: endpoint {
|
||||
remote-endpoint = <&usb3_role_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
clocks = <&pcie0_refclk>;
|
||||
clock-names = "ref";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_0 {
|
||||
dr_mode = "otg";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb3_hs_ep: endpoint {
|
||||
remote-endpoint = <&hs_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
usb3_role_switch: endpoint {
|
||||
remote-endpoint = <&hd3ss3220_out_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
vbus-supply = <®_usb1_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
|
||||
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
|
||||
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
|
||||
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
|
||||
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140
|
||||
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
||||
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hd3ss3220: hd3ss3220grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led3: led3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcal6414: pcal6414-gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */
|
||||
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tpm: tpmgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
|
||||
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_typec: typec1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
|
||||
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
|
||||
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
|
||||
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
|
||||
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
||||
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
};
|
||||
416
arch/arm/dts/imx8mp-beacon-som.dtsi
Normal file
416
arch/arm/dts/imx8mp-beacon-som.dtsi
Normal file
|
|
@ -0,0 +1,416 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
rtc0 = &rtc;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0xc0000000>,
|
||||
<0x1 0x00000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
reg_wl_bt: regulator-wifi-bt {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_wl_bt>;
|
||||
regulator-name = "wl-bt-pow-dwn";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
startup-delay-us = <70000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&eqos {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eqos>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
snps,force_thresh_dma_mode;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <80000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clock-frequency = <384000>;
|
||||
status = "okay";
|
||||
|
||||
pmic@25 {
|
||||
compatible = "nxp,pca9450c";
|
||||
reg = <0x25>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
buck1: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
|
||||
buck4: BUCK4 {
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5: BUCK5 {
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clock-frequency = <384000>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
read-only; /* Manufacturing EEPROM programmed at factory */
|
||||
};
|
||||
|
||||
rtc: rtc@51 {
|
||||
compatible = "nxp,pcf85263";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_wl_bt>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
mwifiex: wifi@1 {
|
||||
compatible = "marvell,sd8997";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wlan>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
|
||||
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
|
||||
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
|
||||
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
|
||||
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
|
||||
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
|
||||
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
|
||||
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
|
||||
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
|
||||
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
|
||||
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
||||
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
||||
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
||||
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
||||
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
|
||||
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
|
||||
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
|
||||
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
|
||||
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_wl_bt: reg-wl-btgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
||||
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
||||
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
|
||||
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
||||
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan: wlangrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -177,6 +177,16 @@ config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
|
|||
select IMX8M_LPDDR4
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_IMX8MP_BEACON
|
||||
bool "imx8mm Beacon Embedded devkit"
|
||||
select BINMAN
|
||||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
select FSL_CAAM
|
||||
select ARCH_MISC_INIT
|
||||
select SPL_CRYPTO if SPL
|
||||
|
||||
config TARGET_IMX8MP_DH_DHCOM_PDK2
|
||||
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
|
||||
select BINMAN
|
||||
|
|
@ -333,6 +343,7 @@ endchoice
|
|||
source "board/advantech/imx8mp_rsb3720a1/Kconfig"
|
||||
source "board/beacon/imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mn/Kconfig"
|
||||
source "board/beacon/imx8mp/Kconfig"
|
||||
source "board/bsh/imx8mn_smm_s2/Kconfig"
|
||||
source "board/cloos/imx8mm_phg/Kconfig"
|
||||
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
|
||||
|
|
|
|||
16
board/beacon/imx8mp/Kconfig
Normal file
16
board/beacon/imx8mp/Kconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
if TARGET_IMX8MP_BEACON
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8mp"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "beacon"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8mp_beacon"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
|
||||
|
||||
|
||||
endif
|
||||
6
board/beacon/imx8mp/MAINTAINERS
Normal file
6
board/beacon/imx8mp/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
i.MX8MP Beacon EmbeddedWorks Devkit
|
||||
M: Adam Ford <aford173@gmail.com>
|
||||
S: Maintained
|
||||
F: board/beacon/imx8mp/
|
||||
F: include/configs/imx8mp_beacon.h
|
||||
F: configs/imx8mp_beacon_defconfig
|
||||
13
board/beacon/imx8mp/Makefile
Normal file
13
board/beacon/imx8mp/Makefile
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
#
|
||||
|
||||
obj-y += imx8mp_beacon.o
|
||||
obj-y += ../../freescale/common/
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
35
board/beacon/imx8mp/imx8mp_beacon.c
Normal file
35
board/beacon/imx8mp/imx8mp_beacon.c
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks */
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
static void setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Enable RGMII TX clk output */
|
||||
setbits_le32(&gpr->gpr[1], BIT(22));
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_NET)
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (CONFIG_IS_ENABLED(FEC_MXC))
|
||||
setup_fec();
|
||||
|
||||
return ret;
|
||||
}
|
||||
19
board/beacon/imx8mp/imx8mp_beacon.env
Normal file
19
board/beacon/imx8mp/imx8mp_beacon.env
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
boot_fdt=try
|
||||
boot_fit=no
|
||||
console=ttymxc1,115200
|
||||
fdt_addr=0x43000000
|
||||
fdt_addr_r=0x43000000
|
||||
fdt_file=imx8mp-beacon-kit.dtb
|
||||
finduuid=part uuid mmc ${mmcdev}:2 uuid
|
||||
image=Image
|
||||
kernel_addr_r=0x40480000
|
||||
loadfdt=echo ${fdt_file}; fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}
|
||||
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
mmcargs=setenv bootargs console=${console} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
|
||||
mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if run loadfdt; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi;
|
||||
mmcdev=1
|
||||
mmcpart=1
|
||||
netargs=setenv bootargs ${jh_clk} console=${console} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
|
||||
netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi;
|
||||
optargs=audit=0 video=LVDS-1:d video=LVDS-2:d
|
||||
scriptaddr=0x40480000
|
||||
9
board/beacon/imx8mp/imximage-8mp-lpddr4.cfg
Normal file
9
board/beacon/imx8mp/imximage-8mp-lpddr4.cfg
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
|
||||
ROM_VERSION v2
|
||||
BOOT_FROM sd
|
||||
LOADER u-boot-spl-ddr.bin 0x920000
|
||||
1881
board/beacon/imx8mp/lpddr4_timing.c
Normal file
1881
board/beacon/imx8mp/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load diff
132
board/beacon/imx8mp/spl.c
Normal file
132
board/beacon/imx8mp/spl.c
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hang.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <spl.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
return BOOT_DEVICE_BOOTROM;
|
||||
}
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
|
||||
if (ret)
|
||||
printf("Failed to initialize caam_jr: %d\n", ret);
|
||||
}
|
||||
/*
|
||||
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
|
||||
* not allow to change it. Should set the clock after PMIC
|
||||
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
|
||||
* set by ROM for ND VDD_SOC
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
|
||||
clock_enable(CCGR_GIC, 0);
|
||||
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
|
||||
clock_enable(CCGR_GIC, 1);
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = pmic_get("pmic@25", &dev);
|
||||
if (ret == -ENODEV) {
|
||||
puts("No pmic@25\n");
|
||||
return 0;
|
||||
}
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
||||
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/*
|
||||
* increase VDD_SOC to typical value 0.95V before first
|
||||
* DRAM access, set DVS1 to 0.85v for suspend.
|
||||
* Enable DVS control through PMIC_STBY_REQ and
|
||||
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
|
||||
*/
|
||||
if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
|
||||
else
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
|
||||
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
|
||||
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
|
||||
|
||||
/* Kernel uses OD/OD freq for SOC */
|
||||
/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
|
||||
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPL_LOAD_FIT)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(1);
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
182
configs/imx8mp_beacon_defconfig
Normal file
182
configs/imx8mp_beacon_defconfig
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARM_SMCCC=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xFFFFDE00
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit"
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y
|
||||
CONFIG_TARGET_IMX8MP_BEACON=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK=0x960000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
|
||||
CONFIG_ARMV8_MULTIENTRY=y
|
||||
CONFIG_ARMV8_SET_SMPEN=y
|
||||
# CONFIG_PSCI_RESET is not set
|
||||
CONFIG_ARMV8_PSCI=y
|
||||
CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
|
||||
CONFIG_ARMV8_PSCI_RELOCATE=y
|
||||
CONFIG_ARMV8_SECURE_BASE=0x970000
|
||||
CONFIG_ARMV8_EA_EL3_FIRST=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb"
|
||||
# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x98fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_TPM=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_SOURCE_FILE="imx8mp_beacon"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="eth1"
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_UUU_SUPPORT=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
|
||||
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PHY_IMX8MQ_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_PCA9450=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
# CONFIG_DM_RNG is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_NXP_FSPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_TMU=y
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_MX7 is not set
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
|
||||
CONFIG_SDP_LOADADDR=0x0
|
||||
CONFIG_USB_FUNCTION_ACM=y
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
# CONFIG_WATCHDOG_AUTOSTART is not set
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_TPM=y
|
||||
# CONFIG_SPL_SHA512 is not set
|
||||
# CONFIG_SPL_SHA384 is not set
|
||||
52
doc/board/beacon/beacon-imx8mp.rst
Normal file
52
doc/board/beacon/beacon-imx8mp.rst
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
U-Boot for the Beacon EmbeddedWorks i.MX8M Plus Devkit
|
||||
======================================================
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Build the ARM Trusted firmware binary
|
||||
- Get DDR firmware
|
||||
- Build U-Boot
|
||||
- Burn U-Noot to microSD Card
|
||||
- Boot
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
--------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6
|
||||
$ make PLAT=imx8mp bl31 CROSS_COMPILE=aarch64-linux-gnu-
|
||||
$ cp build/imx8mn/release/bl31.bin ../
|
||||
|
||||
Get the DDR firmware
|
||||
--------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin
|
||||
$ chmod +x firmware-imx-8.15.bin
|
||||
$ ./firmware-imx-8.15
|
||||
$ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin .
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ make imx8mp_beacon_defconfig
|
||||
$ make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
Burn U-Boot to microSD Card
|
||||
---------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
|
||||
|
||||
Boot
|
||||
----
|
||||
Set baseboard DIP switch:
|
||||
S17: 1100XXXX
|
||||
9
doc/board/beacon/index.rst
Normal file
9
doc/board/beacon/index.rst
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Beacon
|
||||
======
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
beacon-imx8mp
|
||||
|
|
@ -14,6 +14,7 @@ Board-specific doc
|
|||
apple/index
|
||||
armltd/index
|
||||
atmel/index
|
||||
beacon/index
|
||||
broadcom/index
|
||||
bsh/index
|
||||
cloos/index
|
||||
|
|
|
|||
29
include/configs/imx8mp_beacon.h
Normal file
29
include/configs/imx8mp_beacon.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MP_BEACON_H
|
||||
#define __IMX8MP_BEACON_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
#endif
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
/* Totally 6GB DDR */
|
||||
#define CFG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
|
||||
#define PHYS_SDRAM_2 0x100000000
|
||||
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue