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net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus

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Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2023-03-06 15:53:51 +01:00 committed by Stefano Babic
parent 80a34e4008
commit 4bdc3524d7
3 changed files with 52 additions and 0 deletions
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2
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -89,6 +89,7 @@
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
#define IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN BIT(22)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19)
@ -96,6 +97,7 @@
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL BIT(13)
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_ARMV8_PSCI /* Final jump location */

46
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View file

@ -968,10 +968,56 @@ int set_clk_enet(enum enet_freq type)
return 0;
}
static int imx8mp_fec_interface_init(struct udevice *dev,
phy_interface_t interface_type,
bool mx8mp)
{
/* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */
const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0;
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
clrbits_le32(&gpr->gpr[1],
rgmii_en |
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
switch (interface_type) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_RMII:
setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
setbits_le32(&gpr->gpr[1], rgmii_en);
break;
default:
return -EINVAL;
}
return 0;
}
#endif
int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
{
if (IS_ENABLED(CONFIG_IMX8MM) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx8mm-fec"))
return imx8mp_fec_interface_init(dev, interface_type, false);
if (IS_ENABLED(CONFIG_IMX8MN) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx8mn-fec"))
return imx8mp_fec_interface_init(dev, interface_type, false);
if (IS_ENABLED(CONFIG_IMX8MP) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx8mp-fec"))
return imx8mp_fec_interface_init(dev, interface_type, true);
if (IS_ENABLED(CONFIG_IMX8MP) &&
IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))

4
drivers/net/fec_mxc.c
View file

@ -1232,6 +1232,10 @@ static int fecmxc_probe(struct udevice *dev)
uint32_t start;
int ret;
ret = board_interface_eth_init(dev, pdata->phy_interface);
if (ret)
return ret;
if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
if (enet_fused((ulong)priv->eth)) {
printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);