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net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus
Implement common board_interface_eth_init() and call it from the FEC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Signed-off-by: Marek Vasut <marex@denx.de>
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3 changed files with 52 additions and 0 deletions
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@ -89,6 +89,7 @@
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#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
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#define DDR_CSD1_BASE_ADDR 0x40000000
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#define IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN BIT(22)
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20)
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19)
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@ -96,6 +97,7 @@
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16)
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
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#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL BIT(13)
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#define FEC_QUIRK_ENET_MAC
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#ifdef CONFIG_ARMV8_PSCI /* Final jump location */
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@ -968,10 +968,56 @@ int set_clk_enet(enum enet_freq type)
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return 0;
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}
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static int imx8mp_fec_interface_init(struct udevice *dev,
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phy_interface_t interface_type,
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bool mx8mp)
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{
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/* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */
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const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0;
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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clrbits_le32(&gpr->gpr[1],
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rgmii_en |
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IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
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switch (interface_type) {
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_RMII:
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setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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setbits_le32(&gpr->gpr[1], rgmii_en);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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#endif
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int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
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{
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if (IS_ENABLED(CONFIG_IMX8MM) &&
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IS_ENABLED(CONFIG_FEC_MXC) &&
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device_is_compatible(dev, "fsl,imx8mm-fec"))
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return imx8mp_fec_interface_init(dev, interface_type, false);
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if (IS_ENABLED(CONFIG_IMX8MN) &&
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IS_ENABLED(CONFIG_FEC_MXC) &&
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device_is_compatible(dev, "fsl,imx8mn-fec"))
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return imx8mp_fec_interface_init(dev, interface_type, false);
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if (IS_ENABLED(CONFIG_IMX8MP) &&
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IS_ENABLED(CONFIG_FEC_MXC) &&
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device_is_compatible(dev, "fsl,imx8mp-fec"))
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return imx8mp_fec_interface_init(dev, interface_type, true);
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if (IS_ENABLED(CONFIG_IMX8MP) &&
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IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
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device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
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@ -1232,6 +1232,10 @@ static int fecmxc_probe(struct udevice *dev)
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uint32_t start;
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int ret;
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ret = board_interface_eth_init(dev, pdata->phy_interface);
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if (ret)
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return ret;
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if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
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if (enet_fused((ulong)priv->eth)) {
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printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
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