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https://github.com/AsahiLinux/u-boot
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sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features. There are many mores features that just those that are currently mentioned. Since new will be added later and most are not known, let's reuse value from vendor DRAM driver as-is. This will also help adding support for new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Jernej Skrabec
Andre Przywara
parent
f35ec2105e
commit
f221411caa
5 changed files with 126 additions and 142 deletions
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@ -137,6 +137,14 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
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#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
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#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
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#define TPR10_CA_BIT_DELAY BIT(16)
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#define TPR10_DX_BIT_DELAY0 BIT(17)
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#define TPR10_DX_BIT_DELAY1 BIT(18)
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#define TPR10_WRITE_LEVELING BIT(20)
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#define TPR10_READ_CALIBRATION BIT(21)
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#define TPR10_READ_TRAINING BIT(22)
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#define TPR10_WRITE_TRAINING BIT(23)
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struct dram_para {
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u32 clk;
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enum sunxi_dram_type type;
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@ -147,6 +155,7 @@ struct dram_para {
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u32 dx_odt;
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u32 dx_dri;
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u32 ca_dri;
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u32 tpr10;
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};
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@ -52,38 +52,6 @@ config DRAM_SUN50I_H616
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like H616.
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if DRAM_SUN50I_H616
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config DRAM_SUN50I_H616_WRITE_LEVELING
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bool "H616 DRAM write leveling"
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---help---
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Select this when DRAM on your H616 board needs write leveling.
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config DRAM_SUN50I_H616_READ_CALIBRATION
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bool "H616 DRAM read calibration"
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---help---
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Select this when DRAM on your H616 board needs read calibration.
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config DRAM_SUN50I_H616_READ_TRAINING
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bool "H616 DRAM read training"
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---help---
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Select this when DRAM on your H616 board needs read training.
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config DRAM_SUN50I_H616_WRITE_TRAINING
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bool "H616 DRAM write training"
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---help---
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Select this when DRAM on your H616 board needs write training.
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config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
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bool "H616 DRAM bit delay compensation"
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---help---
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Select this when DRAM on your H616 board needs bit delay
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compensation.
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config DRAM_SUN50I_H616_UNKNOWN_FEATURE
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bool "H616 DRAM unknown feature"
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---help---
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Select this when DRAM on your H616 board needs this unknown
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feature.
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config DRAM_SUN50I_H616_DX_ODT
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hex "H616 DRAM DX ODT parameter"
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help
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@ -98,6 +66,12 @@ config DRAM_SUN50I_H616_CA_DRI
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hex "H616 DRAM CA DRI parameter"
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help
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CA DRI value from vendor DRAM settings.
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config DRAM_SUN50I_H616_TPR10
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hex "H616 DRAM TPR10 parameter"
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help
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TPR10 value from vendor DRAM settings. It tells which features
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should be configured, like write leveling, read calibration, etc.
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endif
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config SUN6I_PRCM
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@ -577,109 +577,112 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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u32 *ptr;
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int i;
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
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if (para->tpr10 & TPR10_DX_BIT_DELAY1) {
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x16, ptr);
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writel_relaxed(0x16, ptr + 0x30);
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ptr += 2;
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x16, ptr);
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writel_relaxed(0x16, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760);
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dmb();
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
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}
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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ptr += 2;
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if (para->tpr10 & TPR10_DX_BIT_DELAY0) {
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x10, ptr);
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writel_relaxed(0x10, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x12, ptr);
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writel_relaxed(0x12, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x12, ptr);
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writel_relaxed(0x12, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x14, ptr);
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writel_relaxed(0x14, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x75c);
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dmb();
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
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}
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760);
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dmb();
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
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/* second part */
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x10, ptr);
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writel_relaxed(0x10, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x12, ptr);
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writel_relaxed(0x12, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x12, ptr);
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writel_relaxed(0x12, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x14, ptr);
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writel_relaxed(0x14, ptr + 0x30);
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ptr += 2;
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}
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x75c);
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dmb();
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
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return true;
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}
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@ -718,7 +721,7 @@ static bool mctl_phy_init(struct dram_para *para)
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for (i = 0; i < ARRAY_SIZE(phy_init); i++)
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writel(phy_init[i], &ptr[i]);
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE)) {
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if (para->tpr10 & TPR10_CA_BIT_DELAY) {
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
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for (i = 0; i < 32; i++)
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writel(0x16, &ptr[i]);
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@ -800,7 +803,7 @@ static bool mctl_phy_init(struct dram_para *para)
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clrbits_le32(&mctl_ctl->rfshctl3, 1);
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writel(1, &mctl_ctl->swctl);
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING)) {
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if (para->tpr10 & TPR10_WRITE_LEVELING) {
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for (i = 0; i < 5; i++)
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if (mctl_phy_write_leveling(para))
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break;
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@ -810,7 +813,7 @@ static bool mctl_phy_init(struct dram_para *para)
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}
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}
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION)) {
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if (para->tpr10 & TPR10_READ_CALIBRATION) {
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for (i = 0; i < 5; i++)
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if (mctl_phy_read_calibration(para))
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break;
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@ -820,7 +823,7 @@ static bool mctl_phy_init(struct dram_para *para)
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}
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}
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_TRAINING)) {
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if (para->tpr10 & TPR10_READ_TRAINING) {
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for (i = 0; i < 5; i++)
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if (mctl_phy_read_training(para))
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break;
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@ -830,7 +833,7 @@ static bool mctl_phy_init(struct dram_para *para)
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}
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}
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING)) {
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if (para->tpr10 & TPR10_WRITE_TRAINING) {
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for (i = 0; i < 5; i++)
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if (mctl_phy_write_training(para))
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break;
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@ -840,8 +843,7 @@ static bool mctl_phy_init(struct dram_para *para)
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}
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}
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION))
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mctl_phy_bit_delay_compensation(para);
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mctl_phy_bit_delay_compensation(para);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 4);
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@ -1022,6 +1024,7 @@ unsigned long sunxi_dram_init(void)
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.dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT,
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.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
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.ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
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.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
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};
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unsigned long size;
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|
|
|
|||
|
|
@ -2,13 +2,10 @@ CONFIG_ARM=y
|
|||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2"
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING=y
|
||||
CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y
|
||||
CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y
|
||||
CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y
|
||||
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808
|
||||
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
|
||||
CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
|
||||
CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
|
||||
CONFIG_MACH_SUN50I_H616=y
|
||||
CONFIG_R_I2C_ENABLE=y
|
||||
CONFIG_SPL_SPI_SUNXI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y
|
|||
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
|
||||
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
|
||||
CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1c12
|
||||
CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007
|
||||
CONFIG_MACH_SUN50I_H616=y
|
||||
CONFIG_R_I2C_ENABLE=y
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
|||
Loading…
Reference in a new issue