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https://github.com/AsahiLinux/u-boot
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board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for rockchip and also a reference board for board vendors. Hardware: SoC: RK3588 DRAM: LPDDR4X 8GB Debug: UART2 via USB PCIe: 3x4 *1 SATA *2 HDMI out *2 HDMI IN *1 USB2.0 Host *2 USB3.0 Host *1 Type C *1 MIPI DSI panel dts Sync from Linux v6.2. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@edgeble.ai>
This commit is contained in:
Kever Yang
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11 changed files with 319 additions and 0 deletions
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@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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dtb-$(CONFIG_ROCKCHIP_RK3588) += \
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rk3588-edgeble-neu6a-io.dtb \
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rk3588-evb1-v10.dtb \
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rk3588-rock-5b.dtb
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dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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21
arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
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21
arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
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@ -0,0 +1,21 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3588-u-boot.dtsi"
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/ {
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aliases {
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mmc0 = &sdmmc;
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mmc1 = &sdhci;
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};
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chosen {
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u-boot,spl-boot-order = &sdhci;
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};
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};
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&sdhci {
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bootph-all;
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};
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129
arch/arm/dts/rk3588-evb1-v10.dts
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129
arch/arm/dts/rk3588-evb1-v10.dts
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@ -0,0 +1,129 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3588.dtsi"
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/ {
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model = "Rockchip RK3588 EVB1 V10 Board";
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compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
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aliases {
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mmc0 = &sdhci;
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serial2 = &uart2;
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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power-supply = <&vcc12v_dcin>;
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pwms = <&pwm2 0 25000 0>;
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};
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vcc12v_dcin: vcc12v-dcin-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc12v_dcin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc5v0_sys: vcc5v0-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc12v_dcin>;
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};
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};
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&gmac0 {
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clock_in_out = "output";
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phy-handle = <&rgmii_phy>;
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phy-mode = "rgmii-rxid";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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pinctrl-names = "default";
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rx_delay = <0x00>;
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tx_delay = <0x43>;
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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hym8563: rtc@51 {
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compatible = "haoyu,hym8563";
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reg = <0x51>;
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#clock-cells = <0>;
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clock-output-names = "hym8563";
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pinctrl-names = "default";
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pinctrl-0 = <&hym8563_int>;
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
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wakeup-source;
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};
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};
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&mdio0 {
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rgmii_phy: ethernet-phy@1 {
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/* RTL8211F */
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compatible = "ethernet-phy-id001c.c916";
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reg = <0x1>;
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pinctrl-names = "default";
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pinctrl-0 = <&rtl8211f_rst>;
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reset-assert-us = <20000>;
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reset-deassert-us = <100000>;
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reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
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};
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};
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&pinctrl {
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rtl8211f {
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rtl8211f_rst: rtl8211f-rst {
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rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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hym8563 {
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hym8563_int: hym8563-int {
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rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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&pwm2 {
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status = "okay";
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};
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&sdhci {
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bus-width = <8>;
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no-sdio;
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no-sd;
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non-removable;
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max-frequency = <200000000>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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status = "okay";
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};
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&uart2 {
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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@ -1,5 +1,11 @@
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if ROCKCHIP_RK3588
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config TARGET_EVB_RK3588
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bool "Rockchip EVB1 v10"
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select BOARD_LATE_INIT
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help
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RK3588 EVB is a evaluation board for Rockchp RK3588.
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config TARGET_RK3588_NEU6
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bool "Edgeble Neural Compute Module 6(Neu6) SoM"
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select BOARD_LATE_INIT
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@ -51,6 +57,7 @@ config SYS_MALLOC_F_LEN
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default 0x80000
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source board/edgeble/neural-compute-module-6/Kconfig
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source board/rockchip/evb_rk3588/Kconfig
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source board/radxa/rock5b-rk3588/Kconfig
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endif
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15
board/rockchip/evb_rk3588/Kconfig
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15
board/rockchip/evb_rk3588/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_EVB_RK3588
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config SYS_BOARD
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default "evb_rk3588"
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config SYS_VENDOR
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default "rockchip"
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config SYS_CONFIG_NAME
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default "evb_rk3588"
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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endif
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7
board/rockchip/evb_rk3588/MAINTAINERS
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7
board/rockchip/evb_rk3588/MAINTAINERS
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@ -0,0 +1,7 @@
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EVB-RK3588
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M: Kever Yang <kever.yang@rock-chips.com>
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S: Maintained
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F: board/rockchip/evb_rk3588
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F: include/configs/evb_rk3588.h
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F: configs/evb-rk3588_defconfig
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F: arch/arm/dts/rk3588-evb-u-boot.dtsi
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6
board/rockchip/evb_rk3588/Makefile
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6
board/rockchip/evb_rk3588/Makefile
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
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#
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obj-y += evb-rk3588.o
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39
board/rockchip/evb_rk3588/evb-rk3588.c
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39
board/rockchip/evb_rk3588/evb-rk3588.c
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@ -0,0 +1,39 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
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*/
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#include <fdtdec.h>
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#include <fdt_support.h>
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#ifdef CONFIG_OF_BOARD_SETUP
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static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
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{
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struct fdt_memory gap1 = {
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.start = 0x3fc000000,
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.end = 0x3fc4fffff,
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};
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struct fdt_memory gap2 = {
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.start = 0x3fff00000,
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.end = 0x3ffffffff,
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};
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unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
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unsigned int ret;
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/*
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* Inject the reserved-memory nodes into the DTS
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*/
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ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
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NULL, flags);
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if (ret)
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return ret;
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return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
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NULL, flags);
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return rk3588_add_reserved_memory_fdt_nodes(blob);
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}
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#endif
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69
configs/evb-rk3588_defconfig
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69
configs/evb-rk3588_defconfig
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@ -0,0 +1,69 @@
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00a00000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3588=y
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CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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CONFIG_SPL_MMC=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK_R_ADDR=0x600000
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CONFIG_TARGET_EVB_RK3588=y
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CONFIG_SPL_STACK=0x400000
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CONFIG_DEBUG_UART_BASE=0xFEB50000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0xc00800
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x20000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x4000000
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CONFIG_SPL_BSS_MAX_SIZE=0x4000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_ATF=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_SPL_DOS_PARTITION is not set
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_SUPPORT_EMMC_RPMB=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_SPL_RAM=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_SYSRESET=y
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CONFIG_ERRNO_STR=y
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@ -91,6 +91,7 @@ List of mainline supported Rockchip boards:
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- Rockchip Evb-RK3568 (evb-rk3568)
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* rk3588
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- Rockchip EVB (evb-rk3588)
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- Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588)
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- Radxa ROCK 5B (rock5b-rk3588)
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@ -185,6 +186,15 @@ To build rk3568 boards:
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make evb-rk3568_defconfig
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make CROSS_COMPILE=aarch64-linux-gnu-
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To build rk3588 boards:
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.. code-block:: bash
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export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.33.elf
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export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.bin
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make evb-rk3588_defconfig
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make CROSS_COMPILE=aarch64-linux-gnu-
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Flashing
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--------
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15
include/configs/evb_rk3588.h
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15
include/configs/evb_rk3588.h
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __EVB_RK3588_H
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#define __EVB_RK3588_H
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#include <configs/rk3588_common.h>
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#define ROCKCHIP_DEVICE_SETTINGS \
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"stdout=serial,vidconsole\0" \
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"stderr=serial,vidconsole\0"
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#endif
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