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imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
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@ -276,6 +276,16 @@ void xrdc_init_mda(void)
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void xrdc_init_mrc(void)
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{
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/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
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xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
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xrdc_config_mrc_dx_perm(4, 0, 1, 1);
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xrdc_config_mrc_dx_perm(4, 0, 7, 1);
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xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
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xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
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xrdc_config_mrc_dx_perm(5, 0, 1, 1);
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xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
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/* The MRC8 is for SRAM1 */
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xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
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/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
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