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Prepare v2023.04-rc4

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Merge tag 'v2023.04-rc4' into next

Prepare v2023.04-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2023-03-14 10:58:41 -04:00
commit a5faa4a9eb
134 changed files with 15938 additions and 227 deletions
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1
MAINTAINERS
View file

@ -1336,6 +1336,7 @@ M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/sandbox/
F: doc/arch/sandbox.rst
F: drivers/*/*sandbox*.c
F: include/dt-bindings/*/sandbox*.h
SEAMA

3
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2023
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@ -1335,6 +1335,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
-a rockchip-tpl-path=$(ROCKCHIP_TPL) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
-a spl-dtb=$(CONFIG_SPL_OF_REAL) \

8
arch/arm/dts/Makefile
View file

@ -165,7 +165,13 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-evb.dtb
rk3568-evb.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-rock-5b.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \

4
arch/arm/dts/px30.dtsi
View file

@ -1366,6 +1366,7 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
@ -1378,6 +1379,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
@ -1390,6 +1392,7 @@
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
@ -1402,6 +1405,7 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;

17
arch/arm/dts/r8a77980-condor-u-boot.dts
View file

@ -12,6 +12,23 @@
aliases {
spi0 = &rpc;
};
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
bootph-all;
};
};
&i2c0 {
bootph-all;
sysinfo_eeprom: eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
bootph-all;
};
};
&rpc {

19
arch/arm/dts/r8a77995-draak-u-boot.dts
View file

@ -8,6 +8,25 @@
#include "r8a77995-draak.dts"
#include "r8a77995-u-boot.dtsi"
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
bootph-all;
};
};
&i2c0 {
bootph-all;
sysinfo_eeprom: eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
bootph-all;
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";

17
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*/
#include "rk3308-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &emmc;
};
};
&uart0 {
bootph-all;
clock-frequency = <24000000>;
status = "okay";
};

228
arch/arm/dts/rk3308-rock-pi-s.dts Normal file
View file

@ -0,0 +1,228 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (C) 2023 Akash Gajjar <gajjar04akash@gmail.com>
* Copyright (c) 2023 Jagan Teki <jagan@openedev.com>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3308.dtsi"
/ {
model = "Radxa ROCK Pi S";
compatible = "radxa,rockpis", "rockchip,rk3308";
aliases {
ethernet0 = &mac;
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial0:1500000n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
green-led {
default-state = "on";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
label = "rockpis:green:power";
linux,default-trigger = "default-on";
};
blue-led {
default-state = "on";
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
label = "rockpis:blue:user";
linux,default-trigger = "heartbeat";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-0 = <&wifi_enable_h>;
pinctrl-names = "default";
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_io>;
};
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_ddr: vcc-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_otg: vcc5v0-otg {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_core: vdd-core {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-log {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu0 {
cpu-supply = <&vdd_core>;
};
&emmc {
bus-width = <4>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_io>;
status = "okay";
};
&mac {
clock_in_out = "output";
phy-supply = <&vcc_io>;
snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
};
&i2c1 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
leds {
green_led_gio: green-led-gpio {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
heartbeat_led_gpio: heartbeat-led-gpio {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake: wifi-host-wake {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_pin_pull_down>;
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdio {
#address-cells = <1>;
#size-cells = <0>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <1000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
cap-sd-highspeed;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart4 {
status = "okay";
bluetooth {
compatible = "realtek,rtl8723bs-bt";
device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
};
};
&wdt {
status = "okay";
};

10
arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
View file

@ -92,6 +92,16 @@
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000a

10
arch/arm/dts/rk3328-sdram-ddr4-666.dtsi
View file

@ -89,6 +89,16 @@
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000c

10
arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
View file

@ -92,6 +92,16 @@
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000b

10
arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
View file

@ -92,6 +92,16 @@
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000b

22
arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
View file

@ -14,3 +14,25 @@
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
smbios {
compatible = "u-boot,sysinfo-smbios";
smbios {
system {
manufacturer = "FriendlyELEC";
product = "NanoPi R4S";
};
baseboard {
manufacturer = "FriendlyELEC";
product = "NanoPi R4S";
};
chassis {
manufacturer = "FriendlyELEC";
};
};
};
};

18
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
status = "okay";
};

272
arch/arm/dts/rk3566-radxa-cm3-io.dts Normal file
View file

@ -0,0 +1,272 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Radxa Limited
* Copyright (c) 2022 Amarula Solutions(India)
*/
/dts-v1/;
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
#include "rk3566-radxa-cm3.dtsi"
/ {
model = "Radxa Compute Module 3(CM3) IO Board";
compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
aliases {
mmc1 = &sdmmc0;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_ACTIVITY;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&pi_nled_activity>;
};
};
vcc5v0_usb30: vcc5v0-usb30-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb30";
enable-active-high;
gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb30_en_h>;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_sys>;
};
vcca1v8_image: vcca1v8-image-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca1v8_image";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
vdda0v9_image: vdda0v9-image-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca0v9_image";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vdda_0v9>;
};
};
&combphy1 {
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_rgmii_bus
&gmac1m0_clkinout>;
snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x46>;
rx_delay = <0x2e>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible="ethernet-phy-ieee802.3-c22";
reg= <0x0>;
};
};
&pinctrl {
gmac1 {
gmac1m0_miim: gmac1m0-miim {
rockchip,pins =
/* gmac1_mdcm0 */
<3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_mdiom0 */
<3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
};
gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
rockchip,pins =
/* gmac1_rxd0m0 */
<3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_rxd1m0 */
<3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_rxdvcrsm0 */
<3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
};
gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
rockchip,pins =
/* gmac1_txd0m0 */
<3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_txd1m0 */
<3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_txenm0 */
<3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
};
gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
rockchip,pins =
/* gmac1_rxclkm0 */
<3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_txclkm0 */
<3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
};
gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
rockchip,pins =
/* gmac1_rxd2m0 */
<3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_rxd3m0 */
<3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_txd2m0 */
<3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
/* gmac1_txd3m0 */
<3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
};
gmac1m0_clkinout: gmac1m0-clkinout {
rockchip,pins =
/* gmac1_mclkinoutm0 */
<3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
};
};
leds {
pi_nled_activity: pi-nled-activity {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdcard {
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_usb30_en_h: vcc5v0-host-en-h {
rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc0 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb30>;
status = "okay";
};
&usb2phy1_host {
status = "okay";
};
&usb2phy1_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

425
arch/arm/dts/rk3566-radxa-cm3.dtsi Normal file
View file

@ -0,0 +1,425 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Radxa Limited
* Copyright (c) 2022 Amarula Solutions(India)
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "radxa,cm3", "rockchip,rk3566";
aliases {
mmc0 = &sdhci;
};
leds {
compatible = "gpio-leds";
led-0 {
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
linux,default-trigger = "timer";
default-state = "on";
pinctrl-names = "default";
pinctrl-0 = <&user_led2>;
};
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_1v8: vcc-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
vcc_3v3: vcc-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcca_1v8: vcca-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
sdio_pwrseq: pwrseq-sdio {
compatible = "mmc-pwrseq-simple";
clocks = <&rk817 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on_h>;
reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu_npu>;
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
#clock-cells = <1>;
clock-output-names = "rk817-clkout1", "rk817-clkout2";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_gpu_npu: DCDC_REG2 {
regulator-name = "vdd_gpu_npu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca1v8_pmu: LDO_REG1 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8_p: LDO_REG7 {
regulator-name = "vcc_1v8_p";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc2v8_dvp: LDO_REG9 {
regulator-name = "vcc2v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&pinctrl {
bluetooth {
bt_host_wake_h: bt-host-wake-h {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_reg_on_h: bt-reg-on-h {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host_h: bt-wake-host-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
user_led2: user-led2 {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_reg_on_h: wifi-reg-on-h {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake_h: wifi-host-wake-h {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdmmc1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm43455-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_h>;
};
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rk817 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
vbat-supply = <&vcc_3v3>;
vddio-supply = <&vcc_1v8>;
};
};
&usb2phy0 {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};

617
arch/arm/dts/rk3568-evb.dts
View file

@ -6,13 +6,22 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
@ -26,6 +35,44 @@
regulator-max-microvolt = <12000000>;
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
led_work: led-0 {
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_work_en>;
};
};
rk809-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK809";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
@ -46,10 +93,50 @@
vin-supply = <&dc_12v>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
regulator-name = "vcc5v0_usb_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-name = "vcc5v0_usb_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc3v3_lcd0_n: vcc3v3-lcd0-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd0_n";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_lcd0_n_en>;
regulator-state-mem {
regulator-off-in-suspend;
@ -59,7 +146,13 @@
vcc3v3_lcd1_n: vcc3v3-lcd1-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd1_n";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_lcd1_n_en>;
regulator-state-mem {
regulator-off-in-suspend;
@ -67,13 +160,533 @@
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
codec {
mic-in-differential;
};
};
};
&i2c1 {
status = "okay";
touchscreen0: goodix@14 {
compatible = "goodix,gt1151";
reg = <0x14>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
AVDD28-supply = <&vcc3v3_lcd0_n>;
irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int &touch_rst>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
VDDIO-supply = <&vcc3v3_lcd0_n>;
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
display {
vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
};
vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
};
};
leds {
led_work_en: led_work_en {
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
touchscreen {
touch_int: touch_int {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
touch_rst: touch_rst {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

24
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
* (C) Copyright 2023 Akash Gajjar <gajjar04akash@gmail.com>
*/
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc0;
};
};
&sdmmc0 {
status = "okay";
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
status = "okay";
};

609
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Akash Gajjar <gajjar04akash@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568.dtsi"
/ {
model = "Radxa ROCK3 Model A";
compatible = "radxa,rock3a", "rockchip,rk3568";
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
regulator-name = "vcc5v0_usb_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_hub_en>;
regulator-name = "vcc5v0_usb_hub";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
regulator-name = "vcc5v0_usb_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc_cam: vcc-cam-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_cam_en>;
regulator-name = "vcc_cam";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_mipi: vcc-mipi-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_mipi_en>;
regulator-name = "vcc_mipi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
codec {
mic-in-differential;
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3m1_xfer>;
status = "disabled";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4m1_xfer>;
status = "disabled";
};
&i2c5 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-output-names = "rtcic_32kout";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&eth_phy_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
cam {
vcc_cam_en: vcc_cam_en {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
display {
vcc_mipi_en: vcc_mipi_en {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ethernet {
eth_phy_rst: eth_phy_rst {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
led_user_en: led_user_en {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_enable_h: pcie-enable-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_reset_h: pcie-reset-h {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
bt {
bt_enable: bt-enable {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake: bt-host-wake {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_wake: bt-wake {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable: wifi-enable {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};

122
arch/arm/dts/rk3568.dtsi
View file

@ -42,6 +42,128 @@
reg = <0x0 0xfe190200 0x0 0x20>;
};
pcie30_phy_grf: syscon@fdcb8000 {
compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
reg = <0x0 0xfdcb8000 0x0 0x10000>;
};
pcie30phy: phy@fe8c0000 {
compatible = "rockchip,rk3568-pcie3-phy";
reg = <0x0 0xfe8c0000 0x0 0x20000>;
#phy-cells = <0>;
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
<&cru PCLK_PCIE30PHY>;
clock-names = "refclk_m", "refclk_n", "pclk";
resets = <&cru SRST_PCIE30PHY>;
reset-names = "phy";
rockchip,phy-grf = <&pcie30_phy_grf>;
status = "disabled";
};
pcie3x1: pcie@fe270000 {
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
<0 0 0 2 &pcie3x1_intc 1>,
<0 0 0 3 &pcie3x1_intc 2>,
<0 0 0 4 &pcie3x1_intc 3>;
linux,pci-domain = <1>;
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x0 &gic 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0400000 0x0 0x00400000>,
<0x0 0xfe270000 0x0 0x00010000>,
<0x3 0x7f000000 0x0 0x01000000>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
/* bifurcation; lane1 when using 1+1 */
status = "disabled";
pcie3x1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
};
};
pcie3x2: pcie@fe280000 {
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
<0 0 0 2 &pcie3x2_intc 1>,
<0 0 0 3 &pcie3x2_intc 2>,
<0 0 0 4 &pcie3x2_intc 3>;
linux,pci-domain = <2>;
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x0 &gic 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0800000 0x0 0x00400000>,
<0x0 0xfe280000 0x0 0x00010000>,
<0x3 0xbf000000 0x0 0x01000000>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
/* bifurcation; lane0 when using 1+1 */
status = "disabled";
pcie3x2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
};
};
gmac0: ethernet@fe2a0000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe2a0000 0x0 0x10000>;

17
arch/arm/dts/rk356x-u-boot.dtsi
View file

@ -20,6 +20,23 @@
bootph-all;
status = "okay";
};
otp: nvmem@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
cpu_id: id@a {
reg = <0x0a 0x10>;
};
};
};
&combphy1 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&cru {

187
arch/arm/dts/rk356x.dtsi
View file

@ -592,6 +592,46 @@
status = "disabled";
};
vpu: video-codec@fdea0400 {
compatible = "rockchip,rk3568-vpu";
reg = <0x0 0xfdea0000 0x0 0x800>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
iommus = <&vdpu_mmu>;
power-domains = <&power RK3568_PD_VPU>;
};
vdpu_mmu: iommu@fdea0800 {
compatible = "rockchip,rk3568-iommu";
reg = <0x0 0xfdea0800 0x0 0x40>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3568_PD_VPU>;
#iommu-cells = <0>;
};
vepu: video-codec@fdee0000 {
compatible = "rockchip,rk3568-vepu";
reg = <0x0 0xfdee0000 0x0 0x800>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk", "hclk";
iommus = <&vepu_mmu>;
power-domains = <&power RK3568_PD_RGA>;
};
vepu_mmu: iommu@fdee0800 {
compatible = "rockchip,rk3568-iommu";
reg = <0x0 0xfdee0800 0x0 0x40>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_RGA>;
#iommu-cells = <0>;
};
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
@ -699,6 +739,62 @@
status = "disabled";
};
dsi0: dsi@fe060000 {
compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x00 0xfe060000 0x00 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "hclk";
clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
phy-names = "dphy";
phys = <&dsi_dphy0>;
power-domains = <&power RK3568_PD_VO>;
reset-names = "apb";
resets = <&cru SRST_P_DSITX_0>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi0_in: port@0 {
reg = <0>;
};
dsi0_out: port@1 {
reg = <1>;
};
};
};
dsi1: dsi@fe070000 {
compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xfe070000 0x0 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "hclk";
clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
phy-names = "dphy";
phys = <&dsi_dphy1>;
power-domains = <&power RK3568_PD_VO>;
reset-names = "apb";
resets = <&cru SRST_P_DSITX_1>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in: port@0 {
reg = <0>;
};
dsi1_out: port@1 {
reg = <1>;
};
};
};
hdmi: hdmi@fe0a0000 {
compatible = "rockchip,rk3568-dw-hdmi";
reg = <0x0 0xfe0a0000 0x0 0x20000>;
@ -953,20 +1049,6 @@
status = "disabled";
};
spdif: spdif@fe460000 {
compatible = "rockchip,rk3568-spdif";
reg = <0x0 0xfe460000 0x0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
dmas = <&dmac1 1>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdifm0_tx>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s0_8ch: i2s@fe400000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;
@ -1009,6 +1091,28 @@
status = "disabled";
};
i2s2_2ch: i2s@fe420000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe420000 0x0 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
assigned-clock-rates = <1188000000>;
clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac1 4>, <&dmac1 5>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_I2S2_2CH>;
reset-names = "m";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2m0_sclktx
&i2s2m0_lrcktx
&i2s2m0_sdi
&i2s2m0_sdo>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s3_2ch: i2s@fe430000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe430000 0x0 0x1000>;
@ -1046,6 +1150,20 @@
status = "disabled";
};
spdif: spdif@fe460000 {
compatible = "rockchip,rk3568-spdif";
reg = <0x0 0xfe460000 0x0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
dmas = <&dmac1 1>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdifm0_tx>;
#sound-dai-cells = <0>;
status = "disabled";
};
dmac0: dma-controller@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
@ -1594,6 +1712,42 @@
status = "disabled";
};
csi_dphy: phy@fe870000 {
compatible = "rockchip,rk3568-csi-dphy";
reg = <0x0 0xfe870000 0x0 0x10000>;
clocks = <&cru PCLK_MIPICSIPHY>;
clock-names = "pclk";
#phy-cells = <0>;
resets = <&cru SRST_P_MIPICSIPHY>;
reset-names = "apb";
rockchip,grf = <&grf>;
status = "disabled";
};
dsi_dphy0: mipi-dphy@fe850000 {
compatible = "rockchip,rk3568-dsi-dphy";
reg = <0x0 0xfe850000 0x0 0x10000>;
clock-names = "ref", "pclk";
clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
#phy-cells = <0>;
power-domains = <&power RK3568_PD_VO>;
reset-names = "apb";
resets = <&cru SRST_P_MIPIDSIPHY0>;
status = "disabled";
};
dsi_dphy1: mipi-dphy@fe860000 {
compatible = "rockchip,rk3568-dsi-dphy";
reg = <0x0 0xfe860000 0x0 0x10000>;
clock-names = "ref", "pclk";
clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
#phy-cells = <0>;
power-domains = <&power RK3568_PD_VO>;
reset-names = "apb";
resets = <&cru SRST_P_MIPIDSIPHY1>;
status = "disabled";
};
usb2phy0: usb2phy@fe8a0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a0000 0x0 0x10000>;
@ -1652,6 +1806,7 @@
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@ -1663,6 +1818,7 @@
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@ -1674,6 +1830,7 @@
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@ -1685,6 +1842,7 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@ -1696,6 +1854,7 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;

24
arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include "rk3588-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc;
};
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc;
};
};
&sdmmc {
bus-width = <4>;
bootph-all;
u-boot,spl-fifo-mode;
status = "okay";
};

27
arch/arm/dts/rk3588-edgeble-neu6a-io.dts Normal file
View file

@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/dts-v1/;
#include "rk3588.dtsi"
#include "rk3588-edgeble-neu6a.dtsi"
/ {
model = "Edgeble Neu6A IO Board";
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6a", "rockchip,rk3588";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

32
arch/arm/dts/rk3588-edgeble-neu6a.dtsi Normal file
View file

@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/ {
compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};

516
arch/arm/dts/rk3588-pinctrl.dtsi Normal file
View file

@ -0,0 +1,516 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/pinctrl/rockchip.h>
#include "rockchip-pinconf.dtsi"
/*
* This file is auto generated by pin2dts tool, please keep these code
* by adding changes at end of this file.
*/
&pinctrl {
clk32k {
/omit-if-no-ref/
clk32k_out1: clk32k-out1 {
rockchip,pins =
/* clk32k_out1 */
<2 RK_PC5 1 &pcfg_pull_none>;
};
};
eth0 {
/omit-if-no-ref/
eth0_pins: eth0-pins {
rockchip,pins =
/* eth0_refclko_25m */
<2 RK_PC3 1 &pcfg_pull_none>;
};
};
fspi {
/omit-if-no-ref/
fspim1_pins: fspim1-pins {
rockchip,pins =
/* fspi_clk_m1 */
<2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
/* fspi_cs0n_m1 */
<2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
/* fspi_d0_m1 */
<2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
/* fspi_d1_m1 */
<2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
/* fspi_d2_m1 */
<2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
/* fspi_d3_m1 */
<2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
fspim1_cs1: fspim1-cs1 {
rockchip,pins =
/* fspi_cs1n_m1 */
<2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
};
};
gmac0 {
/omit-if-no-ref/
gmac0_miim: gmac0-miim {
rockchip,pins =
/* gmac0_mdc */
<4 RK_PC4 1 &pcfg_pull_none>,
/* gmac0_mdio */
<4 RK_PC5 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_clkinout: gmac0-clkinout {
rockchip,pins =
/* gmac0_mclkinout */
<4 RK_PC3 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_rx_bus2: gmac0-rx-bus2 {
rockchip,pins =
/* gmac0_rxd0 */
<2 RK_PC1 1 &pcfg_pull_none>,
/* gmac0_rxd1 */
<2 RK_PC2 1 &pcfg_pull_none>,
/* gmac0_rxdv_crs */
<4 RK_PC2 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_tx_bus2: gmac0-tx-bus2 {
rockchip,pins =
/* gmac0_txd0 */
<2 RK_PB6 1 &pcfg_pull_none>,
/* gmac0_txd1 */
<2 RK_PB7 1 &pcfg_pull_none>,
/* gmac0_txen */
<2 RK_PC0 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_rgmii_clk: gmac0-rgmii-clk {
rockchip,pins =
/* gmac0_rxclk */
<2 RK_PB0 1 &pcfg_pull_none>,
/* gmac0_txclk */
<2 RK_PB3 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_rgmii_bus: gmac0-rgmii-bus {
rockchip,pins =
/* gmac0_rxd2 */
<2 RK_PA6 1 &pcfg_pull_none>,
/* gmac0_rxd3 */
<2 RK_PA7 1 &pcfg_pull_none>,
/* gmac0_txd2 */
<2 RK_PB1 1 &pcfg_pull_none>,
/* gmac0_txd3 */
<2 RK_PB2 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_ppsclk: gmac0-ppsclk {
rockchip,pins =
/* gmac0_ppsclk */
<2 RK_PC4 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_ppstring: gmac0-ppstring {
rockchip,pins =
/* gmac0_ppstring */
<2 RK_PB5 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_ptp_refclk: gmac0-ptp-refclk {
rockchip,pins =
/* gmac0_ptp_refclk */
<2 RK_PB4 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
gmac0_txer: gmac0-txer {
rockchip,pins =
/* gmac0_txer */
<4 RK_PC6 1 &pcfg_pull_none>;
};
};
hdmi {
/omit-if-no-ref/
hdmim0_tx1_cec: hdmim0-tx1-cec {
rockchip,pins =
/* hdmim0_tx1_cec */
<2 RK_PC4 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
hdmim0_tx1_scl: hdmim0-tx1-scl {
rockchip,pins =
/* hdmim0_tx1_scl */
<2 RK_PB5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
hdmim0_tx1_sda: hdmim0-tx1-sda {
rockchip,pins =
/* hdmim0_tx1_sda */
<2 RK_PB4 4 &pcfg_pull_none>;
};
};
i2c0 {
/omit-if-no-ref/
i2c0m1_xfer: i2c0m1-xfer {
rockchip,pins =
/* i2c0_scl_m1 */
<4 RK_PC5 9 &pcfg_pull_none_smt>,
/* i2c0_sda_m1 */
<4 RK_PC6 9 &pcfg_pull_none_smt>;
};
};
i2c2 {
/omit-if-no-ref/
i2c2m1_xfer: i2c2m1-xfer {
rockchip,pins =
/* i2c2_scl_m1 */
<2 RK_PC1 9 &pcfg_pull_none_smt>,
/* i2c2_sda_m1 */
<2 RK_PC0 9 &pcfg_pull_none_smt>;
};
};
i2c3 {
/omit-if-no-ref/
i2c3m3_xfer: i2c3m3-xfer {
rockchip,pins =
/* i2c3_scl_m3 */
<2 RK_PB2 9 &pcfg_pull_none_smt>,
/* i2c3_sda_m3 */
<2 RK_PB3 9 &pcfg_pull_none_smt>;
};
};
i2c4 {
/omit-if-no-ref/
i2c4m1_xfer: i2c4m1-xfer {
rockchip,pins =
/* i2c4_scl_m1 */
<2 RK_PB5 9 &pcfg_pull_none_smt>,
/* i2c4_sda_m1 */
<2 RK_PB4 9 &pcfg_pull_none_smt>;
};
};
i2c5 {
/omit-if-no-ref/
i2c5m4_xfer: i2c5m4-xfer {
rockchip,pins =
/* i2c5_scl_m4 */
<2 RK_PB6 9 &pcfg_pull_none_smt>,
/* i2c5_sda_m4 */
<2 RK_PB7 9 &pcfg_pull_none_smt>;
};
};
i2c6 {
/omit-if-no-ref/
i2c6m2_xfer: i2c6m2-xfer {
rockchip,pins =
/* i2c6_scl_m2 */
<2 RK_PC3 9 &pcfg_pull_none_smt>,
/* i2c6_sda_m2 */
<2 RK_PC2 9 &pcfg_pull_none_smt>;
};
};
i2c7 {
/omit-if-no-ref/
i2c7m1_xfer: i2c7m1-xfer {
rockchip,pins =
/* i2c7_scl_m1 */
<4 RK_PC3 9 &pcfg_pull_none_smt>,
/* i2c7_sda_m1 */
<4 RK_PC4 9 &pcfg_pull_none_smt>;
};
};
i2c8 {
/omit-if-no-ref/
i2c8m1_xfer: i2c8m1-xfer {
rockchip,pins =
/* i2c8_scl_m1 */
<2 RK_PB0 9 &pcfg_pull_none_smt>,
/* i2c8_sda_m1 */
<2 RK_PB1 9 &pcfg_pull_none_smt>;
};
};
i2s2 {
/omit-if-no-ref/
i2s2m0_lrck: i2s2m0-lrck {
rockchip,pins =
/* i2s2m0_lrck */
<2 RK_PC0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m0_mclk: i2s2m0-mclk {
rockchip,pins =
/* i2s2m0_mclk */
<2 RK_PB6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m0_sclk: i2s2m0-sclk {
rockchip,pins =
/* i2s2m0_sclk */
<2 RK_PB7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m0_sdi: i2s2m0-sdi {
rockchip,pins =
/* i2s2m0_sdi */
<2 RK_PC3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m0_sdo: i2s2m0-sdo {
rockchip,pins =
/* i2s2m0_sdo */
<4 RK_PC3 2 &pcfg_pull_none>;
};
};
pwm2 {
/omit-if-no-ref/
pwm2m2_pins: pwm2m2-pins {
rockchip,pins =
/* pwm2_m2 */
<4 RK_PC2 11 &pcfg_pull_none>;
};
};
pwm4 {
/omit-if-no-ref/
pwm4m1_pins: pwm4m1-pins {
rockchip,pins =
/* pwm4_m1 */
<4 RK_PC3 11 &pcfg_pull_none>;
};
};
pwm5 {
/omit-if-no-ref/
pwm5m2_pins: pwm5m2-pins {
rockchip,pins =
/* pwm5_m2 */
<4 RK_PC4 11 &pcfg_pull_none>;
};
};
pwm6 {
/omit-if-no-ref/
pwm6m2_pins: pwm6m2-pins {
rockchip,pins =
/* pwm6_m2 */
<4 RK_PC5 11 &pcfg_pull_none>;
};
};
pwm7 {
/omit-if-no-ref/
pwm7m3_pins: pwm7m3-pins {
rockchip,pins =
/* pwm7_ir_m3 */
<4 RK_PC6 11 &pcfg_pull_none>;
};
};
sdio {
/omit-if-no-ref/
sdiom0_pins: sdiom0-pins {
rockchip,pins =
/* sdio_clk_m0 */
<2 RK_PB3 2 &pcfg_pull_none>,
/* sdio_cmd_m0 */
<2 RK_PB2 2 &pcfg_pull_none>,
/* sdio_d0_m0 */
<2 RK_PA6 2 &pcfg_pull_none>,
/* sdio_d1_m0 */
<2 RK_PA7 2 &pcfg_pull_none>,
/* sdio_d2_m0 */
<2 RK_PB0 2 &pcfg_pull_none>,
/* sdio_d3_m0 */
<2 RK_PB1 2 &pcfg_pull_none>;
};
};
spi1 {
/omit-if-no-ref/
spi1m0_pins: spi1m0-pins {
rockchip,pins =
/* spi1_clk_m0 */
<2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
/* spi1_miso_m0 */
<2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
/* spi1_mosi_m0 */
<2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi1m0_cs0: spi1m0-cs0 {
rockchip,pins =
/* spi1_cs0_m0 */
<2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi1m0_cs1: spi1m0-cs1 {
rockchip,pins =
/* spi1_cs1_m0 */
<2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
};
};
spi3 {
/omit-if-no-ref/
spi3m0_pins: spi3m0-pins {
rockchip,pins =
/* spi3_clk_m0 */
<4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
/* spi3_miso_m0 */
<4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
/* spi3_mosi_m0 */
<4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi3m0_cs0: spi3m0-cs0 {
rockchip,pins =
/* spi3_cs0_m0 */
<4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi3m0_cs1: spi3m0-cs1 {
rockchip,pins =
/* spi3_cs1_m0 */
<4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
};
};
uart1 {
/omit-if-no-ref/
uart1m0_xfer: uart1m0-xfer {
rockchip,pins =
/* uart1_rx_m0 */
<2 RK_PB6 10 &pcfg_pull_up>,
/* uart1_tx_m0 */
<2 RK_PB7 10 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart1m0_ctsn: uart1m0-ctsn {
rockchip,pins =
/* uart1m0_ctsn */
<2 RK_PC1 10 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m0_rtsn: uart1m0-rtsn {
rockchip,pins =
/* uart1m0_rtsn */
<2 RK_PC0 10 &pcfg_pull_none>;
};
};
uart6 {
/omit-if-no-ref/
uart6m0_xfer: uart6m0-xfer {
rockchip,pins =
/* uart6_rx_m0 */
<2 RK_PA6 10 &pcfg_pull_up>,
/* uart6_tx_m0 */
<2 RK_PA7 10 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart6m0_ctsn: uart6m0-ctsn {
rockchip,pins =
/* uart6m0_ctsn */
<2 RK_PB1 10 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart6m0_rtsn: uart6m0-rtsn {
rockchip,pins =
/* uart6m0_rtsn */
<2 RK_PB0 10 &pcfg_pull_none>;
};
};
uart7 {
/omit-if-no-ref/
uart7m0_xfer: uart7m0-xfer {
rockchip,pins =
/* uart7_rx_m0 */
<2 RK_PB4 10 &pcfg_pull_up>,
/* uart7_tx_m0 */
<2 RK_PB5 10 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart7m0_ctsn: uart7m0-ctsn {
rockchip,pins =
/* uart7m0_ctsn */
<4 RK_PC6 10 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart7m0_rtsn: uart7m0-rtsn {
rockchip,pins =
/* uart7m0_rtsn */
<4 RK_PC2 10 &pcfg_pull_none>;
};
};
uart9 {
/omit-if-no-ref/
uart9m0_xfer: uart9m0-xfer {
rockchip,pins =
/* uart9_rx_m0 */
<2 RK_PC4 10 &pcfg_pull_up>,
/* uart9_tx_m0 */
<2 RK_PC2 10 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart9m0_ctsn: uart9m0-ctsn {
rockchip,pins =
/* uart9m0_ctsn */
<4 RK_PC5 10 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart9m0_rtsn: uart9m0-rtsn {
rockchip,pins =
/* uart9m0_rtsn */
<4 RK_PC4 10 &pcfg_pull_none>;
};
};
};

22
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Collabora Ltd.
*/
#include "rk3588-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &sdmmc;
};
};
&sdmmc {
bus-width = <4>;
bootph-pre-ram;
status = "okay";
};

44
arch/arm/dts/rk3588-rock-5b.dts Normal file
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@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3588.dtsi"
/ {
model = "Radxa ROCK 5 Model B";
compatible = "radxa,rock-5b", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

7
arch/arm/dts/rk3588-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include "rockchip-u-boot.dtsi"
#include "rk3588s-u-boot.dtsi"

58
arch/arm/dts/rk3588.dtsi Normal file
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@ -0,0 +1,58 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "rk3588s.dtsi"
#include "rk3588-pinctrl.dtsi"
/ {
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
<&cru CLK_GMAC0_PTP_REF>;
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
power-domains = <&power RK3588_PD_GMAC>;
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";
rockchip,grf = <&sys_grf>;
rockchip,php-grf = <&php_grf>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
};
};

3403
arch/arm/dts/rk3588s-pinctrl.dtsi Normal file
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File diff suppressed because it is too large Load diff

71
arch/arm/dts/rk3588s-u-boot.dtsi Normal file
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@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include "rockchip-u-boot.dtsi"
/ {
dmc {
compatible = "rockchip,rk3588-dmc";
bootph-all;
status = "okay";
};
pmu1_grf: syscon@fd58a000 {
bootph-all;
compatible = "rockchip,rk3588-pmu1-grf", "syscon";
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
sdmmc: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>,
<&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
clock-names = "ciu-drive", "ciu-sample", "biu", "ciu";
fifo-depth = <0x100>;
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
status = "disabled";
};
otp: nvmem@fecc0000 {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc0000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
cpu_id: id@7 {
reg = <0x07 0x10>;
};
};
};
&xin24m {
bootph-all;
status = "okay";
};
&cru {
bootph-pre-ram;
status = "okay";
};
&sys_grf {
bootph-pre-ram;
status = "okay";
};
&uart2 {
clock-frequency = <24000000>;
bootph-pre-ram;
status = "okay";
};
&ioc {
bootph-pre-ram;
};

1703
arch/arm/dts/rk3588s.dtsi Normal file
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File diff suppressed because it is too large Load diff

10
arch/arm/dts/rockchip-u-boot.dtsi
View file

@ -20,9 +20,12 @@
mkimage {
filename = "idbloader.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
#ifdef CONFIG_TPL
multiple-data-files;
#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
rockchip-tpl {
};
#elif defined(CONFIG_TPL)
u-boot-tpl {
};
#endif
@ -134,9 +137,12 @@
mkimage {
filename = "idbloader-spi.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rkspi";
#ifdef CONFIG_TPL
multiple-data-files;
#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
rockchip-tpl {
};
#elif defined(CONFIG_TPL)
u-boot-tpl {
};
#endif

2
arch/arm/dts/sama7g5.dtsi
View file

@ -151,7 +151,7 @@
0x1 0x0 0x48000000 0x8000000
0x2 0x0 0x50000000 0x8000000
0x3 0x0 0x58000000 0x8000000>;
clocks = <&pmc PMC_TYPE_CORE 13>; /* PMC_MCK1 */
clocks = <&pmc PMC_TYPE_CORE 23>; /* PMC_MCK1 */
status = "disabled";
nand_controller: nand-controller {

11
arch/arm/include/asm/arch-rk3588/boot0.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3588/gpio.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

24
arch/arm/include/asm/arch-rockchip/clock.h
View file

@ -22,6 +22,14 @@ enum {
ROCKCHIP_SYSCON_PMUSGRF,
ROCKCHIP_SYSCON_CIC,
ROCKCHIP_SYSCON_MSCH,
ROCKCHIP_SYSCON_USBGRF,
ROCKCHIP_SYSCON_PCIE30_PHY_GRF,
ROCKCHIP_SYSCON_PHP_GRF,
ROCKCHIP_SYSCON_PIPE_PHY0_GRF,
ROCKCHIP_SYSCON_PIPE_PHY1_GRF,
ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
ROCKCHIP_SYSCON_VOP_GRF,
ROCKCHIP_SYSCON_VO_GRF,
};
/* Standard Rockchip clock numbers */
@ -61,6 +69,15 @@ enum rk_clk_id {
.frac = _frac, \
}
#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
{ \
.rate = _rate##U, \
.p = _p, \
.m = _m, \
.s = _s, \
.k = _k, \
}
struct rockchip_pll_rate_table {
unsigned long rate;
unsigned int nr;
@ -74,6 +91,11 @@ struct rockchip_pll_rate_table {
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
/* for RK3588 */
unsigned int m;
unsigned int p;
unsigned int s;
unsigned int k;
};
enum rockchip_pll_type {
@ -82,6 +104,7 @@ enum rockchip_pll_type {
pll_rk3328,
pll_rk3366,
pll_rk3399,
pll_rk3588,
};
struct rockchip_pll_clock {
@ -171,5 +194,6 @@ int rockchip_get_clk(struct udevice **devp);
* Return: 0 success, or error value
*/
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
int rockchip_get_scmi_clk(struct udevice **devp);
#endif

451
arch/arm/include/asm/arch-rockchip/cru_rk3588.h Normal file
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@ -0,0 +1,451 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang <zhangqing@rock-chips.com>
*/
#ifndef _ASM_ARCH_CRU_RK3588_H
#define _ASM_ARCH_CRU_RK3588_H
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
#define CPU_PVTPLL_HZ (1008 * MHz)
#define LPLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1500 * MHz)
#define NPLL_HZ (850 * MHz)
#define PPLL_HZ (1100 * MHz)
/* RK3588 pll id */
enum rk3588_pll_id {
B0PLL,
B1PLL,
LPLL,
CPLL,
GPLL,
NPLL,
V0PLL,
AUPLL,
PPLL,
PLL_COUNT,
};
struct rk3588_clk_info {
unsigned long id;
char *name;
bool is_cru;
};
struct rk3588_clk_priv {
struct rk3588_cru *cru;
struct rk3588_grf *grf;
ulong ppll_hz;
ulong gpll_hz;
ulong cpll_hz;
ulong npll_hz;
ulong v0pll_hz;
ulong aupll_hz;
ulong armclk_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
};
struct rk3588_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int reserved0[3];
};
struct rk3588_cru {
struct rk3588_pll pll[18];
unsigned int reserved0[16];/* Address Offset: 0x0240 */
unsigned int mode_con00;/* Address Offset: 0x0280 */
unsigned int reserved1[31];/* Address Offset: 0x0284 */
unsigned int clksel_con[178]; /* Address Offset: 0x0300 */
unsigned int reserved2[142];/* Address Offset: 0x05c8 */
unsigned int clkgate_con[78];/* Address Offset: 0x0800 */
unsigned int reserved3[50];/* Address Offset: 0x0938 */
unsigned int softrst_con[78];/* Address Offset: 0x0400 */
unsigned int reserved4[50];/* Address Offset: 0x0b38 */
unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
unsigned int glb_rst_st;/* Address Offset: 0x0c04 */
unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */
unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */
unsigned int glb_rst_con;/* Address Offset: 0x0c10 */
unsigned int reserved5[4];/* Address Offset: 0x0c14 */
unsigned int sdio_con[2];/* Address Offset: 0x0c24 */
unsigned int reserved7;/* Address Offset: 0x0c2c */
unsigned int sdmmc_con[2];/* Address Offset: 0x0c30 */
unsigned int reserved8[48562];/* Address Offset: 0x0c38 */
unsigned int pmuclksel_con[21]; /* Address Offset: 0x0100 */
unsigned int reserved9[299];/* Address Offset: 0x0c38 */
unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
};
check_member(rk3588_cru, mode_con00, 0x280);
check_member(rk3588_cru, pmuclksel_con[1], 0x30304);
struct pll_rate_table {
unsigned long rate;
unsigned int m;
unsigned int p;
unsigned int s;
unsigned int k;
};
#define RK3588_PLL_CON(x) ((x) * 0x4)
#define RK3588_MODE_CON 0x280
#define RK3588_PHP_CRU_BASE 0x8000
#define RK3588_PMU_CRU_BASE 0x30000
#define RK3588_BIGCORE0_CRU_BASE 0x50000
#define RK3588_BIGCORE1_CRU_BASE 0x52000
#define RK3588_DSU_CRU_BASE 0x58000
#define RK3588_PLL_CON(x) ((x) * 0x4)
#define RK3588_MODE_CON0 0x280
#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
#define RK3588_GLB_CNT_TH 0xc00
#define RK3588_GLB_SRST_FST 0xc08
#define RK3588_GLB_SRST_SND 0xc0c
#define RK3588_GLB_RST_CON 0xc10
#define RK3588_GLB_RST_ST 0xc04
#define RK3588_SDIO_CON0 0xC24
#define RK3588_SDIO_CON1 0xC28
#define RK3588_SDMMC_CON0 0xC30
#define RK3588_SDMMC_CON1 0xC34
#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
#define RK3588_B0_PLL_MODE_CON (RK3588_BIGCORE0_CRU_BASE + 0x280)
#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
#define RK3588_B1_PLL_MODE_CON (RK3588_BIGCORE1_CRU_BASE + 0x280)
#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
#define RK3588_LPLL_MODE_CON (RK3588_DSU_CRU_BASE + 0x280)
#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
enum {
/* CRU_CLK_SEL8_CON */
ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,
ACLK_LOW_TOP_ROOT_SRC_SEL_MASK = 1 << ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT,
ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL = 0,
ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL,
ACLK_LOW_TOP_ROOT_DIV_SHIFT = 9,
ACLK_LOW_TOP_ROOT_DIV_MASK = 0x1f << ACLK_LOW_TOP_ROOT_DIV_SHIFT,
PCLK_TOP_ROOT_SEL_SHIFT = 7,
PCLK_TOP_ROOT_SEL_MASK = 3 << PCLK_TOP_ROOT_SEL_SHIFT,
PCLK_TOP_ROOT_SEL_100M = 0,
PCLK_TOP_ROOT_SEL_50M,
PCLK_TOP_ROOT_SEL_24M,
ACLK_TOP_ROOT_SRC_SEL_SHIFT = 5,
ACLK_TOP_ROOT_SRC_SEL_MASK = 3 << ACLK_TOP_ROOT_SRC_SEL_SHIFT,
ACLK_TOP_ROOT_SRC_SEL_GPLL = 0,
ACLK_TOP_ROOT_SRC_SEL_CPLL,
ACLK_TOP_ROOT_SRC_SEL_AUPLL,
ACLK_TOP_ROOT_DIV_SHIFT = 0,
ACLK_TOP_ROOT_DIV_MASK = 0x1f << ACLK_TOP_ROOT_DIV_SHIFT,
/* CRU_CLK_SEL9_CON */
ACLK_TOP_S400_SEL_SHIFT = 8,
ACLK_TOP_S400_SEL_MASK = 3 << ACLK_TOP_S400_SEL_SHIFT,
ACLK_TOP_S400_SEL_400M = 0,
ACLK_TOP_S400_SEL_200M,
ACLK_TOP_S200_SEL_SHIFT = 6,
ACLK_TOP_S200_SEL_MASK = 3 << ACLK_TOP_S200_SEL_SHIFT,
ACLK_TOP_S200_SEL_200M = 0,
ACLK_TOP_S200_SEL_100M,
/* CRU_CLK_SEL38_CON */
CLK_I2C8_SEL_SHIFT = 13,
CLK_I2C8_SEL_MASK = 1 << CLK_I2C8_SEL_SHIFT,
CLK_I2C7_SEL_SHIFT = 12,
CLK_I2C7_SEL_MASK = 1 << CLK_I2C7_SEL_SHIFT,
CLK_I2C6_SEL_SHIFT = 11,
CLK_I2C6_SEL_MASK = 1 << CLK_I2C6_SEL_SHIFT,
CLK_I2C5_SEL_SHIFT = 10,
CLK_I2C5_SEL_MASK = 1 << CLK_I2C5_SEL_SHIFT,
CLK_I2C4_SEL_SHIFT = 9,
CLK_I2C4_SEL_MASK = 1 << CLK_I2C4_SEL_SHIFT,
CLK_I2C3_SEL_SHIFT = 8,
CLK_I2C3_SEL_MASK = 1 << CLK_I2C3_SEL_SHIFT,
CLK_I2C2_SEL_SHIFT = 7,
CLK_I2C2_SEL_MASK = 1 << CLK_I2C2_SEL_SHIFT,
CLK_I2C1_SEL_SHIFT = 6,
CLK_I2C1_SEL_MASK = 1 << CLK_I2C1_SEL_SHIFT,
ACLK_BUS_ROOT_SEL_SHIFT = 5,
ACLK_BUS_ROOT_SEL_MASK = 3 << ACLK_BUS_ROOT_SEL_SHIFT,
ACLK_BUS_ROOT_SEL_GPLL = 0,
ACLK_BUS_ROOT_SEL_CPLL,
ACLK_BUS_ROOT_DIV_SHIFT = 0,
ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
/* CRU_CLK_SEL40_CON */
CLK_SARADC_SEL_SHIFT = 14,
CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT,
CLK_SARADC_SEL_GPLL = 0,
CLK_SARADC_SEL_24M,
CLK_SARADC_DIV_SHIFT = 6,
CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT,
/* CRU_CLK_SEL41_CON */
CLK_UART_SRC_SEL_SHIFT = 14,
CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT,
CLK_UART_SRC_SEL_GPLL = 0,
CLK_UART_SRC_SEL_CPLL,
CLK_UART_SRC_DIV_SHIFT = 9,
CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT,
CLK_TSADC_SEL_SHIFT = 8,
CLK_TSADC_SEL_MASK = 0x1 << CLK_TSADC_SEL_SHIFT,
CLK_TSADC_SEL_GPLL = 0,
CLK_TSADC_SEL_24M,
CLK_TSADC_DIV_SHIFT = 0,
CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
/* CRU_CLK_SEL42_CON */
CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
/* CRU_CLK_SEL43_CON */
CLK_UART_SEL_SHIFT = 0,
CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
CLK_UART_SEL_SRC = 0,
CLK_UART_SEL_FRAC,
CLK_UART_SEL_XIN24M,
/* CRU_CLK_SEL59_CON */
CLK_PWM2_SEL_SHIFT = 14,
CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
CLK_PWM1_SEL_SHIFT = 12,
CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
CLK_SPI4_SEL_SHIFT = 10,
CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT,
CLK_SPI3_SEL_SHIFT = 8,
CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
CLK_SPI2_SEL_SHIFT = 6,
CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
CLK_SPI1_SEL_SHIFT = 4,
CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
CLK_SPI0_SEL_SHIFT = 2,
CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
CLK_SPI_SEL_200M = 0,
CLK_SPI_SEL_150M,
CLK_SPI_SEL_24M,
/* CRU_CLK_SEL60_CON */
CLK_PWM3_SEL_SHIFT = 0,
CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT,
CLK_PWM_SEL_100M = 0,
CLK_PWM_SEL_50M,
CLK_PWM_SEL_24M,
/* CRU_CLK_SEL62_CON */
DCLK_DECOM_SEL_SHIFT = 5,
DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
DCLK_DECOM_SEL_GPLL = 0,
DCLK_DECOM_SEL_SPLL,
DCLK_DECOM_DIV_SHIFT = 0,
DCLK_DECOM_DIV_MASK = 0x1F << DCLK_DECOM_DIV_SHIFT,
/* CRU_CLK_SEL77_CON */
CCLK_EMMC_SEL_SHIFT = 14,
CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT,
CCLK_EMMC_SEL_GPLL = 0,
CCLK_EMMC_SEL_CPLL,
CCLK_EMMC_SEL_24M,
CCLK_EMMC_DIV_SHIFT = 8,
CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT,
/* CRU_CLK_SEL78_CON */
SCLK_SFC_SEL_SHIFT = 12,
SCLK_SFC_SEL_MASK = 3 << SCLK_SFC_SEL_SHIFT,
SCLK_SFC_SEL_GPLL = 0,
SCLK_SFC_SEL_CPLL,
SCLK_SFC_SEL_24M,
SCLK_SFC_DIV_SHIFT = 6,
SCLK_SFC_DIV_MASK = 0x3f << SCLK_SFC_DIV_SHIFT,
BCLK_EMMC_SEL_SHIFT = 5,
BCLK_EMMC_SEL_MASK = 1 << BCLK_EMMC_SEL_SHIFT,
BCLK_EMMC_SEL_GPLL = 0,
BCLK_EMMC_SEL_CPLL,
BCLK_EMMC_DIV_SHIFT = 0,
BCLK_EMMC_DIV_MASK = 0x1f << BCLK_EMMC_DIV_SHIFT,
/* CRU_CLK_SEL81_CON */
CLK_GMAC1_PTP_SEL_SHIFT = 13,
CLK_GMAC1_PTP_SEL_MASK = 1 << CLK_GMAC1_PTP_SEL_SHIFT,
CLK_GMAC1_PTP_SEL_CPLL = 0,
CLK_GMAC1_PTP_DIV_SHIFT = 7,
CLK_GMAC1_PTP_DIV_MASK = 0x3f << CLK_GMAC1_PTP_DIV_SHIFT,
CLK_GMAC0_PTP_SEL_SHIFT = 6,
CLK_GMAC0_PTP_SEL_MASK = 1 << CLK_GMAC0_PTP_SEL_SHIFT,
CLK_GMAC0_PTP_SEL_CPLL = 0,
CLK_GMAC0_PTP_DIV_SHIFT = 0,
CLK_GMAC0_PTP_DIV_MASK = 0x3f << CLK_GMAC0_PTP_DIV_SHIFT,
/* CRU_CLK_SEL83_CON */
CLK_GMAC_125M_SEL_SHIFT = 15,
CLK_GMAC_125M_SEL_MASK = 1 << CLK_GMAC_125M_SEL_SHIFT,
CLK_GMAC_125M_SEL_GPLL = 0,
CLK_GMAC_125M_SEL_CPLL,
CLK_GMAC_125M_DIV_SHIFT = 8,
CLK_GMAC_125M_DIV_MASK = 0x7f << CLK_GMAC_125M_DIV_SHIFT,
/* CRU_CLK_SEL84_CON */
CLK_GMAC_50M_SEL_SHIFT = 7,
CLK_GMAC_50M_SEL_MASK = 1 << CLK_GMAC_50M_SEL_SHIFT,
CLK_GMAC_50M_SEL_GPLL = 0,
CLK_GMAC_50M_SEL_CPLL,
CLK_GMAC_50M_DIV_SHIFT = 0,
CLK_GMAC_50M_DIV_MASK = 0x7f << CLK_GMAC_50M_DIV_SHIFT,
/* CRU_CLK_SEL110_CON */
HCLK_VOP_ROOT_SEL_SHIFT = 10,
HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT,
HCLK_VOP_ROOT_SEL_200M = 0,
HCLK_VOP_ROOT_SEL_100M,
HCLK_VOP_ROOT_SEL_50M,
HCLK_VOP_ROOT_SEL_24M,
ACLK_VOP_LOW_ROOT_SEL_SHIFT = 8,
ACLK_VOP_LOW_ROOT_SEL_MASK = 3 << ACLK_VOP_LOW_ROOT_SEL_SHIFT,
ACLK_VOP_LOW_ROOT_SEL_400M = 0,
ACLK_VOP_LOW_ROOT_SEL_200M,
ACLK_VOP_LOW_ROOT_SEL_100M,
ACLK_VOP_LOW_ROOT_SEL_24M,
ACLK_VOP_ROOT_SEL_SHIFT = 5,
ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT,
ACLK_VOP_ROOT_SEL_GPLL = 0,
ACLK_VOP_ROOT_SEL_CPLL,
ACLK_VOP_ROOT_SEL_AUPLL,
ACLK_VOP_ROOT_SEL_NPLL,
ACLK_VOP_ROOT_SEL_SPLL,
ACLK_VOP_ROOT_DIV_SHIFT = 0,
ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
/* CRU_CLK_SEL111_CON */
DCLK1_VOP_SRC_SEL_SHIFT = 14,
DCLK1_VOP_SRC_SEL_MASK = 3 << DCLK1_VOP_SRC_SEL_SHIFT,
DCLK1_VOP_SRC_DIV_SHIFT = 9,
DCLK1_VOP_SRC_DIV_MASK = 0x1f << DCLK1_VOP_SRC_DIV_SHIFT,
DCLK0_VOP_SRC_SEL_SHIFT = 7,
DCLK0_VOP_SRC_SEL_MASK = 3 << DCLK0_VOP_SRC_SEL_SHIFT,
DCLK_VOP_SRC_SEL_GPLL = 0,
DCLK_VOP_SRC_SEL_CPLL,
DCLK_VOP_SRC_SEL_V0PLL,
DCLK_VOP_SRC_SEL_AUPLL,
DCLK0_VOP_SRC_DIV_SHIFT = 0,
DCLK0_VOP_SRC_DIV_MASK = 0x7f << DCLK0_VOP_SRC_DIV_SHIFT,
/* CRU_CLK_SEL112_CON */
DCLK2_VOP_SEL_SHIFT = 11,
DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT,
DCLK1_VOP_SEL_SHIFT = 9,
DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT,
DCLK0_VOP_SEL_SHIFT = 7,
DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT,
DCLK2_VOP_SRC_SEL_SHIFT = 5,
DCLK2_VOP_SRC_SEL_MASK = 3 << DCLK2_VOP_SRC_SEL_SHIFT,
DCLK2_VOP_SRC_DIV_SHIFT = 0,
DCLK2_VOP_SRC_DIV_MASK = 0x1f << DCLK2_VOP_SRC_DIV_SHIFT,
/* CRU_CLK_SEL113_CON */
DCLK3_VOP_SRC_SEL_SHIFT = 7,
DCLK3_VOP_SRC_SEL_MASK = 3 << DCLK3_VOP_SRC_SEL_SHIFT,
DCLK3_VOP_SRC_DIV_SHIFT = 0,
DCLK3_VOP_SRC_DIV_MASK = 0x7f << DCLK3_VOP_SRC_DIV_SHIFT,
/* CRU_CLK_SEL117_CON */
CLK_AUX16MHZ_1_DIV_SHIFT = 8,
CLK_AUX16MHZ_1_DIV_MASK = 0xff << CLK_AUX16MHZ_1_DIV_SHIFT,
CLK_AUX16MHZ_0_DIV_SHIFT = 0,
CLK_AUX16MHZ_0_DIV_MASK = 0xff << CLK_AUX16MHZ_0_DIV_SHIFT,
/* CRU_CLK_SEL165_CON */
PCLK_CENTER_ROOT_SEL_SHIFT = 6,
PCLK_CENTER_ROOT_SEL_MASK = 3 << PCLK_CENTER_ROOT_SEL_SHIFT,
PCLK_CENTER_ROOT_SEL_200M = 0,
PCLK_CENTER_ROOT_SEL_100M,
PCLK_CENTER_ROOT_SEL_50M,
PCLK_CENTER_ROOT_SEL_24M,
HCLK_CENTER_ROOT_SEL_SHIFT = 4,
HCLK_CENTER_ROOT_SEL_MASK = 3 << HCLK_CENTER_ROOT_SEL_SHIFT,
HCLK_CENTER_ROOT_SEL_400M = 0,
HCLK_CENTER_ROOT_SEL_200M,
HCLK_CENTER_ROOT_SEL_100M,
HCLK_CENTER_ROOT_SEL_24M,
ACLK_CENTER_LOW_ROOT_SEL_SHIFT = 2,
ACLK_CENTER_LOW_ROOT_SEL_MASK = 3 << ACLK_CENTER_LOW_ROOT_SEL_SHIFT,
ACLK_CENTER_LOW_ROOT_SEL_500M = 0,
ACLK_CENTER_LOW_ROOT_SEL_250M,
ACLK_CENTER_LOW_ROOT_SEL_100M,
ACLK_CENTER_LOW_ROOT_SEL_24M,
ACLK_CENTER_ROOT_SEL_SHIFT = 0,
ACLK_CENTER_ROOT_SEL_MASK = 3 << ACLK_CENTER_ROOT_SEL_SHIFT,
ACLK_CENTER_ROOT_SEL_700M = 0,
ACLK_CENTER_ROOT_SEL_400M,
ACLK_CENTER_ROOT_SEL_200M,
ACLK_CENTER_ROOT_SEL_24M,
/* CRU_CLK_SEL172_CON */
CCLK_SDIO_SRC_SEL_SHIFT = 8,
CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT,
CCLK_SDIO_SRC_SEL_GPLL = 0,
CCLK_SDIO_SRC_SEL_CPLL,
CCLK_SDIO_SRC_SEL_24M,
CCLK_SDIO_SRC_DIV_SHIFT = 2,
CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
/* CRU_CLK_SEL176_CON */
CLK_PCIE_PHY1_PLL_DIV_SHIFT = 6,
CLK_PCIE_PHY1_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY1_PLL_DIV_SHIFT,
CLK_PCIE_PHY0_PLL_DIV_SHIFT = 0,
CLK_PCIE_PHY0_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY0_PLL_DIV_SHIFT,
/* CRU_CLK_SEL177_CON */
CLK_PCIE_PHY2_REF_SEL_SHIFT = 8,
CLK_PCIE_PHY2_REF_SEL_MASK = 1 << CLK_PCIE_PHY2_REF_SEL_SHIFT,
CLK_PCIE_PHY1_REF_SEL_SHIFT = 7,
CLK_PCIE_PHY1_REF_SEL_MASK = 1 << CLK_PCIE_PHY1_REF_SEL_SHIFT,
CLK_PCIE_PHY0_REF_SEL_SHIFT = 6,
CLK_PCIE_PHY0_REF_SEL_MASK = 1 << CLK_PCIE_PHY0_REF_SEL_SHIFT,
CLK_PCIE_PHY_REF_SEL_24M = 0,
CLK_PCIE_PHY_REF_SEL_PPLL,
CLK_PCIE_PHY2_PLL_DIV_SHIFT = 0,
CLK_PCIE_PHY2_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY2_PLL_DIV_SHIFT,
/* PMUCRU_CLK_SEL2_CON */
CLK_PMU1PWM_SEL_SHIFT = 9,
CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT,
/* PMUCRU_CLK_SEL3_CON */
CLK_I2C0_SEL_SHIFT = 6,
CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT,
CLK_I2C_SEL_200M = 0,
CLK_I2C_SEL_100M,
};
#endif

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arch/arm/include/asm/arch-rockchip/grf_rk3588.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#ifndef __SOC_ROCKCHIP_RK3588_GRF_H__
#define __SOC_ROCKCHIP_RK3588_GRF_H__
struct rk3588_pmu1grf {
unsigned int soc_con[12];
unsigned int reserved0[(0x0050 - 0x002c) / 4 - 1];
unsigned int biu_con;
unsigned int biu_sts;
unsigned int reserved1[(0x0060 - 0x0054) / 4 - 1];
unsigned int soc_sts;
unsigned int reserved2[(0x0080 - 0x0060) / 4 - 1];
unsigned int mem_con[4];
unsigned int reserved3[(0x0200 - 0x008c) / 4 - 1];
unsigned int os_reg[8];
unsigned int reserved4[(0x0230 - 0x021c) / 4 - 1];
unsigned int rst_sts;
unsigned int rst_clr;
unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
unsigned int sd_detect_con;
unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
unsigned int sd_detect_sts;
unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
unsigned int sd_detect_clr;
unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
unsigned int sd_detect_cnt;
};
check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0);
#endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */

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arch/arm/include/asm/arch-rockchip/ioc_rk3588.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_IOC_RK3588_H
#define _ASM_ARCH_IOC_RK3588_H
struct rk3588_bus_ioc {
unsigned int reserved0000[3]; /* Address Offset: 0x0000 */
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
unsigned int gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
unsigned int gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
unsigned int gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
unsigned int gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
unsigned int gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
unsigned int gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
unsigned int gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
unsigned int gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
unsigned int gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
unsigned int gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
unsigned int gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */
unsigned int gpio2b_iomux_sel_h; /* Address Offset: 0x004C */
unsigned int gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */
unsigned int gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */
unsigned int gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */
unsigned int gpio2d_iomux_sel_h; /* Address Offset: 0x005C */
unsigned int gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
unsigned int gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
unsigned int gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
unsigned int gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
unsigned int gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
unsigned int gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */
unsigned int gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */
unsigned int gpio3d_iomux_sel_h; /* Address Offset: 0x007C */
unsigned int gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
unsigned int gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
unsigned int gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
unsigned int gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
unsigned int gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
unsigned int gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
unsigned int gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
unsigned int gpio4d_iomux_sel_h; /* Address Offset: 0x009C */
};
check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
struct rk3588_pmu1_ioc {
unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
unsigned int gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */
unsigned int reserved0012; /* Address Offset: 0x000C */
unsigned int gpio0a_ds_l; /* Address Offset: 0x0010 */
unsigned int gpio0a_ds_h; /* Address Offset: 0x0014 */
unsigned int gpio0b_ds_l; /* Address Offset: 0x0018 */
unsigned int reserved0028; /* Address Offset: 0x001C */
unsigned int gpio0a_p; /* Address Offset: 0x0020 */
unsigned int gpio0b_p; /* Address Offset: 0x0024 */
unsigned int gpio0a_ie; /* Address Offset: 0x0028 */
unsigned int gpio0b_ie; /* Address Offset: 0x002C */
unsigned int gpio0a_smt; /* Address Offset: 0x0030 */
unsigned int gpio0b_smt; /* Address Offset: 0x0034 */
unsigned int gpio0a_pdis; /* Address Offset: 0x0038 */
unsigned int gpio0b_pdis; /* Address Offset: 0x003C */
unsigned int xin_con; /* Address Offset: 0x0040 */
};
check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
struct rk3588_pmu2_ioc {
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */
unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x000C */
unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */
unsigned int gpio0b_ds_h; /* Address Offset: 0x0014 */
unsigned int gpio0c_ds_l; /* Address Offset: 0x0018 */
unsigned int gpio0c_ds_h; /* Address Offset: 0x001C */
unsigned int gpio0d_ds_l; /* Address Offset: 0x0020 */
unsigned int gpio0d_ds_h; /* Address Offset: 0x0024 */
unsigned int gpio0b_p; /* Address Offset: 0x0028 */
unsigned int gpio0c_p; /* Address Offset: 0x002C */
unsigned int gpio0d_p; /* Address Offset: 0x0030 */
unsigned int gpio0b_ie; /* Address Offset: 0x0034 */
unsigned int gpio0c_ie; /* Address Offset: 0x0038 */
unsigned int gpio0d_ie; /* Address Offset: 0x003C */
unsigned int gpio0b_smt; /* Address Offset: 0x0040 */
unsigned int gpio0c_smt; /* Address Offset: 0x0044 */
unsigned int gpio0d_smt; /* Address Offset: 0x0048 */
unsigned int gpio0b_pdis; /* Address Offset: 0x004C */
unsigned int gpio0c_pdis; /* Address Offset: 0x0050 */
unsigned int gpio0d_pdis; /* Address Offset: 0x0054 */
};
check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054);
#endif

28
arch/arm/include/asm/arch-rockchip/sdram.h
View file

@ -8,10 +8,13 @@
enum {
DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
LPDDR4 = 0x7,
DDR3 = 3,
LPDDR2 = 5,
LPDDR3 = 6,
LPDDR4 = 7,
LPDDR4X = 8,
LPDDR5 = 9,
DDR5 = 10,
UNUSED = 0xFF
};
@ -21,16 +24,16 @@ enum {
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [26:25] cs0_col_ch1
* [24] bk_ch1
* [23:22] low bits of cs0_row_ch1
* [21:20] low bits of cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [17:16] dbw_ch1
* [15:13] low bits of ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0,
* [11] low bit of rank_ch0
* [10:9] cs0_col_ch0
* [8] bk_ch0
* [7:6] low bits of cs0_row_ch0
* [5:4] low bits of cs1_row_ch0
@ -61,6 +64,11 @@ enum {
/*
* sys_reg3 bitfield struct
* [31:28] version
* [16] cs3_delta_row
* [15] cs2_delta_row
* [14] high bit of rank_ch0
* [13:12] high bits of ddrtype
* [7] high bit of cs0_row_ch1
* [6] high bit of cs1_row_ch1
* [5] high bit of cs0_row_ch0
@ -70,6 +78,8 @@ enum {
*/
#define SYS_REG_VERSION_SHIFT 28
#define SYS_REG_VERSION_MASK 0xf
#define SYS_REG_EXTEND_DDRTYPE_SHIFT 12
#define SYS_REG_EXTEND_DDRTYPE_MASK 3
#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2)
#define SYS_REG_EXTEND_CS0_ROW_MASK 1
#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2)

34
arch/arm/mach-rockchip/Kconfig
View file

@ -286,7 +286,11 @@ config ROCKCHIP_RK3568
select REGMAP
select SYSCON
select BOARD_LATE_INIT
select DM_REGULATOR_FIXED
select DM_RESET
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply MISC_INIT_R
help
The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
@ -294,6 +298,27 @@ config ROCKCHIP_RK3568
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
config ROCKCHIP_RK3588
bool "Support Rockchip RK3588"
select ARM64
select SUPPORT_SPL
select SPL
select CLK
select PINCTRL
select RAM
select REGMAP
select SYSCON
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply MISC_INIT_R
help
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
SDIO3.0 I2C, UART, SPI, GPIO and PWM.
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@ -401,6 +426,14 @@ config TPL_ROCKCHIP_COMMON_BOARD
common board is a basic TPL board init which can be shared for most
of SoCs to avoid copy-paste for different SoCs.
config ROCKCHIP_EXTERNAL_TPL
bool "Use external TPL binary"
default y if ROCKCHIP_RK3568
help
Some Rockchip SoCs require an external TPL to initialize DRAM.
Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
include the external TPL in the image built by binman.
config ROCKCHIP_BOOT_MODE_REG
hex "Rockchip boot mode flag register address"
help
@ -491,6 +524,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
endif

1
arch/arm/mach-rockchip/Makefile
View file

@ -44,6 +44,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/

2
arch/arm/mach-rockchip/board.c
View file

@ -323,7 +323,7 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
#ifdef CONFIG_MISC_INIT_R
__weak int misc_init_r(void)
{
const u32 cpuid_offset = 0x7;
const u32 cpuid_offset = CFG_CPUID_OFFSET;
const u32 cpuid_length = 0x10;
u8 cpuid[cpuid_length];
int ret;

6
arch/arm/mach-rockchip/misc.c
View file

@ -23,7 +23,7 @@
int rockchip_setup_macaddr(void)
{
#if IS_ENABLED(CONFIG_CMD_NET)
#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256)
int ret;
const char *cpuid = env_get("cpuid#");
u8 hash[SHA256_SUM_LEN];
@ -52,6 +52,10 @@ int rockchip_setup_macaddr(void)
mac_addr[0] &= 0xfe; /* clear multicast bit */
mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
eth_env_set_enetaddr("ethaddr", mac_addr);
/* Make a valid MAC address for ethernet1 */
mac_addr[5] ^= 0x01;
eth_env_set_enetaddr("eth1addr", mac_addr);
#endif
return 0;
}

31
arch/arm/mach-rockchip/rk3568/rk3568.c
View file

@ -7,6 +7,7 @@
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
@ -23,6 +24,16 @@
#define SGRF_SOC_CON4 0x10
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
#define PMU_BASE_ADDR 0xfdd90000
#define PMU_NOC_AUTO_CON0 (0x70)
#define PMU_NOC_AUTO_CON1 (0x74)
#define EDP_PHY_GRF_BASE 0xfdcb0000
#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
#define CPU_GRF_BASE 0xfdc30000
#define GRF_CORE_PVTPLL_CON0 (0x10)
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@ -70,6 +81,12 @@ static struct mm_region rk3568_mem_map[] = {
}
};
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
};
struct mm_region *mem_map = rk3568_mem_map;
void board_debug_uart_init(void)
@ -91,6 +108,20 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
/*
* When perform idle operation, corresponding clock can
* be opened or gated automatically.
*/
writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
/* Disable eDP phy by default */
writel(0x00070007, EDP_PHY_GRF_CON10);
writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
/* Set core pvtpll ring length */
writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
/* Set the emmc sdmmc0 to secure */
rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
| SDMMC0_HPROT_SECURE_CTRL << 4));

56
arch/arm/mach-rockchip/rk3588/Kconfig Normal file
View file

@ -0,0 +1,56 @@
if ROCKCHIP_RK3588
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
help
Neu6:
Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
Neu6-IO:
Neural Compute Module 6(Neu6) IO board is an industrial form factor
IO board and Neu6a needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 6(Neu6) IO platform.
config TARGET_ROCK5B_RK3588
bool "Radxa ROCK5B RK3588 board"
select BOARD_LATE_INIT
help
Radxa ROCK5B is a Rockchip RK3588 based SBC (Single Board Computer)
by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x HDMI output, 1x HDMI input
Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 54mm
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
config ROCKCHIP_STIMER_BASE
default 0xfd8c8000
config SYS_SOC
default "rk3588"
config SYS_MALLOC_F_LEN
default 0x80000
source board/edgeble/neural-compute-module-6/Kconfig
source board/radxa/rock5b-rk3588/Kconfig
endif

9
arch/arm/mach-rockchip/rk3588/Makefile Normal file
View file

@ -0,0 +1,9 @@
#
# (C) Copyright 2021 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += rk3588.o
obj-y += clk_rk3588.o
obj-y += syscon_rk3588.o

32
arch/arm/mach-rockchip/rk3588/clk_rk3588.c Normal file
View file

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2020 Rockchip Electronics Co., Ltd.
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3588.h>
#include <linux/err.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(rockchip_rk3588_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk3588_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}

157
arch/arm/mach-rockchip/rk3588/rk3588.c Normal file
View file

@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include <common.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>
DECLARE_GLOBAL_DATA_PTR;
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
#define FW_DDR_MST21_REG 0x94
#define FW_DDR_MST26_REG 0xa8
#define FW_DDR_MST27_REG 0xac
#define FIREWALL_SYSMEM_BASE 0xfe038000
#define FW_SYSM_MST5_REG 0x54
#define FW_SYSM_MST13_REG 0x74
#define FW_SYSM_MST21_REG 0x94
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
#define PMU1_IOC_BASE 0xfd5f0000
#define PMU2_IOC_BASE 0xfd5f4000
#define BUS_IOC_BASE 0xfd5f8000
#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
static struct mm_region rk3588_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xf0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xf0000000UL,
.phys = 0xf0000000UL,
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x900000000,
.phys = 0x900000000,
.size = 0x150000000,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = rk3588_mem_map;
/* GPIO0B_IOMUX_SEL_H */
enum {
GPIO0B5_SHIFT = 4,
GPIO0B5_MASK = GENMASK(7, 4),
GPIO0B5_REFER = 8,
GPIO0B5_UART2_TX_M0 = 10,
GPIO0B6_SHIFT = 8,
GPIO0B6_MASK = GENMASK(11, 8),
GPIO0B6_REFER = 8,
GPIO0B6_UART2_RX_M0 = 10,
};
void board_debug_uart_init(void)
{
__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
/* Refer to BUS_IOC */
rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
GPIO0B6_MASK | GPIO0B5_MASK,
GPIO0B6_REFER << GPIO0B6_SHIFT |
GPIO0B5_REFER << GPIO0B5_SHIFT);
/* UART2_M0 Switch iomux */
rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
GPIO0B6_MASK | GPIO0B5_MASK,
GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
}
#ifdef CONFIG_SPL_BUILD
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
if (reg & 0x1)
return;
asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
}
#endif
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
int secure_reg;
/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
#endif
return 0;
}
#endif

32
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c Normal file
View file

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3588_syscon_ids[] = {
{ .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
{ .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF },
{ .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
{ .compatible = "rockchip,rk3588-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
{ .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY0_GRF },
{ .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY1_GRF },
{ .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY2_GRF },
{ .compatible = "rockchip,rk3588-pmu", .data = ROCKCHIP_SYSCON_PMU },
{ }
};
U_BOOT_DRIVER(syscon_rk3588) = {
.name = "rk3588_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3588_syscon_ids,
#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
};

21
arch/arm/mach-rockchip/sdram.c
View file

@ -37,13 +37,19 @@ struct tos_parameter_t {
int dram_init_banksize(void)
{
size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE),
(unsigned long)(gd->ram_top));
size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
/* Add usable memory beyond the blob of space for peripheral near 4GB */
if (ram_top > SZ_4G && top < SZ_4G) {
gd->bd->bi_dram[1].start = SZ_4G;
gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
}
#else
#ifdef CONFIG_SPL_OPTEE_IMAGE
struct tos_parameter_t *tos_parameter;
@ -88,9 +94,15 @@ size_t rockchip_sdram_size(phys_addr_t reg)
u32 sys_reg3 = readl(reg + 4);
u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
& SYS_REG_NUM_CH_MASK);
u32 version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) &
SYS_REG_VERSION_MASK;
dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
if (version >= 3)
dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
debug("%s %x %x\n", __func__, (u32)reg + 4, sys_reg3);
for (ch = 0; ch < ch_num; ch++) {
rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
SYS_REG_RANK_MASK);
@ -98,8 +110,7 @@ size_t rockchip_sdram_size(phys_addr_t reg)
SYS_REG_COL_MASK);
cs1_col = cs0_col;
bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
SYS_REG_VERSION_MASK) == 0x2) {
if (version >= 2) {
cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
SYS_REG_CS1_COL_MASK);
if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
@ -176,7 +187,7 @@ size_t rockchip_sdram_size(phys_addr_t reg)
* 2. update board_get_usable_ram_top() and dram_init_banksize()
* to reserve memory for peripheral space after previous update.
*/
if (size_mb > (SDRAM_MAX_SIZE >> 20))
if (!IS_ENABLED(CONFIG_ARM64) && size_mb > (SDRAM_MAX_SIZE >> 20))
size_mb = (SDRAM_MAX_SIZE >> 20);
return (size_t)size_mb << 20;

6
arch/sandbox/include/asm/types.h
View file

@ -18,11 +18,7 @@ typedef unsigned short umode_t;
/*
* Number of bits in a C 'long' on this architecture.
*/
#ifdef CONFIG_PHYS_64BIT
#define BITS_PER_LONG 64
#else /* CONFIG_PHYS_64BIT */
#define BITS_PER_LONG 32
#endif /* CONFIG_PHYS_64BIT */
#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG
#ifdef CONFIG_PHYS_64BIT
typedef unsigned long long dma_addr_t;

2
board/edgeble/neural-compute-module-2/MAINTAINERS
View file

@ -1,4 +1,4 @@
RV1126-ECM0
RV1126-NEU2
M: Jagan Teki <jagan@edgeble.ai>
S: Maintained
F: board/edgeble/neural-compute-module-2

15
board/edgeble/neural-compute-module-6/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_RK3588_NEU6
config SYS_BOARD
default "neural-compute-module-6"
config SYS_VENDOR
default "edgeble"
config SYS_CONFIG_NAME
default "neural-compute-module-6"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/edgeble/neural-compute-module-6/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
RK3588-NEU6
M: Jagan Teki <jagan@edgeble.ai>
S: Maintained
F: board/edgeble/neural-compute-module-6
F: include/configs/neural-compute-module-6.h
F: configs/neu6a-io-rk3588_defconfig

7
board/edgeble/neural-compute-module-6/Makefile Normal file
View file

@ -0,0 +1,7 @@
#
# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += neu6.o

4
board/edgeble/neural-compute-module-6/neu6.c Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/

15
board/radxa/rock5b-rk3588/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_ROCK5B_RK3588
config SYS_BOARD
default "rock5b-rk3588"
config SYS_VENDOR
default "radxa"
config SYS_CONFIG_NAME
default "rock5b-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/radxa/rock5b-rk3588/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
ROCK5B-RK3588
M: Eugen Hristev <eugen.hristev@collabora.com>
S: Maintained
F: board/radxa/rock5b-rk3588
F: include/configs/rock5b-rk3588
F: configs/rock5b-rk3588_defconfig

6
board/radxa/rock5b-rk3588/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2022 Collabora Ltd.
#
obj-y += rock5b-rk3588.o

39
board/radxa/rock5b-rk3588/rock5b-rk3588.c Normal file
View file

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2023 Collabora Ltd.
*/
#include <fdtdec.h>
#include <fdt_support.h>
#ifdef CONFIG_OF_BOARD_SETUP
int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
{
struct fdt_memory gap1 = {
.start = 0x3fc000000,
.end = 0x3fc4fffff,
};
struct fdt_memory gap2 = {
.start = 0x3fff00000,
.end = 0x3ffffffff,
};
unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
unsigned int ret;
/*
* Inject the reserved-memory nodes into the DTS
*/
ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
NULL, flags);
if (ret)
return ret;
return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
NULL, flags);
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
return rock5b_add_reserved_memory_fdt_nodes(blob);
}
#endif

7
board/rockchip/evb_rk3308/MAINTAINERS
View file

@ -4,3 +4,10 @@ S: Maintained
F: board/rockchip/evb_rk3308
F: include/configs/evb_rk3308.h
F: configs/evb-rk3308_defconfig
ROCK-PI-S
M: Akash Gajjar <gajjar04akash@gmail.com>
S: Maintained
F: configs/rock-pi-s-rk3308_defconfig
F: arch/arm/dts/rk3308-rock-pi-s.dts
F: arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi

14
board/rockchip/evb_rk3568/MAINTAINERS
View file

@ -4,3 +4,17 @@ S: Maintained
F: board/rockchip/evb_rk3568
F: include/configs/evb_rk3568.h
F: configs/evb-rk3568_defconfig
F: arch/arm/dts/rk3568-evb-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
RADXA-CM3
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/radxa-cm3-io-rk3566_defconfig
ROCK-3A
M: Akash Gajjar <gajjar04akash@gmail.com>
S: Maintained
F: configs/rock-3a-rk3568_defconfig
F: arch/arm/dts/rk3568-rock-3a.dts
F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi

12
common/Kconfig
View file

@ -1154,15 +1154,3 @@ config FDT_SIMPLEFB
config IO_TRACE
bool
config USB_HUB_DEBOUNCE_TIMEOUT
int "Timeout in milliseconds for USB HUB connection"
depends on USB
default 1000
help
Value in milliseconds of the USB connection timeout, the max delay to
wait the hub port status to be connected steadily after being powered
off and powered on in the usb hub driver.
This define allows to increase the HUB_DEBOUNCE_TIMEOUT default
value = 1s because some usb device needs around 1.5s to be initialized
and a 2s value should solve detection issue on problematic USB keys.

2
common/Makefile
View file

@ -24,7 +24,7 @@ obj-$(CONFIG_CMD_MII) += miiphyutil.o
obj-$(CONFIG_PHYLIB) += miiphyutil.o
obj-$(CONFIG_USB_HOST) += usb.o usb_hub.o
obj-$(CONFIG_USB_GADGET) += usb.o usb_hub.o
obj-$(CONFIG_USB_GADGET) += usb.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
obj-$(CONFIG_USB_ONBOARD_HUB) += usb_onboard_hub.o

1
configs/evb-rk3568_defconfig
View file

@ -65,5 +65,4 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y

2
configs/n2350_defconfig
View file

@ -14,7 +14,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
CONFIG_TARGET_N2350=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="armada-385-thecus-n2350"
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SYS_PROMPT="N2350 > "

6
configs/nanopi-r4s-rk3399_defconfig
View file

@ -72,3 +72,9 @@ CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_MISC=y
CONFIG_MISC_INIT_R=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y

67
configs/neu6a-io-rk3588_defconfig Normal file
View file

@ -0,0 +1,67 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_RK3588_NEU6=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y

7
configs/pm9g45_defconfig
View file

@ -14,15 +14,15 @@ CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_ENV_OFFSET_REDUND=0x100000
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_SYS_LOAD_ADDR=0x70000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="fbcon=rotate:3 console=tty0 console=ttyS0,115200 root=/dev/mtdblock4 mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,1664k(env),2M(linux)ro,-(root) rw rootfstype=jffs2"
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:128k(bootstrap)ro,640k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),8M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="nand read 0x70000000 0x200000 0x300000;bootm 0x70000000"
CONFIG_BOOTCOMMAND="nand read 0x70000000 0x180000 0x880000; nand read 0x70080000 0x200000 0x800000; bootz 0x70080000 - 0x70000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_RESET_PHY_R=y
@ -53,7 +53,6 @@ CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_MACB=y

5
configs/r8a77980_condor_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@ -64,6 +65,9 @@ CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
@ -84,6 +88,7 @@ CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y

5
configs/r8a77995_draak_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@ -65,6 +66,9 @@ CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
@ -94,6 +98,7 @@ CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y

77
configs/radxa-cm3-io-rk3566_defconfig Normal file
View file

@ -0,0 +1,77 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

1
configs/ringneck-px30_defconfig
View file

@ -107,6 +107,7 @@ CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_RAM_ROCKCHIP_DDR4=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

74
configs/rock-3a-rk3568_defconfig Normal file
View file

@ -0,0 +1,74 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y

89
configs/rock-pi-s-rk3308_defconfig Normal file
View file

@ -0,0 +1,89 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00600000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
CONFIG_ROCKCHIP_RK3308=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_SPL_STACK_R_ADDR=0xc00000
CONFIG_DEBUG_UART_BASE=0xFF0A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SLEEP is not set
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

72
configs/rock5b-rk3588_defconfig Normal file
View file

@ -0,0 +1,72 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_ROCK5B_RK3588=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYSRESET=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y

4
configs/sandbox_spl_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FPGA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_RTC=y
CONFIG_CMD_CPU=y
@ -126,6 +127,8 @@ CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
CONFIG_SPL_FIRMWARE=y
CONFIG_DM_FPGA=y
CONFIG_SANDBOX_FPGA=y
CONFIG_GPIO_HOG=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_SANDBOX_GPIO=y
@ -237,6 +240,7 @@ CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_RSA_VERIFY_WITH_PKEY=y
CONFIG_TPM=y
CONFIG_SPL_CRC8=y
CONFIG_LZ4=y
CONFIG_ZSTD=y
CONFIG_ERRNO_STR=y

18
doc/board/rockchip/rockchip.rst
View file

@ -86,6 +86,14 @@ List of mainline supported Rockchip boards:
- Radxa ROCK Pi 4 (rock-pi-4-rk3399)
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)
* rk3588
- Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588)
- Radxa ROCK 5B (rock5b-rk3588)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
- Elgin-R1 (elgin-rv1108)
@ -167,6 +175,16 @@ To build rk3399 boards:
make evb-rk3399_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
To build rk3568 boards:
.. code-block:: bash
export BL31=../arm-trusted-firmware/build/rk3568/release/bl31/bl31.elf
[or]export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf
export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1560MHz_v1.13.bin
make evb-rk3568_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
Flashing
--------

2
doc/develop/release_cycle.rst
View file

@ -70,7 +70,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot v2023.04-rc3 was released on Mon 27 February 2023.
.. * U-Boot v2023.04-rc4 was released on Mon 13 March 2023.
* U-Boot v2023.04-rc4 was released on Mon 13 March 2023.
.. * U-Boot v2023.04-rc5 was released on Mon 27 March 2023.

3
doc/develop/uefi/fwu_updates.rst
View file

@ -27,7 +27,8 @@ metadata. Individual drivers can be added based on the type of storage
media, and its partitioning method. Details of the storage device
containing the FWU metadata partitions are specified through a U-Boot
specific device tree property `fwu-mdata-store`. Please refer to
U-Boot `doc <doc/device-tree-bindings/firmware/fwu-mdata-gpt.yaml>`__
U-Boot :download:`fwu-mdata-gpt.yaml
</device-tree-bindings/firmware/fwu-mdata-gpt.yaml>`
for the device tree bindings.
Enabling the FWU Multi Bank Update feature

4
doc/develop/uefi/uefi.rst
View file

@ -386,8 +386,8 @@ is because the FWU feature supports multiple partitions(banks) of
updatable images, and the actual dfu alt number to which the image is
to be written to is determined at runtime, based on the value of the
update bank to which the image is to be written. For more information
on the FWU Multi Bank Update feature, please refer `doc
<doc/develop/uefi/fwu_updates.rst>`__.
on the FWU Multi Bank Update feature, please refer to
:doc:`/develop/uefi/fwu_updates`.
When using the FMP for FIT images, the image index value needs to be
set to 1.

33
doc/usage/cmd/panic.rst Normal file
View file

@ -0,0 +1,33 @@
.. SPDX-License-Identifier: GPL-2.0+:
panic command
=============
Synopis
-------
::
panic [message]
Description
-----------
Display a message and reset the board.
message
text to be displayed
Examples
--------
::
=> panic 'Unrecoverable error'
Unrecoverable error
resetting ...
Configuration
-------------
If CONFIG_PANIC_HANG=y, the user has to reset the board manually.

1
doc/usage/index.rst
View file

@ -65,6 +65,7 @@ Shell commands
cmd/md
cmd/mmc
cmd/mtest
cmd/panic
cmd/part
cmd/pause
cmd/pinmux

1
drivers/clk/renesas/Kconfig
View file

@ -49,6 +49,7 @@ config CLK_RCAR_GEN3
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
select CLK_RCAR_CPG_LIB
select DM_RESET
help
Enable this to support the clocks on Renesas RCar Gen3 SoC.

1
drivers/clk/rockchip/Makefile
View file

@ -16,5 +16,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o

267
drivers/clk/rockchip/clk_pll.c
View file

@ -45,6 +45,10 @@ enum {
#define MIN_FOUTVCO_FREQ (800 * MHZ)
#define MAX_FOUTVCO_FREQ (2000 * MHZ)
#define RK3588_VCO_MIN_HZ (2250UL * MHZ)
#define RK3588_VCO_MAX_HZ (4500UL * MHZ)
#define RK3588_FOUT_MIN_HZ (37UL * MHZ)
#define RK3588_FOUT_MAX_HZ (4500UL * MHZ)
int gcd(int m, int n)
{
@ -164,6 +168,65 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
return rate_table;
}
static struct rockchip_pll_rate_table *
rk3588_pll_clk_set_by_auto(unsigned long fin_hz,
unsigned long fout_hz)
{
struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
u32 p, m, s;
ulong fvco, fref, fout, ffrac;
if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
return NULL;
if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ)
return NULL;
if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
for (s = 0; s <= 6; s++) {
fvco = fout_hz << s;
if (fvco < RK3588_VCO_MIN_HZ ||
fvco > RK3588_VCO_MAX_HZ)
continue;
for (p = 2; p <= 4; p++) {
for (m = 64; m <= 1023; m++) {
if (fvco == m * fin_hz / p) {
rate_table->p = p;
rate_table->m = m;
rate_table->s = s;
rate_table->k = 0;
return rate_table;
}
}
}
}
pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
} else {
for (s = 0; s <= 6; s++) {
fvco = fout_hz << s;
if (fvco < RK3588_VCO_MIN_HZ ||
fvco > RK3588_VCO_MAX_HZ)
continue;
for (p = 1; p <= 4; p++) {
for (m = 64; m <= 1023; m++) {
if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
rate_table->p = p;
rate_table->m = m;
rate_table->s = s;
fref = fin_hz / p;
ffrac = fvco - (m * fref);
fout = ffrac * 65536;
rate_table->k = fout / fref;
return rate_table;
}
}
}
}
pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
}
return NULL;
}
static const struct rockchip_pll_rate_table *
rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
{
@ -174,10 +237,14 @@ rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
break;
rate_table++;
}
if (rate_table->rate != rate)
return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
else
if (rate_table->rate != rate) {
if (pll->type == pll_rk3588)
return rk3588_pll_clk_set_by_auto(24 * MHZ, rate);
else
return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
} else {
return rate_table;
}
}
static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
@ -296,6 +363,192 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
}
}
#define RK3588_PLLCON(i) ((i) * 0x4)
#define RK3588_PLLCON0_M_MASK 0x3ff << 0
#define RK3588_PLLCON0_M_SHIFT 0
#define RK3588_PLLCON1_P_MASK 0x3f << 0
#define RK3588_PLLCON1_P_SHIFT 0
#define RK3588_PLLCON1_S_MASK 0x7 << 6
#define RK3588_PLLCON1_S_SHIFT 6
#define RK3588_PLLCON2_K_MASK 0xffff
#define RK3588_PLLCON2_K_SHIFT 0
#define RK3588_PLLCON1_PWRDOWN BIT(13)
#define RK3588_PLLCON6_LOCK_STATUS BIT(15)
#define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300)
#define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300)
#define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300)
#define RK3588_CORE_DIV_MASK 0x1f
#define RK3588_CORE_L02_DIV_SHIFT 0
#define RK3588_CORE_L13_DIV_SHIFT 7
#define RK3588_CORE_B02_DIV_SHIFT 8
#define RK3588_CORE_B13_DIV_SHIFT 0
static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll,
void __iomem *base, ulong pll_id,
ulong drate)
{
const struct rockchip_pll_rate_table *rate;
rate = rockchip_get_pll_settings(pll, drate);
if (!rate) {
printf("%s unsupported rate\n", __func__);
return -EINVAL;
}
debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
__func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
/*
* When power on or changing PLL setting,
* we must force PLL into slow mode to ensure output stable clock.
*/
if (pll_id == 3)
rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1);
rk_clrsetreg(base + pll->mode_offset,
pll->mode_mask << pll->mode_shift,
RKCLK_PLL_MODE_SLOW << pll->mode_shift);
if (pll_id == 0)
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
RKCLK_PLL_MODE_SLOW << 6);
else if (pll_id == 1)
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
RKCLK_PLL_MODE_SLOW << 6);
else if (pll_id == 2)
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
pll->mode_mask << 14,
RKCLK_PLL_MODE_SLOW << 14);
/* Power down */
rk_setreg(base + pll->con_offset + RK3588_PLLCON(1),
RK3588_PLLCON1_PWRDOWN);
rk_clrsetreg(base + pll->con_offset,
RK3588_PLLCON0_M_MASK,
(rate->m << RK3588_PLLCON0_M_SHIFT));
rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1),
(RK3588_PLLCON1_P_MASK |
RK3588_PLLCON1_S_MASK),
(rate->p << RK3588_PLLCON1_P_SHIFT |
rate->s << RK3588_PLLCON1_S_SHIFT));
if (rate->k) {
rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
RK3588_PLLCON2_K_MASK,
rate->k << RK3588_PLLCON2_K_SHIFT);
}
/* Power up */
rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),
RK3588_PLLCON1_PWRDOWN);
/* waiting for pll lock */
while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) &
RK3588_PLLCON6_LOCK_STATUS)) {
udelay(1);
debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id);
}
rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
if (pll_id == 0) {
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
2 << 6);
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
0 << RK3588_CORE_B02_DIV_SHIFT);
rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1),
RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
0 << RK3588_CORE_B13_DIV_SHIFT);
} else if (pll_id == 1) {
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
pll->mode_mask << 6,
2 << 6);
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
0 << RK3588_CORE_B02_DIV_SHIFT);
rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1),
RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
0 << RK3588_CORE_B13_DIV_SHIFT);
} else if (pll_id == 2) {
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
pll->mode_mask << 14,
2 << 14);
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
0 << RK3588_CORE_L13_DIV_SHIFT);
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
0 << RK3588_CORE_L02_DIV_SHIFT);
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
0 << RK3588_CORE_L13_DIV_SHIFT);
rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
0 << RK3588_CORE_L02_DIV_SHIFT);
}
if (pll_id == 3)
rk_clrsetreg(base + 0x84c, 0x1 << 1, 0);
debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
pll, readl(base + pll->con_offset),
readl(base + pll->con_offset + 0x4),
readl(base + pll->con_offset + 0x8),
readl(base + pll->mode_offset));
return 0;
}
static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll,
void __iomem *base, ulong pll_id)
{
u32 m, p, s, k;
u32 con = 0, shift, mode;
u64 rate, postdiv;
con = readl(base + pll->mode_offset);
shift = pll->mode_shift;
if (pll_id == 8)
mode = RKCLK_PLL_MODE_NORMAL;
else
mode = (con & (pll->mode_mask << shift)) >> shift;
switch (mode) {
case RKCLK_PLL_MODE_SLOW:
return OSC_HZ;
case RKCLK_PLL_MODE_NORMAL:
/* normal mode */
con = readl(base + pll->con_offset);
m = (con & RK3588_PLLCON0_M_MASK) >>
RK3588_PLLCON0_M_SHIFT;
con = readl(base + pll->con_offset + RK3588_PLLCON(1));
p = (con & RK3588_PLLCON1_P_MASK) >>
RK3036_PLLCON0_FBDIV_SHIFT;
s = (con & RK3588_PLLCON1_S_MASK) >>
RK3588_PLLCON1_S_SHIFT;
con = readl(base + pll->con_offset + RK3588_PLLCON(2));
k = (con & RK3588_PLLCON2_K_MASK) >>
RK3588_PLLCON2_K_SHIFT;
rate = OSC_HZ / p;
rate *= m;
if (k) {
/* fractional mode */
u64 frac_rate64 = OSC_HZ * k;
postdiv = p * 65536;
do_div(frac_rate64, postdiv);
rate += frac_rate64;
}
rate = rate >> s;
return rate;
case RKCLK_PLL_MODE_DEEP:
default:
return 32768;
}
}
ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
void __iomem *base,
ulong pll_id)
@ -311,6 +564,10 @@ ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
pll->mode_mask = PLL_RK3328_MODE_MASK;
rate = rk3036_pll_get_rate(pll, base, pll_id);
break;
case pll_rk3588:
pll->mode_mask = PLL_MODE_MASK;
rate = rk3588_pll_get_rate(pll, base, pll_id);
break;
default:
printf("%s: Unknown pll type for pll clk %ld\n",
__func__, pll_id);
@ -336,6 +593,10 @@ int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
pll->mode_mask = PLL_RK3328_MODE_MASK;
ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
break;
case pll_rk3588:
pll->mode_mask = PLL_MODE_MASK;
ret = rk3588_pll_set_rate(pll, base, pll_id, drate);
break;
default:
printf("%s: Unknown pll type for pll clk %ld\n",
__func__, pll_id);

3
drivers/clk/rockchip/clk_rk3568.c
View file

@ -1442,6 +1442,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv,
switch (rate) {
case OSC_HZ:
case 26 * MHz:
case 25 * MHz:
src_clk = CLK_SDMMC_SEL_24M;
break;
case 400 * MHz:
@ -1631,6 +1632,8 @@ static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
switch (rate) {
case OSC_HZ:
case 26 * MHz:
case 25 * MHz:
src_clk = CCLK_EMMC_SEL_24M;
break;
case 52 * MHz:

1996
drivers/clk/rockchip/clk_rk3588.c Normal file
View file

File diff suppressed because it is too large Load diff

20
drivers/gpio/rk_gpio.c
View file

@ -142,6 +142,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
char *end;
int ret;
@ -150,9 +151,22 @@ static int rockchip_gpio_probe(struct udevice *dev)
if (ret)
return ret;
uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
end = strrchr(dev->name, '@');
priv->bank = trailing_strtoln(dev->name, end);
/*
* If "gpio-ranges" is present in the devicetree use it to parse
* the GPIO bank ID, otherwise use the legacy method.
*/
ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
"gpio-ranges", NULL, 3,
0, &args);
if (!ret || ret != -ENOENT) {
uc_priv->gpio_count = args.args[2];
priv->bank = args.args[1] / args.args[2];
} else {
uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
end = strrchr(dev->name, '@');
priv->bank = trailing_strtoln(dev->name, end);
}
priv->name[0] = 'A' + priv->bank;
uc_priv->bank_name = priv->name;

4
drivers/misc/Kconfig
View file

@ -92,10 +92,6 @@ config ROCKCHIP_EFUSE
or through child-nodes that are generated based on the e-fuse map
retrieved from the DTS.
This driver currently supports the RK3399 only, but can easily be
extended (by porting the read function from the Linux kernel sources)
to support other recent Rockchip devices.
config ROCKCHIP_OTP
bool "Rockchip OTP Support"
depends on MISC

333
drivers/misc/rockchip-efuse.c
View file

@ -13,50 +13,57 @@
#include <dm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <malloc.h>
#include <misc.h>
#define RK3399_A_SHIFT 16
#define RK3399_A_MASK 0x3ff
#define RK3399_NFUSES 32
#define RK3399_BYTES_PER_FUSE 4
#define RK3399_STROBSFTSEL BIT(9)
#define RK3399_RSB BIT(7)
#define RK3399_PD BIT(5)
#define RK3399_PGENB BIT(3)
#define RK3399_LOAD BIT(2)
#define RK3399_STROBE BIT(1)
#define RK3399_CSB BIT(0)
struct rockchip_efuse_regs {
u32 ctrl; /* 0x00 efuse control register */
u32 dout; /* 0x04 efuse data out register */
u32 rf; /* 0x08 efuse redundancy bit used register */
u32 _rsvd0;
u32 jtag_pass; /* 0x10 JTAG password */
u32 strobe_finish_ctrl;
/* 0x14 efuse strobe finish control register */
};
#define EFUSE_CTRL 0x0000
#define RK3036_A_SHIFT 8
#define RK3036_A_MASK GENMASK(15, 8)
#define RK3036_ADDR(n) ((n) << RK3036_A_SHIFT)
#define RK3128_A_SHIFT 7
#define RK3128_A_MASK GENMASK(15, 7)
#define RK3128_ADDR(n) ((n) << RK3128_A_SHIFT)
#define RK3288_A_SHIFT 6
#define RK3288_A_MASK GENMASK(15, 6)
#define RK3288_ADDR(n) ((n) << RK3288_A_SHIFT)
#define RK3399_A_SHIFT 16
#define RK3399_A_MASK GENMASK(25, 16)
#define RK3399_ADDR(n) ((n) << RK3399_A_SHIFT)
#define RK3399_STROBSFTSEL BIT(9)
#define RK3399_RSB BIT(7)
#define RK3399_PD BIT(5)
#define EFUSE_PGENB BIT(3)
#define EFUSE_LOAD BIT(2)
#define EFUSE_STROBE BIT(1)
#define EFUSE_CSB BIT(0)
#define EFUSE_DOUT 0x0004
#define RK3328_INT_STATUS 0x0018
#define RK3328_INT_FINISH BIT(0)
#define RK3328_DOUT 0x0020
#define RK3328_AUTO_CTRL 0x0024
#define RK3328_AUTO_RD BIT(1)
#define RK3328_AUTO_ENB BIT(0)
struct rockchip_efuse_plat {
void __iomem *base;
struct clk *clk;
};
struct rockchip_efuse_data {
int (*read)(struct udevice *dev, int offset, void *buf, int size);
int offset;
int size;
int block_size;
};
#if defined(DEBUG)
static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
static int dump_efuse(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
/*
* N.B.: This function is tailored towards the RK3399 and assumes that
* there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to
* be read.
*/
struct udevice *dev;
u8 fuses[128];
int ret;
u8 data[4];
int ret, i;
/* retrieve the device */
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(rockchip_efuse), &dev);
if (ret) {
@ -64,65 +71,152 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
return 0;
}
ret = misc_read(dev, 0, &fuses, sizeof(fuses));
if (ret < 0) {
printf("%s: misc_read failed\n", __func__);
return 0;
}
for (i = 0; true; i += sizeof(data)) {
ret = misc_read(dev, i, &data, sizeof(data));
if (ret < 0)
return 0;
printf("efuse-contents:\n");
print_buffer(0, fuses, 1, 128, 16);
print_buffer(i, data, 1, sizeof(data), sizeof(data));
}
return 0;
}
U_BOOT_CMD(
rk3399_dump_efuses, 1, 1, dump_efuses,
"Dump the content of the efuses",
dump_efuse, 1, 1, dump_efuse,
"Dump the content of the efuse",
""
);
#endif
static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
static int rockchip_rk3036_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_efuse_plat *plat = dev_get_plat(dev);
struct rockchip_efuse_regs *efuse =
(struct rockchip_efuse_regs *)plat->base;
struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
u8 *buffer = buf;
unsigned int addr_start, addr_end, addr_offset;
u32 out_value;
u8 bytes[RK3399_NFUSES * RK3399_BYTES_PER_FUSE];
int i = 0;
u32 addr;
/* Switch to read mode */
writel(EFUSE_LOAD, efuse->base + EFUSE_CTRL);
udelay(2);
addr_start = offset / RK3399_BYTES_PER_FUSE;
addr_offset = offset % RK3399_BYTES_PER_FUSE;
addr_end = DIV_ROUND_UP(offset + size, RK3399_BYTES_PER_FUSE);
while (size--) {
clrsetbits_le32(efuse->base + EFUSE_CTRL, RK3036_A_MASK,
RK3036_ADDR(offset++));
udelay(2);
setbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(2);
*buffer++ = (u8)(readl(efuse->base + EFUSE_DOUT) & 0xFF);
clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(2);
}
/* cap to the size of the efuse block */
if (addr_end > RK3399_NFUSES)
addr_end = RK3399_NFUSES;
/* Switch to inactive mode */
writel(0x0, efuse->base + EFUSE_CTRL);
writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
&efuse->ctrl);
udelay(1);
for (addr = addr_start; addr < addr_end; addr++) {
setbits_le32(&efuse->ctrl,
RK3399_STROBE | (addr << RK3399_A_SHIFT));
udelay(1);
out_value = readl(&efuse->dout);
clrbits_le32(&efuse->ctrl, RK3399_STROBE);
udelay(1);
return 0;
}
memcpy(&bytes[i], &out_value, RK3399_BYTES_PER_FUSE);
i += RK3399_BYTES_PER_FUSE;
static int rockchip_rk3128_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
u8 *buffer = buf;
/* Switch to read mode */
writel(EFUSE_LOAD, efuse->base + EFUSE_CTRL);
udelay(2);
while (size--) {
clrsetbits_le32(efuse->base + EFUSE_CTRL, RK3128_A_MASK,
RK3128_ADDR(offset++));
udelay(2);
setbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(2);
*buffer++ = (u8)(readl(efuse->base + EFUSE_DOUT) & 0xFF);
clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(2);
}
/* Switch to inactive mode */
writel(0x0, efuse->base + EFUSE_CTRL);
return 0;
}
static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
u8 *buffer = buf;
/* Switch to read mode */
writel(EFUSE_CSB, efuse->base + EFUSE_CTRL);
writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + EFUSE_CTRL);
udelay(2);
while (size--) {
clrsetbits_le32(efuse->base + EFUSE_CTRL, RK3288_A_MASK,
RK3288_ADDR(offset++));
udelay(2);
setbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(2);
*buffer++ = (u8)(readl(efuse->base + EFUSE_DOUT) & 0xFF);
clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(2);
}
/* Switch to standby mode */
writel(RK3399_PD | RK3399_CSB, &efuse->ctrl);
writel(EFUSE_CSB | EFUSE_PGENB, efuse->base + EFUSE_CTRL);
memcpy(buf, bytes + addr_offset, size);
return 0;
}
static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
u32 status, *buffer = buf;
int ret;
while (size--) {
writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | RK3399_ADDR(offset++),
efuse->base + RK3328_AUTO_CTRL);
udelay(1);
ret = readl_poll_sleep_timeout(efuse->base + RK3328_INT_STATUS,
status, (status & RK3328_INT_FINISH), 1, 50);
if (ret)
return ret;
*buffer++ = readl(efuse->base + RK3328_DOUT);
writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
}
return 0;
}
static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
u32 *buffer = buf;
/* Switch to array read mode */
writel(EFUSE_LOAD | EFUSE_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
efuse->base + EFUSE_CTRL);
udelay(1);
while (size--) {
setbits_le32(efuse->base + EFUSE_CTRL,
EFUSE_STROBE | RK3399_ADDR(offset++));
udelay(1);
*buffer++ = readl(efuse->base + EFUSE_DOUT);
clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
udelay(1);
}
/* Switch to power-down mode */
writel(RK3399_PD | EFUSE_CSB, efuse->base + EFUSE_CTRL);
return 0;
}
@ -130,7 +224,38 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
static int rockchip_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
return rockchip_rk3399_efuse_read(dev, offset, buf, size);
const struct rockchip_efuse_data *data =
(void *)dev_get_driver_data(dev);
u32 block_start, block_end, block_offset, blocks;
u8 *buffer;
int ret;
if (offset < 0 || !buf || size <= 0 || offset + size > data->size)
return -EINVAL;
if (!data->read)
return -ENOSYS;
offset += data->offset;
if (data->block_size <= 1)
return data->read(dev, offset, buf, size);
block_start = offset / data->block_size;
block_offset = offset % data->block_size;
block_end = DIV_ROUND_UP(offset + size, data->block_size);
blocks = block_end - block_start;
buffer = calloc(blocks, data->block_size);
if (!buffer)
return -ENOMEM;
ret = data->read(dev, block_start, buffer, blocks);
if (!ret)
memcpy(buf, buffer + block_offset, size);
free(buffer);
return ret;
}
static const struct misc_ops rockchip_efuse_ops = {
@ -142,11 +267,71 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev)
struct rockchip_efuse_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr_ptr(dev);
return 0;
}
static const struct rockchip_efuse_data rk3036_data = {
.read = rockchip_rk3036_efuse_read,
.size = 0x20,
};
static const struct rockchip_efuse_data rk3128_data = {
.read = rockchip_rk3128_efuse_read,
.size = 0x40,
};
static const struct rockchip_efuse_data rk3288_data = {
.read = rockchip_rk3288_efuse_read,
.size = 0x20,
};
static const struct rockchip_efuse_data rk3328_data = {
.read = rockchip_rk3328_efuse_read,
.offset = 0x60,
.size = 0x20,
.block_size = 4,
};
static const struct rockchip_efuse_data rk3399_data = {
.read = rockchip_rk3399_efuse_read,
.size = 0x80,
.block_size = 4,
};
static const struct udevice_id rockchip_efuse_ids[] = {
{ .compatible = "rockchip,rk3399-efuse" },
{
.compatible = "rockchip,rk3036-efuse",
.data = (ulong)&rk3036_data,
},
{
.compatible = "rockchip,rk3066a-efuse",
.data = (ulong)&rk3288_data,
},
{
.compatible = "rockchip,rk3128-efuse",
.data = (ulong)&rk3128_data,
},
{
.compatible = "rockchip,rk3188-efuse",
.data = (ulong)&rk3288_data,
},
{
.compatible = "rockchip,rk3228-efuse",
.data = (ulong)&rk3288_data,
},
{
.compatible = "rockchip,rk3288-efuse",
.data = (ulong)&rk3288_data,
},
{
.compatible = "rockchip,rk3328-efuse",
.data = (ulong)&rk3328_data,
},
{
.compatible = "rockchip,rk3399-efuse",
.data = (ulong)&rk3399_data,
},
{}
};
@ -155,6 +340,6 @@ U_BOOT_DRIVER(rockchip_efuse) = {
.id = UCLASS_MISC,
.of_match = rockchip_efuse_ids,
.of_to_plat = rockchip_efuse_of_to_plat,
.plat_auto = sizeof(struct rockchip_efuse_plat),
.plat_auto = sizeof(struct rockchip_efuse_plat),
.ops = &rockchip_efuse_ops,
};

234
drivers/misc/rockchip-otp.c
View file

@ -6,9 +6,12 @@
#include <common.h>
#include <asm/io.h>
#include <command.h>
#include <display_options.h>
#include <dm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <malloc.h>
#include <misc.h>
/* OTP Register Offsets */
@ -47,37 +50,80 @@
#define OTPC_TIMEOUT 10000
#define RK3588_OTPC_AUTO_CTRL 0x0004
#define RK3588_ADDR_SHIFT 16
#define RK3588_ADDR(n) ((n) << RK3588_ADDR_SHIFT)
#define RK3588_BURST_SHIFT 8
#define RK3588_BURST(n) ((n) << RK3588_BURST_SHIFT)
#define RK3588_OTPC_AUTO_EN 0x0008
#define RK3588_AUTO_EN BIT(0)
#define RK3588_OTPC_DOUT0 0x0020
#define RK3588_OTPC_INT_ST 0x0084
#define RK3588_RD_DONE BIT(1)
struct rockchip_otp_plat {
void __iomem *base;
unsigned long secure_conf_base;
unsigned long otp_mask_base;
};
static int rockchip_otp_wait_status(struct rockchip_otp_plat *otp,
u32 flag)
{
int delay = OTPC_TIMEOUT;
struct rockchip_otp_data {
int (*read)(struct udevice *dev, int offset, void *buf, int size);
int offset;
int size;
int block_size;
};
while (!(readl(otp->base + OTPC_INT_STATUS) & flag)) {
udelay(1);
delay--;
if (delay <= 0) {
printf("%s: wait init status timeout\n", __func__);
return -ETIMEDOUT;
}
#if defined(DEBUG)
static int dump_otp(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct udevice *dev;
u8 data[4];
int ret, i;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(rockchip_otp), &dev);
if (ret) {
printf("%s: no misc-device found\n", __func__);
return 0;
}
/* clean int status */
writel(flag, otp->base + OTPC_INT_STATUS);
for (i = 0; true; i += sizeof(data)) {
ret = misc_read(dev, i, &data, sizeof(data));
if (ret < 0)
return 0;
print_buffer(i, data, 1, sizeof(data), sizeof(data));
}
return 0;
}
static int rockchip_otp_ecc_enable(struct rockchip_otp_plat *otp,
bool enable)
{
int ret = 0;
U_BOOT_CMD(
dump_otp, 1, 1, dump_otp,
"Dump the content of the otp",
""
);
#endif
static int rockchip_otp_poll_timeout(struct rockchip_otp_plat *otp,
u32 flag, u32 reg)
{
u32 status;
int ret;
ret = readl_poll_sleep_timeout(otp->base + reg, status,
(status & flag), 1, OTPC_TIMEOUT);
if (ret)
return ret;
/* Clear int flag */
writel(flag, otp->base + reg);
return 0;
}
static int rockchip_otp_ecc_enable(struct rockchip_otp_plat *otp, bool enable)
{
writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
otp->base + OTPC_SBPI_CTRL);
@ -92,11 +138,7 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp_plat *otp,
writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE);
if (ret < 0)
printf("%s timeout during ecc_enable\n", __func__);
return ret;
return rockchip_otp_poll_timeout(otp, OTPC_SBPI_DONE, OTPC_INT_STATUS);
}
static int rockchip_px30_otp_read(struct udevice *dev, int offset,
@ -104,29 +146,27 @@ static int rockchip_px30_otp_read(struct udevice *dev, int offset,
{
struct rockchip_otp_plat *otp = dev_get_plat(dev);
u8 *buffer = buf;
int ret = 0;
int ret;
ret = rockchip_otp_ecc_enable(otp, false);
if (ret < 0) {
printf("%s rockchip_otp_ecc_enable err\n", __func__);
if (ret)
return ret;
}
writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
udelay(5);
while (size--) {
writel(offset++ | OTPC_USER_ADDR_MASK,
otp->base + OTPC_USER_ADDR);
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
otp->base + OTPC_USER_ENABLE);
ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE);
if (ret < 0) {
printf("%s timeout during read setup\n", __func__);
ret = rockchip_otp_poll_timeout(otp, OTPC_USER_DONE,
OTPC_INT_STATUS);
if (ret)
goto read_end;
}
*buffer++ = readb(otp->base + OTPC_USER_Q);
*buffer++ = (u8)(readl(otp->base + OTPC_USER_Q) & 0xFF);
}
read_end:
@ -135,10 +175,98 @@ read_end:
return ret;
}
static int rockchip_rk3568_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_otp_plat *otp = dev_get_plat(dev);
u16 *buffer = buf;
int ret;
ret = rockchip_otp_ecc_enable(otp, false);
if (ret)
return ret;
writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
udelay(5);
while (size--) {
writel(offset++ | OTPC_USER_ADDR_MASK,
otp->base + OTPC_USER_ADDR);
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
otp->base + OTPC_USER_ENABLE);
ret = rockchip_otp_poll_timeout(otp, OTPC_USER_DONE,
OTPC_INT_STATUS);
if (ret)
goto read_end;
*buffer++ = (u16)(readl(otp->base + OTPC_USER_Q) & 0xFFFF);
}
read_end:
writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
return ret;
}
static int rockchip_rk3588_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
struct rockchip_otp_plat *otp = dev_get_plat(dev);
u32 *buffer = buf;
int ret;
while (size--) {
writel(RK3588_ADDR(offset++) | RK3588_BURST(1),
otp->base + RK3588_OTPC_AUTO_CTRL);
writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
ret = rockchip_otp_poll_timeout(otp, RK3588_RD_DONE,
RK3588_OTPC_INT_ST);
if (ret)
return ret;
*buffer++ = readl(otp->base + RK3588_OTPC_DOUT0);
}
return 0;
}
static int rockchip_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
return rockchip_px30_otp_read(dev, offset, buf, size);
const struct rockchip_otp_data *data =
(void *)dev_get_driver_data(dev);
u32 block_start, block_end, block_offset, blocks;
u8 *buffer;
int ret;
if (offset < 0 || !buf || size <= 0 || offset + size > data->size)
return -EINVAL;
if (!data->read)
return -ENOSYS;
offset += data->offset;
if (data->block_size <= 1)
return data->read(dev, offset, buf, size);
block_start = offset / data->block_size;
block_offset = offset % data->block_size;
block_end = DIV_ROUND_UP(offset + size, data->block_size);
blocks = block_end - block_start;
buffer = calloc(blocks, data->block_size);
if (!buffer)
return -ENOMEM;
ret = data->read(dev, block_start, buffer, blocks);
if (!ret)
memcpy(buf, buffer + block_offset, size);
free(buffer);
return ret;
}
static const struct misc_ops rockchip_otp_ops = {
@ -147,21 +275,47 @@ static const struct misc_ops rockchip_otp_ops = {
static int rockchip_otp_of_to_plat(struct udevice *dev)
{
struct rockchip_otp_plat *otp = dev_get_plat(dev);
struct rockchip_otp_plat *plat = dev_get_plat(dev);
otp->base = dev_read_addr_ptr(dev);
plat->base = dev_read_addr_ptr(dev);
return 0;
}
static const struct rockchip_otp_data px30_data = {
.read = rockchip_px30_otp_read,
.size = 0x40,
};
static const struct rockchip_otp_data rk3568_data = {
.read = rockchip_rk3568_otp_read,
.size = 0x80,
.block_size = 2,
};
static const struct rockchip_otp_data rk3588_data = {
.read = rockchip_rk3588_otp_read,
.offset = 0xC00,
.size = 0x400,
.block_size = 4,
};
static const struct udevice_id rockchip_otp_ids[] = {
{
.compatible = "rockchip,px30-otp",
.data = (ulong)&rockchip_px30_otp_read,
.data = (ulong)&px30_data,
},
{
.compatible = "rockchip,rk3308-otp",
.data = (ulong)&rockchip_px30_otp_read,
.data = (ulong)&px30_data,
},
{
.compatible = "rockchip,rk3568-otp",
.data = (ulong)&rk3568_data,
},
{
.compatible = "rockchip,rk3588-otp",
.data = (ulong)&rk3588_data,
},
{}
};
@ -170,7 +324,7 @@ U_BOOT_DRIVER(rockchip_otp) = {
.name = "rockchip_otp",
.id = UCLASS_MISC,
.of_match = rockchip_otp_ids,
.ops = &rockchip_otp_ops,
.of_to_plat = rockchip_otp_of_to_plat,
.plat_auto = sizeof(struct rockchip_otp_plat),
.plat_auto = sizeof(struct rockchip_otp_plat),
.ops = &rockchip_otp_ops,
};

30
drivers/mmc/renesas-sdhi.c
View file

@ -977,34 +977,50 @@ static int renesas_sdhi_probe(struct udevice *dev)
/* optional SDnH clock */
ret = clk_get_by_name(dev, "clkh", &priv->clkh);
if (ret < 0)
if (ret < 0) {
dev_dbg(dev, "failed to get clkh\n");
} else {
ret = clk_set_rate(&priv->clkh, 800000000);
if (ret < 0) {
dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret);
goto err_clk;
}
}
/* set to max rate */
ret = clk_set_rate(&priv->clk, 200000000);
if (ret < 0) {
dev_err(dev, "failed to set rate for host clock\n");
clk_free(&priv->clk);
return ret;
dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret);
goto err_clkh;
}
ret = clk_enable(&priv->clk);
if (ret) {
dev_err(dev, "failed to enable host clock\n");
return ret;
dev_err(dev, "failed to enable SDn clock (%d)\n", ret);
goto err_clkh;
}
priv->quirks = quirks;
ret = tmio_sd_probe(dev, quirks);
if (ret)
goto err_tmio_probe;
renesas_sdhi_filter_caps(dev);
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
renesas_sdhi_reset_tuning(priv);
#endif
return 0;
err_tmio_probe:
clk_disable(&priv->clk);
err_clkh:
clk_free(&priv->clkh);
err_clk:
clk_free(&priv->clk);
return ret;
}

8
drivers/mmc/rockchip_dw_mmc.c
View file

@ -41,6 +41,14 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
int ret;
/*
* The clock frequency chosen here affects CLKDIV in the dw_mmc core.
* That can be either 0 or 1, but it must be set to 1 for eMMC DDR52
* 8-bit mode. It will be set to 0 for all other modes.
*/
if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
freq *= 2;
ret = clk_set_rate(&priv->clk, freq);
if (ret < 0) {
debug("%s: err=%d\n", __func__, ret);

7
drivers/phy/rockchip/Kconfig
View file

@ -11,6 +11,13 @@ config PHY_ROCKCHIP_INNO_USB2
help
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
config PHY_ROCKCHIP_NANENG_COMBOPHY
bool "Support Rockchip NANENG combo PHY Driver"
depends on ARCH_ROCKCHIP
select PHY
help
Enable this to support the Rockchip NANENG combo PHY.
config PHY_ROCKCHIP_PCIE
bool "Rockchip PCIe PHY Driver"
depends on ARCH_ROCKCHIP

1
drivers/phy/rockchip/Makefile
View file

@ -4,6 +4,7 @@
#
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o

65
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
View file

@ -179,12 +179,21 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
if (IS_ERR(priv->reg_base))
return PTR_ERR(priv->reg_base);
ret = ofnode_read_u32(dev_ofnode(dev), "reg", &reg);
ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &reg);
if (ret) {
dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
return ret;
}
/* support address_cells=2 */
if (reg == 0) {
if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg)) {
dev_err(dev, "%s must have reg[1]\n",
ofnode_get_name(dev_ofnode(dev)));
return -EINVAL;
}
}
phy_cfgs = (const struct rockchip_usb2phy_cfg *)
dev_get_driver_data(dev);
if (!phy_cfgs)
@ -289,11 +298,65 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{
.reg = 0xfe8a0000,
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 },
.bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
.bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
.utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
.utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
.utmi_ls = { 0x00c0, 5, 4, 0, 1 },
},
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
.ls_det_en = { 0x0080, 1, 1, 0, 1 },
.ls_det_st = { 0x0084, 1, 1, 0, 1 },
.ls_det_clr = { 0x0088, 1, 1, 0, 1 },
.utmi_ls = { 0x00c0, 17, 16, 0, 1 },
.utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
}
},
},
{
.reg = 0xfe8b0000,
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
.utmi_ls = { 0x00c0, 5, 4, 0, 1 },
.utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
},
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
.ls_det_en = { 0x0080, 1, 1, 0, 1 },
.ls_det_st = { 0x0084, 1, 1, 0, 1 },
.ls_det_clr = { 0x0088, 1, 1, 0, 1 },
.utmi_ls = { 0x00c0, 17, 16, 0, 1 },
.utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
}
},
},
{ /* sentinel */ }
};
static const struct udevice_id rockchip_usb2phy_ids[] = {
{
.compatible = "rockchip,rk3399-usb2phy",
.data = (ulong)&rk3399_usb2phy_cfgs,
},
{
.compatible = "rockchip,rk3568-usb2phy",
.data = (ulong)&rk3568_phy_cfgs,
},
{ /* sentinel */ }
};

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