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board: mntre: imx8mq: Add MNT Reform 2 board support

Browse source 
The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Patrick Wildt 2023-02-06 00:48:26 +01:00 committed by Stefano Babic
parent 50f64026f7
commit ebe2e0c309
11 changed files with 1766 additions and 0 deletions
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11
arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mq-u-boot.dtsi"
&pinctrl_uart1 {
bootph-pre-ram;
};
&uart1 { /* console */
bootph-pre-ram;
};

7
arch/arm/mach-imx/imx8m/Kconfig
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@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MQ_REFORM2
bool "imx8mq_reform2"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
select BINMAN
@ -362,6 +368,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/menlo/mx8menlo/Kconfig"
source "board/msc/sm2s_imx8mp/Kconfig"
source "board/mntre/imx8mq_reform2/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/purism/librem5/Kconfig"

15
board/mntre/imx8mq_reform2/Kconfig Normal file
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if TARGET_IMX8MQ_REFORM2
config SYS_BOARD
default "imx8mq_reform2"
config SYS_VENDOR
default "mntre"
config SYS_CONFIG_NAME
default "imx8mq_reform2"
config IMX_CONFIG
default "arch/arm/mach-imx/imx8m/imximage.cfg"
endif

7
board/mntre/imx8mq_reform2/MAINTAINERS Normal file
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REFORM2 IMX8MQ BOARD
M: Lukas F. Hartmann <lukas@mntre.com>
M: Patrick Wildt <patrick@blueri.se>
S: Maintained
F: board/mntre/imx8mq_reform2/
F: include/configs/imx8mq_reform2.h
F: configs/imx8mq_reform2_defconfig

12
board/mntre/imx8mq_reform2/Makefile Normal file
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#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mq_reform2.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

171
board/mntre/imx8mq_reform2/imx8mq_reform2.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <spl.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <power/pmic.h>
DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
return 0;
}
#ifdef CONFIG_FEC_MXC
#define PHY_RESET IMX_GPIO_NR(1, 9)
#define PHY_RX_CTL IMX_GPIO_NR(1, 24)
#define PHY_RXC IMX_GPIO_NR(1, 25)
#define PHY_RD0 IMX_GPIO_NR(1, 26)
#define PHY_RD1 IMX_GPIO_NR(1, 27)
#define PHY_RD2 IMX_GPIO_NR(1, 28)
#define PHY_RD3 IMX_GPIO_NR(1, 29)
#define STRAP_AR8035 (0x28) // 0010 1000
static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
/* 1.8V(1)/1.5V select(0) */
IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
};
static const iomux_v3_cfg_t enet_ar8035_pads[] = {
IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
};
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Pull PHY into reset */
gpio_request(PHY_RESET, "fec_rst");
gpio_direction_output(PHY_RESET, 0);
/* Configure ethernet pins value as GPIOs */
gpio_request(PHY_RD0, "fec_rd0");
gpio_direction_output(PHY_RD0, 0);
gpio_request(PHY_RD1, "fec_rd1");
gpio_direction_output(PHY_RD1, 0);
gpio_request(PHY_RD2, "fec_rd2");
gpio_direction_output(PHY_RD2, 0);
gpio_request(PHY_RD3, "fec_rd3");
gpio_direction_output(PHY_RD3, 1);
gpio_request(PHY_RX_CTL, "fec_rx_ctl");
gpio_direction_output(PHY_RX_CTL, 0);
gpio_request(PHY_RXC, "fec_rxc");
gpio_direction_output(PHY_RXC, 1);
/* Set ethernet pins to GPIO to bootstrap PHY */
imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
ARRAY_SIZE(enet_ar8035_gpio_pads));
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(22));
set_clk_enet(ENET_125MHZ);
/* 1 ms minimum reset pulse for ar8035 */
mdelay(1);
/* Release PHY from reset */
gpio_set_value(PHY_RESET, 1);
/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
udelay(12);
/* Change ethernet pins back to normal function */
imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
ARRAY_SIZE(enet_ar8035_pads));
}
#endif
#define USB1_HUB_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define USB1_HUB_RESET IMX_GPIO_NR(1, 14)
static void setup_usb(void)
{
imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
gpio_request(USB1_HUB_RESET, "usb1_rst");
gpio_direction_output(USB1_HUB_RESET, 0);
mdelay(10);
gpio_set_value(USB1_HUB_RESET, 1);
}
int board_init(void)
{
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
setup_usb();
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
init_usb_clk();
#endif
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "Reform2");
env_set("board_rev", "iMX8MQ");
#endif
return 0;
}

1014
board/mntre/imx8mq_reform2/lpddr4_timing.c Normal file
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95
board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h Normal file
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/*
* Copyright Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
/* MNT Reform2 */
#define CFG_DDR_MB 4096
#define CFG_DDR_RANK_BITS 1
#define CFG_DDR_CHANNEL_CNT 2
#ifdef WR_POST_EXT_3200
#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008)
#else
#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 8)
#endif
#if CFG_DDR_MB == 1024
/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
#define CH2_VAL_DDRC_ADDRMAP6_R0 0x0F070707
#elif CFG_DDR_MB == 2048
/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
#define CH2_VAL_DDRC_ADDRMAP6_R0 0x07070707
/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000016
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x0F070707
#elif CFG_DDR_MB == 3072
/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000015
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x48080707
#elif CFG_DDR_MB == 4096
/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000017
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707
#else
#error unsupported memory size
#endif
#define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */
#define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */
#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
#define CH2_LPDDR4_CS LPDDR4_CS_R0
#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R0
#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R0
#else
#error unsupported memory rank/size
#endif
/*
* rank0 will succeed, even if really rank 1, so we need
* to probe memory if rank0 succeeds
*/
#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R1
#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R1
#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R1
#endif
#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
#define CH2_LPDDR4_CS LPDDR4_CS_R1
#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R1
#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R1
#else
#error unsupported memory rank/size
#endif
#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R0
#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R0
#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R0
#endif
#else
#error unsupported rank bits
#endif
#if (CFG_DDR_CHANNEL_CNT == 2)
#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
#error unsupported options
#endif
#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#error unsupported options
#endif
#endif

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board/mntre/imx8mq_reform2/spl.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
extern struct dram_timing_info dram_timing_ch2;
static void spl_dram_init(void)
{
ddr_init(&dram_timing_ch2);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#define USDHC2_VSEL IMX_GPIO_NR(1, 8)
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
return 1;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_VSEL, "usdhc2_vsel");
gpio_direction_output(USDHC2_VSEL, 0);
break;
default:
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
#define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
#define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
#define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
#define I2C_MUX_ADDR 0x70
#define I2C_FAN53555_ADDR 0x60
static iomux_v3_cfg_t const power_pads[] = {
IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
};
int power_init_board(void)
{
uint8_t val;
imx_iomux_v3_setup_multiple_pads(power_pads,
ARRAY_SIZE(usdhc2_pads));
/* Release I2C multiplexer reset */
gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
gpio_direction_output(I2C1_PCA9546_RESET, 1);
/* Select VSEL0 on voltage regulators */
gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
gpio_direction_output(ARM_DRAM_VSEL, 0);
gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
gpio_direction_output(DRAM_1P1_VSEL, 0);
gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
/* Set mux to target ARM/DRAM regulator */
i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
/* .6 + .40 = 1.00 */
val = 0x80 + 40;
i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
/* Set mux to target DRAM regulator */
i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
/* .6 + .50 = 1.10 */
val = 0x80 + 50;
i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
/* Set mux to target SoC/GPU/VPU regulator */
i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
/* .6 + .30 = .90 */
val = 0x80 + 30;
i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
/* Set mux to target peripherals */
i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
return 0;
}
void spl_board_init(void)
{
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

107
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CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_REFORM2=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x1f000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x180000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x187ff0
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=1050
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_MDIO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __IMX8M_REFORM2_H
#define __IMX8M_REFORM2_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#endif
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 4
#endif
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc0,115200\0" \
"fdt_addr_r=0x43000000\0" \
"ramdisk_addr_r=0x44000000\0" \
"boot_fdt=try\0" \
"fdtfile=imx8mq-mnt-reform2.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"stdin=serial,usbkbd\0"
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GiB DDR */
#define CFG_MXC_UART_BASE UART_BASE_ADDR(1)
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif