Commit graph

6251 commits

Author SHA1 Message Date
Hans de Goede
fc3a832576 sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.

The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).

For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.

This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
7582e39eb0 sun6i: dram: Do not try to initialize a second dram chan on A31s
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
10191ed098 sun6i: Add sunxi_get_ss_bonding_id() function
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
37781a1a7e sun6i: Make dram clk and zq value Kconfig options
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.

Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Tom Rini
5f88ed5cde Merge git://git.denx.de/u-boot-x86 2015-01-13 13:39:25 -05:00
James Doublesin
fc46bae2ae arm: am437x: Enable hardware leveling for EMIF
Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values.  Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.

Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13 11:53:39 -05:00
Bin Meng
cdcc17d73d x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:05 -08:00
Bin Meng
ade8127a79 x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Bin Meng
9d74f03460 x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
7698d36a10 x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
8cb20ccc34 x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
3ba6a0f4f6 x86: Allow a hardcoded TSC frequency provided by Kconfig
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.

Normally the bypass should be turned on in a simulation environment
like qemu.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
5c564b0d2f x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
b2439aecd3 x86: fsp: Drop get_hob_type() and get_hob_length()
These two are not worth having separate inline functions as they are
really simple, so drop them.

Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
cb3b2e62ca x86: Add an 'mtrr' command to list and adjust MTRRs
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:25:02 -08:00
Simon Glass
c72f74e278 x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.

For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
801d70ce02 x86: Disable CAR before relocation on platforms that need it
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
7b00896ade x86: ivybridge: Add a way to turn off the CAR
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
db55bd7dad x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
aaafcd6c3f x86: ivybridge: Request MTRRs for DRAM regions
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
9818a00eea x86: ivybridge: Set up an MTRR for the video frame buffer
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
aff2523f69 x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
3a5659f7cf x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
f4a6f0aed0 x86: Tidy up VESA mode numbers
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
818f602112 x86: Use cache, don't clear the display in video BIOS
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
d19ee5c27e x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is
not considered at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Simon Glass
6c911c4322 x86: Drop RAMTOP Kconfig
We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:58 -08:00
Simon Glass
bbd43d659c x86: Correct XIP_ROM_SIZE
This should default to the size of the ROM for faster execution before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Bin Meng
b21b208184 x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
1eb47efc49 x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Matthias Fuchs
5f1459dc0d ppc4xx: remove some CPCI405 variants
only keep CPCI4052

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
5f8f6294a7 ppc4xx: remove G2000 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
fc88a5bf79 ppc4xx: remove WUH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
807db88b62 ppc4xx: remove VOH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
d526330479 ppc4xx: remove PMC405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
dbe7bb0d21 ppc4xx: remove PCI405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
cc6e715f1b ppc4xx: remove OCRTC board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
e434d5d729 ppc4xx: remove HUB405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
843125daeb ppc4xx: remove HH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
7ac9d47a22 ppc4xx: remove DU440 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
bc114076dc ppc4xx: remove DU405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
9a4018e09a ppc4xx: remove DP405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
3705726010 ppc4xx: remove CPCIISER4 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
2404124c47 ppc4xx: remove CMS700 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
b5e7c84f72 ppc4xx: remove ASH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
61b57c4ab9 ppc4xx: remove AR405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
2b8a04e551 ppx4xx: remove APC405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:21 -05:00
Matthias Fuchs
cbdc662a2c m68k: remove TASREG board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
2015-01-13 09:37:21 -05:00
Bin Meng
949dbc12db x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
8f9052fd98 pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
fa5530b85d x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
4722c035cf x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
120c41695b x86: Clean up the board dts files
This commits cleans up the board dts files.

- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
  serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
  dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
  skeleton.dtsi

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
9ca5a0ca0e x86: Rename coreboot.dsti to serial.dtsi
The name of coreboot.dtsi is misleading, as it actually describes
the legacy serial port device node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
57706e4bd6 x86: Remove alex.dts in arch/x86/dts
No board is using alex.dts, so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Alexey Brodkin
4c8c485ad9 arc: introduce "mdbtrick" target
MetaWare debugger (MDB) is still used as a primary tool for interaction
with target via JTAG. Moreover some very advanced features are not yet
implemented in GDB for ARC (and not sure if they will be implemnted
sometime soon given complexity and rare need for those features for
common user).

So if we're talking about development process when U-Boot is loaded in
target memory not by low-level boot-loader but manually through JTAG
chances are high developer uses MDB for it.

But MDB doesn't support PIE (position-independent executable) - it will
refuse to even start - that means no chance to load elf contents on
target.
Then the only way to load U-Boot in MDB is to fake it by:
  1. Reset PIE flag in ELF header
     This is simpe - on attempt to open elf MDB checks header and if it
doesn't match its expectation refuces to use provided elf.
  2. Strip all debug information from elf
     If (1) is done then MDB will open elf but on parsing of elf's debug
info it will refuse to process due to debug info it cannot understand
(symbols with PIE relocation).

Even though it could be done manually (I got it documented quite a while
ago here http://www.denx.de/wiki/U-Boot/ARCNotes) having this automated
way is very convenient. User may build U-Boot that will be loaded on
target via MDB saying "make mdbtrick".

Then if we now apply the manipulation MDB will happily start and will
load all required sections into the target.

Indeed there will be no source-level debug info available. But still MDB
will do its work on showing disassembly, global symbols, registers,
accessing low-level debug facilities etc.

As a summary - this is a pretty dirty hack but it simplifies life a lot
for us ARc developers.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-09 23:59:54 +03:00
Stefan Agner
75d7a0d7f1 arm: build arch memset/memcpy in Thumb2 mode
Resynchronize memcpy/memset with kernel 3.17 and build them in
Thumb2 mode (unified syntax). Those assembler files can be built
and linked in ARM mode too, however when calling them from Thumb2
built code, the stack got corrupted and the copy did not succeed
(the exact details have not been traced back). However, the Linux
kernel builds those files in Thumb2 mode. Hence U-Boot should
build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set.

To build the files without warning, some assembler instructions
had to be replaced with their UAL compliant variant (thanks
Jeroen for this input).

To build the file in Thumb2 mode the implicit-it=always option need
to be set to generate Thumb2 compliant IT instructions where needed.
We add this option to the general AFLAGS when building for Thumb2.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-01-09 10:20:22 -05:00
Tom Rini
f10d86d3ff Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-08 13:50:38 -05:00
Fabio Estevam
906d6fe303 mx25: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b ("arm: relocate the exception vectors") mx25pdk
hangs like this:

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
(hangs)

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx25 to boot again.

Acked-By: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-01-08 13:50:17 -05:00
Fabio Estevam
8ed5e4ce0b mx25: Remove empty line after printing the reset cause
Currently there is an unneeded empty line after printing the reset cause:

U-Boot 2015.01-rc4-00080-g0551a93 (Jan 06 2015 - 13:04:19)

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: POR

Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
MMC:   FSL_SDHC: 0

Remove the extra "\n" when printing the reset cause.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-01-08 11:00:45 -05:00
Masahiro Yamada
b4ad44baab ARM: UniPhier: add UART initialization routine for low-level debug
The low-level debugging functions are useful to debug the early boot
stage where the full UART driver is not available.

UniPhier SoCs need to initialize the UART port 0 to use this feature.
The initialization routine is called at the very entry of the
lowlevel_init().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-08 23:01:56 +09:00
Masahiro Yamada
2661dfd004 ARM: UniPhier: enable output of system bus
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-08 23:01:45 +09:00
Masahiro Yamada
5e165b258f ARM: UniPhier: fix SRAM size on support card
The max size of available memories on slot0 and slot1 is 32MB because
 - EA[25] signal is not output on the save-pin mode which is
   used PH1-LD4 or later SoCs.
 - EA[25] signal is not connected by the limitation (or bug?) of
   the PLD logic of DCC support card.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-08 23:01:21 +09:00
Marek Vasut
653cda8f66 dt: socfpga: Replace num-chipselect with num-cs
This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:13:30 +05:30
Marek Vasut
7411486253 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 16:02:58 +05:30
Tom Rini
fc078895d8 Merge branch 'misc' of git://git.denx.de/u-boot-x86 2015-01-05 20:00:25 -05:00
Sjoerd Simons
9332274989 cros-ec-keyboard: Synchronize DT binding from linux
The ChromeOS EC keyboard is used by various different chromebooks. Peach
pi being the third board in the u-boot tree to use it (snow and peach
pit the other two). Rather then embedding the same big DT node in the
peach-pi DT again, copy the dtsi snippit & bindings documentation from
linux and include it in all 3 boards.

This slightly changes the dt bindings in u-boot:
  * google,key-rows becomes keypad,num-rows
  * google,key-colums becomes keypad,num-colums
  * google,repeat-delay-ms and google,repeat-rate-ms are no longer used
    and replaced by hardcoded values (similar to tegra kbc)

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:16 -07:00
Karicheri, Muralidharan
58927a964e keystone: set default pci mode to root complex
pci ports are used as root complex in Linux. So set this as default
in u-boot for keystone devices

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
2015-01-05 15:13:47 -05:00
Dmitry Lifshitz
87791adc22 arm: omap: reset sata on boot
On OMAP platforms (like OMAP5) Linux kernel fails to detect a SATA
device if it is used by U-Boot.

It happens because U-Boot does not reset SATA controller before boot.

Reset the controller on OS boot so that Linux will have a clean state
to work with.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-05 15:13:47 -05:00
Dmitry Lifshitz
8decf5d4a5 OMAP5+: sata/scsi: implement scsi_bus_reset()
Implement missing scsi_bus_reset() for SCSI subsystem commands
on OMAP platforms.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-05 15:13:46 -05:00
Nishanth Menon
25098144ac Revert "ARM: omap4: Update sdram setting for panda rev A6"
This reverts commit 47a4bea6af.

Signed-off-by: Nishanth Menon <nm@ti.com>
2015-01-05 15:13:45 -05:00
Nishanth Menon
38e5a5abda ARM: OMAP4: Panda: rework DMM logic
Part of DMM logic is reuse from commit
47a4bea6af ("ARM: omap4: Update sdram
setting for panda rev A6") Which broke SDP4430 with ES2.3 (uses old
DDR).

So, to maintain support for newer DDR used in Panda ES rev B3, we
should, in addition to the commit
675cc77a3a ("ARM:OMAP4+: panda-es: Support
Rev B3 Elpida DDR2 RAM"), DDR timings, also do DMM configuration
specific to Panda.

Signed-off-by: Nishanth Menon <nm@ti.com>
2015-01-05 15:13:45 -05:00
Tom Rini
b31079282e omap-common/hwinit-common.c: timer_init() doesn't need to touch gd
The gd will be cleared at first so we don't need to set arch.tbl to 0.
In addition, the checks later against lastinc also work fine with an
initial value of 0 here.  This also brings us in line with sunxi code
for example.

Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-05 15:13:45 -05:00
Tom Rini
b352dde1ea am33xx: Drop timer_init call from s_init
In both SPL and non-SPL cases we will make a call to timer_init() early
on and do not need to call it again within s_init().

Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-05 15:13:45 -05:00
Tom Rini
57b5e43e95 socfpga: Drop redundant save_boot_params
The save_boot_params function here is the same as the default weak one
from arch/arm/cpu/armv7/start.S, drop.

Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-01-05 15:13:44 -05:00
Ian Campbell
97a8196451 ARM: bootm: do not add PSCI to fdt when booting in secure mode.
Commit 8bc347e2ec "ARM: bootm: Allow booting in secure mode on hyp capable
systems" added the capability to select nonsec vs sec mode boot via an
environment var.

There is a subtle gotcha with this functionality, which is that the PSCI nodes
are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting
in secure mode. Which means that if the kernel is PSCI aware then it will fail
to boot because it will try and do PSCI from secure world, which won't work.

This likely didn't get noticed before because the original purpose was to
support booting the legacy linux-sunxi kernels which don't understand PSCI.

To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and
use from the virt-dt code.

As well as avoiding the creation of the PSCI nodes we should also avoid
reserving the secure RAM, so do so.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2015-01-05 15:02:03 -05:00
Masahiro Yamada
d622ac3927 powerpc: mpc824x: remove MPC824X cpu support
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>
2015-01-05 12:08:55 -05:00
Masahiro Yamada
9067b30008 mpc8260: remove atc board support
These boards are still non-generic boards.

drivers/rtc/ds12887.c should also be removed because it can not
be built without CONFIG_ATC.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:55 -05:00
Masahiro Yamada
f7e1af8690 mpc8260: remove CPU86, CPU87 board support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:55 -05:00
Masahiro Yamada
e2b1962977 mpc8260: remove ep82xxm board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-05 12:08:55 -05:00
Masahiro Yamada
8eecbaf303 mpc8260: remove gw8260 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Oliver Brown <obrown@adventnetworks.com>
2015-01-05 12:08:54 -05:00
Masahiro Yamada
87882f5727 mpc8260: remove IPHASE4539 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Grandegger <wg@denx.de>
2015-01-05 12:08:54 -05:00
Masahiro Yamada
d2fd1d6623 mpc8260: remove muas3001 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
2015-01-05 12:08:54 -05:00
Masahiro Yamada
dc0b2fb4a7 mpc8260: remove PM825, PM826, PM828 board support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:54 -05:00
Masahiro Yamada
b3a2bbe1a4 mpc8260: remove MPC8266ADS board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rune Torgersen <runet@innovsys.com>
2015-01-05 12:08:54 -05:00
Masahiro Yamada
cc90905f78 mpc8260: remove VoVPN-GW board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-05 12:08:54 -05:00
Masahiro Yamada
4ad015bab0 mpc8260: remove ep8260 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Frank Panno <fpanno@delphintech.com>
2015-01-05 12:08:53 -05:00
Masahiro Yamada
793116d2c5 mpc8260: remove ppmc8260 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Brad Kemp <Brad.Kemp@seranoa.com>
2015-01-05 12:08:53 -05:00
Masahiro Yamada
b35c0ad6e6 mpc8260: remove sacsng board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
2015-01-05 12:08:53 -05:00
Masahiro Yamada
d19f6a60ec powerpc: remove cogent_8xx, cogent_mpc8260 board support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
2015-01-05 12:08:53 -05:00
Masahiro Yamada
af0e35149b mpc8xx: remove ESTEEM192E board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Conn Clark <clark@esteem.com>
2015-01-05 12:08:53 -05:00
Masahiro Yamada
5ec71100dc mpc8xx: remove IP860 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:53 -05:00
Masahiro Yamada
ca620cd149 mpc8xx: remove IVMS8, IVML24 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
acc2372db0 mpc8xx: remove lwmon board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
f017cd7f71 mpc8xx: remove NETVIA board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Pantelis Antoniou <panto@intracom.gr>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
79cbecb81b mpc8xx: remove R360MPI board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
8737fc7529 mpc8xx: remove RRvision board support
This board is still a non-generic board.

Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted
because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177,
CONFIG_VIDEO_ENCODER_AD7179 are not defined any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:52 -05:00
Masahiro Yamada
72ba368f45 mpc8xx: remove SPD823TS board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
4317d070db mpc8xx: remove KUP4X, KUP4K board support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Klaus Heydeck <heydeck@kieback-peter.de>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
3c5b20f1b7 mpc8xx: remove ELPT860 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: The LEOX team <team@leox.org>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
ceaf499b50 powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
5d2a5ef712 mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:50 -05:00
Tom Rini
b4a0b4006f Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-02 07:42:58 -05:00
Tom Rini
a74a4a86a5 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-01-01 15:10:39 -05:00
Peng Fan
b93ab2ee75 arm:mx6sx add QSPI support
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Tom Rini
6d76e2aca8 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-30 16:42:23 -05:00
Tom Rini
5523cc2b8a Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-30 12:17:18 -05:00
Tom Rini
f23041a38a Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2014-12-30 09:11:56 -05:00
Tom Rini
87b27c7aa7 Merge branch 'master' of git://git.denx.de/u-boot-samsung 2014-12-30 09:11:42 -05:00
Marek Vasut
cd3c5896b6 imx: i2c: Zap unnecessary malloc() calls
The malloc() calls are unnecessary, just allocate the stuff on stack.
While at it, reorder the code a little, so that only one variable is
used for the text, use snprintf() instead of sprintf() and use %01d
as a formatting string to avoid any possible overflows.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2014-12-30 14:05:48 +01:00
Pierre Aubert
248802d401 imx SPL: enable boot from eMMC boot partitions.
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
2014-12-30 14:05:36 +01:00
Stefano Babic
4e0114d967 Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-12-30 13:04:38 +01:00
Masahiro Yamada
7b77c9ab6f ARM: UniPhier: display boot swap pin status by pinmon command
This information would be useful enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-30 17:45:40 +09:00
Masahiro Yamada
c67b2afd6b ARM: UniPhier: add dump command of DDR PHY parameters
This commit adds a dump command of DDR PHY parameters of UniPhier
SoC family.  It might not be used very often for the regular operation
but it would be useful when something goes wrong with DDR memories.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-30 17:45:37 +09:00
Masahiro Yamada
b614e16cc0 ARM: UniPhier: add DDR PHY training code
This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-30 17:45:25 +09:00
Steve Rae
4d013d8fa8 bcm281xx: add support for "USB OTG clock"
enable this clock with the following:
  clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
2014-12-29 16:31:23 -05:00
Stephen Warren
47705eff7a ARM: rpi: support model A+
Add a board rev entry for the new model A+, and augment the board
rev error handling code to be a bit more verbose.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-29 16:31:22 -05:00
Linus Walleij
9be5c661be arm: semihosting: get rid of forward declarations
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Linus Walleij
4e1ef15091 arm: semihosting: fix up compile bugs
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.

The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.

Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Suggested-by: Mark Hambleton <mark.hambleton@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Linus Walleij
50b5639430 arm: semihosting: staticize internal functions
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.

However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.

Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.

This gives us some freedom to rearrange the semihosting
code without affecting the external interface.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Joonyoung Shim
fb56435f50 arm: exynos: clock: support SPLL as mmc source clock for exynos5420
MMC of exynos5420 can select SPLL as source clock, so add to support
SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-24 10:56:24 +09:00
Sjoerd Simons
ce88a25cc2 odroid-XU3: Add entry for DTS EHCI GPIO
Add samsung,vbus-gpio information for the XU3. This allows the usage of
the EHCI controller on the XU3, which is connected to the SMSC LAN9514
chip (usb hub + network).

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:48:01 +09:00
Sjoerd Simons
a7b99204a0 exynos5420: fix compilation without parade video
Not all exynos 5420 based devices with an LCD also have a parade LVDS
bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
and CONFIG_VIDEO_PARADE is not.

As a side-effect move the parade functions from the exynos system header
file to its own file.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:38:27 +09:00
Sjoerd Simons
307e90e617 Exynos5800: The Peach-Pi board does not have a Parade video bridge
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
Pi. So drop it from  device-tree

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:38:22 +09:00
Hyungwon Hwang
6207604f9c Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:37:10 +09:00
Stefan Roese
d0e932de7c arm: socfpga: Change watchdog timeout
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.

Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-12-21 14:39:04 +01:00
Peng Fan
eb412d79e4 imx:mx6 fix return value of mxc_get_clock
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.

Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-19 10:43:04 +01:00
Bin Meng
255fd5caa5 x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
41702bac01 x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
aada6276c6 x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
adfe3b247a x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
8c5224c9f5 x86: Use consistent name XXX_ADDR for binary blob flash address
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
58f542de30 x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
240a79d95c x86: Enable the queensbay cpu directory build
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
b71eec3129 x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Simon Glass
0f61de8d9d x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:06 -07:00
Bin Meng
b2e02d2865 x86: Add basic support to queensbay platform and crownbay board
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
efbeeafe95 x86: Integrate Tunnel Creek processor microcode
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
b591ee3913 x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.

Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
cf29e3e303 x86: ivybridge: Update the microcode
There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
81f79ef792 x86: Move microcode updates into a separate directory
We might end up with a few of these, so put them in their own directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:05 -07:00
Thierry Reding
1dfdd9ba4e ARM: Implement non-cached memory support
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
6e2fca94ff ARM: tegra: Enable PCIe on Jetson TK1
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
9c46e6cb45 ARM: tegra: Add Tegra124 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra124 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
12e5f6acda ARM: tegra: Add GIC for Tegra124
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
affe026928 ARM: tegra: Enable PCIe on Beaver
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.

In addition the board has a mini-PCIe expansion slot.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
5a2c96a0e5 ARM: tegra: Enable PCIe on Cardhu
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
a1811bc5b9 ARM: tegra: Add Tegra30 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
cd99876120 ARM: tegra: Add GIC for Tegra30
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
7dd8738f08 ARM: tegra: Enable PCIe on TrimSlice
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
65d2465d5d ARM: tegra: Add Tegra20 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
b02f3e0c2d ARM: tegra: Enable XUSB pad controller on Jetson TK1
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
78e9f1c4f3 ARM: tegra: Add XUSB pad controller on Tegra124
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
79c7a90f6c ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
48510c089b ARM: tegra: Implement powergate support
Implement the powergate API that allows various power partitions to be
power up and down.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
59cb3bf4c6 ARM: tegra: Provide PCIEXCLK reset ID
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
a723074550 ARM: tegra: Implement tegra_plle_enable()
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Marcel Ziswiler
839e4f7c66 ARM: tegra: colibri_t30: comment style fix
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 12:47:11 -07:00
Masahiro Yamada
992e874885 ARM: UniPhier: select CONFIG_SPL
Now UniPhier platform is only supported with SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:27 +09:00
Masahiro Yamada
d4d45ead23 ARM: UniPhier: remove unnecessary ifdef conditional
init_page_table is only set on SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:12 +09:00
Masahiro Yamada
490f55c4a6 ARM: UniPhier: fix property names of aliases nodes of device trees
The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:01 +09:00
Tom Rini
e3bf81b1e8 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-12-16 15:20:02 -05:00
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Tudor Laurentiu
d4be1753c6 p5040ds: changed liodn offsets
Offsets were overlaping, causing pamu access violations in
hypervised scenarios.

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:34 -08:00
Jeffrey Ladouceur
3fa66db459 mpc85xx: inhibit qman and bman portals by default
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:07 -08:00
York Sun
0ccee4e627 powerpc/mpc85xx: Fix DDR TLB mapping leftover
Commit f29f804a93 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
CC: Scott Wood <scottwood@freescale.com>
2014-12-15 09:15:40 -08:00
Masahiro Yamada
e6126a5872 x86: move arch-specific asmlinkage to <asm/linkage.h>
Commit 65dd74a674 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.

Commit ed0a2fbf14 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)

The generic asmlinkage is defined in <linux/linkage.h>.  If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-15 07:22:53 -07:00
Bin Meng
ba7b38a529 x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:06 -07:00
Bin Meng
bceb9f0fc8 x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
95a5a47466 x86: Add post failure codes for bist and car
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
8e04d4c537 x86: queensbay: Adapt FSP support codes
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 22:32:05 -07:00
Bin Meng
752a0b085b x86: Initial import from Intel FSP release for Queensbay platform
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.

For more details, check http://www.intel.com/fsp.

Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 22:32:05 -07:00
Bin Meng
a2927e09bc x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
568868dda9 x86: Add Intel Crown Bay board dts file
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
2795573a8c x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
fe0c33a5ac x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
64542f4616 x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:03 -07:00
Tom Rini
a5a5882611 Merge git://git.denx.de/u-boot-dm 2014-12-11 20:47:34 -05:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Allen Martin
a6c7b46181 ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.

The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
2014-12-11 13:18:44 -07:00
Simon Glass
754204b5c2 tegra: dts: Sync tegra124.dtsi with linux kernel
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-12-11 13:18:44 -07:00
Simon Glass
6ee350bb93 dts: Bring in Chrome OS keyboard device tree definition
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Simon Glass
776f96f513 dm: i2c: dts: Add an I2C bus for sandbox
Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
6ec1b75358 dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Alison Wang
0de15707a7 kconfig: ls102xa: Change the prompt messages
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:41 -08:00
Xiubo Li
660673af4f ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:22 -08:00
Xiubo Li
e87f3b308c ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:12 -08:00
Xiubo Li
1a2826f6e0 ls102xa: changing a few targets' configurations.
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:03 -08:00
Xiubo Li
290e6e921f ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.

Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:53 -08:00
Xiubo Li
73a1cb27c0 ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.

This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:45 -08:00
Xiubo Li
b8e5c7f94a ARM: HYP/non-sec: add the pen address BE mode support.
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.

This patch adds BE mode support for smp pen address.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:30 -08:00
Nikhil Badola
a1c04e2785 drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:50 -08:00
Alison Wang
8ab967b6c6 arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:24 -08:00
Alison Wang
d612f0ab34 arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:14 -08:00
Alison Wang
86949c2b7c arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:39:22 -08:00
Alison Wang
50f0c66325 kconfig: ls1021a: add SUPPORT_SPL
Add SUPPORT_SPL feature for SD and NAND boot on
LS1021AQDS and LS1021ATWR.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:38:51 -08:00
Alison Wang
14d54dec1b arm: spl: Add I2C linker list in generic .lds
On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds to fix the issue about
using I2C in SPL.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:38:35 -08:00
Minghuan Lian
da419027af arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:56 -08:00
chenhui zhao
306fa01279 arm: ls102xa: clear EPU registers for deep sleep
After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:42 -08:00
Tang Yuantian
b699b01e5c arm: ls102xa: fixed a bus frequency setting error
The bus frequency in SOC node should be clock frequency of platform.
That is not true if it is devided by 2.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:09 -08:00
Tom Rini
9b416a9f4c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-10 09:07:25 -05:00
Tom Rini
d51aae6423 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2014-12-10 09:07:06 -05:00
Nobuhiro Iwamatsu
3183c2a0cb arm: rmobile: Add mmc.h for sh_mmcif of rmobile
R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver.
This adds arch-rmobile/mmc.h that defines mmcif_mmc_init().

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-10 14:32:11 +09:00
Vikas Manocha
2ce4eaf4c8 stv0991: enable ethernet support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2014-12-09 15:16:19 -05:00
Vikas Manocha
9fa32b1237 stv0991: Add basic stv0991 architecture support
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add arch/arm/cpu/armv7/Makefile hunk]
Signed-off-by: Tom Rini <trini@ti.com>
2014-12-09 15:16:01 -05:00
Tom Rini
272a1acf1e Merge git://git.denx.de/u-boot-mpc85xx 2014-12-08 16:35:07 -05:00
Tom Rini
98d2d5e8c4 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-12-08 16:35:06 -05:00
Tom Rini
0fffbd26d5 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2014-12-08 16:35:05 -05:00
Masahiro Yamada
7a3620b246 ARM: UniPhier: detect the number of flash banks at run-time
Some UniPhier boards are equipped with an expansion slot that
some optional SRAM/NOR-flash cards can be attached to.  So, run-time
detection of the number of flash banks would be more user-friendly.

Until this commit, UniPhier boards have achieved this by (ab)using
board_flash_wp_on() because the boot failed if flash_size got zero.
Fortunately, this problem was solved by commit 70879a9256 (flash:
do not fail even if flash_size is zero).

Now it is possible to throw away such a tricky workaround.  This
commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further
refactoring.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09 00:08:33 +09:00
Masahiro Yamada
dc7246e725 ARM: UniPhier: extend register area of init page table for PH1-sLD3
0x20000000-0x2fffffff: assigned to ARM mpcore (sLD3 only)
0xf0000000-0xffffffff: assigned to Denali NAND controller (sLD3 only)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09 00:08:33 +09:00
Masahiro Yamada
230ce30a51 ARM: UniPhier: add device tree sources for PH1-sLD3
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09 00:08:26 +09:00
Masahiro Yamada
f5fd7afcd5 ARM: UniPhier: add more device nodes to device tree
Add I2C controller and NAND controller devices.  Fix indentation too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09 00:05:46 +09:00
Masahiro Yamada
8b923a56dc blackfin: include <linux/compiler.h> rather than define __iomem
The macro __iomem is defined in include/linux/compiler.h.
Let's include it rather than double __iomem defines.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
2014-12-08 09:35:46 -05:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Daniel Schwierzeck
e19db555b4 Kbuild: introduce Makefile in arch/$ARCH/
Introduce a Makefile under arch/$ARCH/ and include it in the
top Makefile (similar to Linux kernel). This allows further
refactoringi like moving architecture-specific code out of global
makefiles, deprecating config variables (CPU, CPUDIR, SOC) or
deprecating arch/$ARCH/config.mk.

In contrary to Linux kernel, U-Boot defines the ARCH variable by
Kconfig, thus the arch Makefile can only included conditionally
after the top config.mk.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:45 -05:00
Masahiro Yamada
36da51ebac powerpc: mpc8xx: remove hermes board support
This board sprinkles #ifdef(CONFIG_HERMES) over various global files
such as include/common.h, common/board_r.c, common/cmd_bdinfo.c.
Let's zap such an ill-behaved board.

It has not been converted to generic board yet and mpc8xx is old
enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2014-12-08 09:35:43 -05:00
Stephen Warren
9316e14400 ARM: rpi: rename rpi_b to rpi
The U-Boot port runs on a variety of RPi models, not just the B. So,
rename the port to something slightly more generic.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:42 -05:00
Stephen Warren
6fe7845a98 ARM: rpi_b: detect board revision
Detect the board revision early during boot, and print the decoded
model name.

Eventually, this information can be used for tasks such as:
- Allowing/preventing USB device mode; some models have a USB device on-
  board so only host mode makes sense. Others connect the SoC directly
  to the USB connector, so device-mode might make sense.
- The on-board USB hub/Ethernet requires different GPIOs to enable it,
  although luckily the default appears to be fine so far.
- The compute module contains an on-board eMMC device, so we could store
  the environment there. Other models use an SD card and so don't support
  saving the environment (unless we store it in a file on the FAT boot
  partition...)

Set $fdtfile based on this information. At present, the mainline Linux
kernel doesn't contain a separate DTB for most models, but I hope that
will change soon.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:42 -05:00
Masahiro Yamada
f5d0b9b2c3 ARM: UniPhier: merge UniPhier config headers into a single file
Some configurations have been moved to Kconfig and the difference
among the config headers of UniPhier SoC variants is getting smaller
and smaller.  Now is a good time to merge them into a single file.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
3201455d6a ARM: UniPhier: move support card select to Kconfig
There are two kinds of expansion boards which are often used for
the UniPhier platform and they are only exclusively selectable.
It can be better described by the "choice" menu of Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
84b3584f21 ARM: UniPhier: move CONFIG_UNIPHIER_SMP to Kconfig
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
b115678bdf ARM: UniPhier: use boot_is_swapped() macro for readability
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 01:25:44 +09:00
Masahiro Yamada
9248a78f40 ARM: UniPhier: remove Denali NAND controller fixup code
This ugly work-around code is unnecessary since commit f09eb52b3f
(mtd: denali: set some registers after nand_scan_ident()).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-07 17:47:32 +09:00
Dinh Nguyen
b9b5cf0ea3 socfpga: correctly increment freeze_controller_base address
Correctly increment the base address of the freeze controller. And since
SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-12-06 13:53:57 +01:00
Dinh Nguyen
5d2f930de0 socfpga: add missing struct member fifo_triple_byte
socfpga_scan_manager structure was missing a data member.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-12-06 13:53:57 +01:00
Stefan Roese
481549f8c1 arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
c877eaa8a0 arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bits
As suggested by Pavel, lets combine the two calls into one.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
369164042e arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
ae79e2d298 arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
60896653d5 arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
881f6a448f arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi
This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
5bf1f1ed13 arm: socfpga: dts: Move to SPDX license identifiers
The socfpga dts files are copied from the Rocketboards.org repository.
In U-Boot we usually replace the full-blown license header text with
the SPDX license identifiers. Lets do this for these new dts files
as well.

I just forgot to do this while adding the DT support for socfpga.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
2014-12-06 13:51:54 +01:00
Tudor Laurentiu
8d3eaa9709 powerpc/mpc85xx: use correct dma compatible for several SoCs
Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
 T1023/4, T1040, T2080/1, T4240, B4860.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
5818643bf4 t1024qds: increase IO drive strength
Increase IO drive strength to fix FCS error on RGMII ports
on T1024QDS.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
cc19c25e27 net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
48c6f328f0 powerpc/t1024rdb: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.

T1024RDB board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - one 10Gbps XFI interface
- PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors.
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD
- eSPI: 64MB N25Q512 SPI flash.
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- USB: Two  Type-A USB2.0 ports with internal PHY
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC
- I2C: Four I2C controllers
- UART: Two UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
	   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
aba8004818 powerpc/t1024qds: Add T1024 QDS board support
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.

T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - Three 1G/2.5Gbps SGMII ports
  - Four 1Gbps QSGMII ports
  - one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
  - Chrontel CH7201 for HDMI connection.
  - TI DS90C387R for direct LCD connection.
  - Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
  - 32-bit RISC controller for flexible support of the communications peripherals
  - Serial DMA channel for receive and transmit on all serial channels
  - Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
	   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
f605079041 powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Priyanka Jain
2892ec5f43 powerpc/mpc85xx: Update LIODN entries for T1040
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shaohui Xie
b24f6d401c powerpc/b4860qds: add workaround for XFI
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.

A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shaveta Leekha
ffc1a87b91 85xx/b4860: Add alternate serdes protocols for B4860/B4420
Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:12 -08:00
Zhao Qiang
e7f533cd59 powerpc/mpc85xx: modify erratum A007186
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:09 -08:00
Prabhakar Kushwaha
31530e0b8a board/t104xrdb: Conditional workaround of errata A-008044
Workaround of Errata A-008044 was implemented without errata number and it is
enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0.

So put errata number and make it conditional.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:09 -08:00
Prabhakar Kushwaha
9f074e67f5 powerpc/mpc85xx:Put errata number for T104x NAND boot issue
When device is configured to load RCW from NAND flash IFC_A[16:31] are driven
low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using
IFC_A[16:31] lines are not accessible.

Workaround is already in-place.
Put the errata number to adhere errata handling framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:08 -08:00
York Sun
14109c7a6a mpc85xx/t2080: Fix parsing DDR ratio for new revision
T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio,
the same way as T4240 rev 2.0.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-12-05 08:06:08 -08:00
Shengzhou Liu
2519cb344e powerpc/t2080: add serdes2 protocol 0x2e
Add serdes2 protocol 0x2e.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:07 -08:00
Stefan Roese
e49631afa0 arm: am33xx: Handle NAND+I2C boot-device the same way as NAND
Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
Otherwise the SPL boot IF can't handle this device correctly.
Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
Draco leads to this boot-device passed to SPL from the BootROM.

With this change, Draco boots just fine into main U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
2014-12-04 21:28:31 -05:00
Nobuhiro Iwamatsu
d3a22419cf arm: rmobile: rcar: Add structure for infomation of module control register
The infomation of module control register for R-Car ARM SoC (r8a7790, r8a7791,
r8a7793 and r8a7794) are almost the same, they can be combined into one
structure. This provides structure that summarizes infomation of module control
register and default register values.
And this structure is the module control use of the kernel at boot time.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:05:57 +09:00
Nobuhiro Iwamatsu
c72dd8eab1 arm: rmobile: rcar: Add infomation of bits for module control register
This adds infomation of bits for module control register. This is used
to control modules on ARM R-Car SoCs.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:05:34 +09:00
Nobuhiro Iwamatsu
11d902c6a6 arm: rmobile: rcar: Add mstp_setclrbits and mstp_setclrbits_le32
This addes macro for set and clear bit control for module control register.
This is used when user want to disable the function of the devices
corresponding to register.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:05:12 +09:00
Nobuhiro Iwamatsu
44e1eebf86 arm: rmobile: rcar: Move control macro of mstp to arch-rmobile/rcar-mstp.h
Control macro of mstp is common in R-Car ARM SoC (r8a7790, r8a7791,
r8a7793 and r8a7794). This moves these to arch-rmobile/rcar-mstp.h

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:04:13 +09:00
Nobuhiro Iwamatsu
aaa717ebde arm: rmobile: rcar: Move module control register to header file of SoC
Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and
r8a7794) are same address. This moves these to header file of SoC.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:03:53 +09:00
Felipe Balbi
1e4ad74b87 beagle_x15: add board support for Beagle x15
BeagleBoard-X15 is the next generation Open Source
Hardware BeagleBoard based on TI's AM5728 SoC
featuring dual core 1.5GHZ A15 processor. The
platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60),
separate LCD port, video In port, 4GB eMMC, uSD,
Analog audio in/out, dual 1G Ethernet.

For more information, refer to:
http://www.elinux.org/Beagleboard:BeagleBoard-X15

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:39 -05:00
Felipe Balbi
d11ac4b56d arm: omap: add support for am57xx devices
just add a few ifdefs around because this
device is very similar to dra7xxx.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
56fe405516 arm: omap_common: expose tps659038 and dra7xx_dplls
expose those two definitions so they can be
used by another board which we're adding in upcoming
patches.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
eedd991611 arm: omap5: sdram: mark emif_get_ext_phy_ctrl_const_regs __weak
this will allow for boards to overwrite those
in case memory setup is different.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
29bc86ade9 arm: omap5: make hw_init_data weak
this way we can let boards overwrite based
on what they need.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Felipe Balbi
dbf02eca0b arm: omap-common: emif: allow to map memory without interleaving
If we want to have two sections, one on each EMIF, without
interleaving, current code wouldn't enable emif2. Fix that
problem.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:13 -05:00
Felipe Balbi
113d7e88cb arm: dra7xx: prcm: add missing registers
some boards might want to use USB1 for host,
without fiddling those registers it'll be
impossible.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:13 -05:00
Felipe Balbi
c27cd33b8c arm: omap5: tps659038: rename regulator defines
Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:13 -05:00
Tom Rini
97cdf64026 Merge branch 'sandbox' of git://git.denx.de/u-boot-x86 2014-12-04 09:24:05 -05:00
Tom Rini
f4e7e2d121 Merge git://git.denx.de/u-boot-x86 2014-12-01 15:24:07 -05:00
Stefan Agner
9e89a64fbd arm: vf610: improve evaluation of reset source
Improve the evaluation of the reset source. Bit description according
to latest reference manual rev. 7.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-12-01 10:20:22 +01:00
Stefan Roese
7731745c13 arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)
As checkpatch complaines about these camel-case defines, lets change
them to only use upper-case characters.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:20:20 +01:00
Soeren Moch
dd1c8f1b5f sata: fix reset_sata for dwc_ahsata
- fix crash when sata device is not initialized
- remove disable_sata_clock() since it is not clear which clock for which
  device should be disabled here
- call disable_sata_clock() for mx6 in preboot_os instead

Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-12-01 10:20:19 +01:00
Soeren Moch
f8bbd7f7b0 tbs2910: fix Kconfig
fix Kconfig for tbs2910 board to prevent crash on relocation

Signed-off-by: Soeren Moch <smoch@web.de>
2014-12-01 10:20:19 +01:00
Tom Rini
e17e998d7f Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2014-11-27 13:10:04 -05:00
Masahiro Yamada
b5e57fc786 ARM: UniPhier: enable Device Tree control
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
149c751dc7 usb: UniPhier: support OF configuration
If CONFIG_OF_CONTROL is defined, search device tree nodes that are
compatible with "panasonic,uniphier-ehci" and take the base address
from their "reg" property.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
625177d27e serial: UniPhier: support OF configuration
This commit implements the ofdata_to_platdata handler for the UniPhier
serial driver and adds serial device nodes to the device tree sources.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
509eb67802 ARM: UniPhier: add device tree sources
This commit adds basic device tree sources for UniPhier SoCs/boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:20:56 +09:00
Masahiro Yamada
630bf80ebb ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>.  Consequently, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not
support GPIO.

In the first place, GPIO has nothing to do with OF_CONTROL.
It is wrong that lib/fdtdec.c includes GPIO functions; it should
be split into two files, FDT-common things and GPIO things.
It is, however, a pretty big work to fix that correctly.

This is a compromised commit to add a dummy <asm/arch/gpio.h>
to support OF_CONTROL for UniPhier platform.  This dummy header
will be removed after FDT-GPIO stuff is fixed correctly.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-11-28 02:17:21 +09:00
Masahiro Yamada
4b4af643fa ARM: UniPhier: do not compile platform data when CONFIG_OF_CONTROL=y
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:17:03 +09:00
Tom Rini
38cd8c4253 Merge branch 'master' of git://git.denx.de/u-boot-mips 2014-11-27 10:49:38 -05:00
Daniel Schwierzeck
6cec63d59d MIPS: bootm: remove unused or redundant header files
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Daniel Schwierzeck
c9639421fd MIPS: bootm: add missing initramfs relocation
The initramfs is currently only relocated if the user calls
the bootm ramdisk subcommand. If bootm should be used without
subcommands, the arch-specific bootm code needs to implement
the relocation.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Daniel Schwierzeck
426f87045c MIPS: remove board.c
After all MIPS boards are switched to generic-board, the
MIPS specific board.c can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Daniel Schwierzeck
6d08e22aca MIPS: fix setup of initial stack frame
To get correct stack walking and backtrace functionality in gdb,
registers fp and ra should be initialized before calling board_init_f
or board_init_r. Thus allocating stack space and zeroing it as it is
currently done in board.c becomes obsolete.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Marek Vasut
b19157bf3f mtd: nand: s3c: Unify the register definition and naming
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
2014-11-26 23:21:43 -06:00
Simon Glass
f80a8bbee8 sandbox: Fix warnings in cpu.c and os.c
This fixes the following two problems:

cppcheck reports:
[arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err
[arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Denk <wd@denx.de>
2014-11-26 20:25:39 -07:00
Tom Rini
85bafb6da4 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-11-26 11:23:26 -05:00
Tom Rini
21008ad638 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
	drivers/mmc/fsl_esdhc.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-26 11:22:29 -05:00
Tom Rini
878cd63e02 Merge branch 'master' of http://git.denx.de/u-boot-samsung 2014-11-26 11:21:16 -05:00
Tom Rini
f2ffe7da7f Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2014-11-26 11:21:16 -05:00
Tom Rini
1fc4e6f486 Merge git://git.denx.de/u-boot-fdt 2014-11-26 11:21:14 -05:00
Simon Glass
f3e56fe369 x86: dts: Add video information to the device tree
This provides panel timing information needed by the video driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
0ca2426bea x86: Add support for running option ROMs natively
On x86 machines we can use an emulator to run option ROMS as with other
architectures. But with some additional effort (mostly due to the 16-bit
nature of option ROMs) we can run them natively. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:38:57 -07:00
Simon Glass
22465fc46c x86: Add vesa mode configuration options
Add Kconfig options to allow selection of a vesa mode on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:15 -07:00
Simon Glass
e34aef1de3 x86: Add GDT descriptors for option ROMs
Option ROMs require a few additional descriptors. Add these, and remove the
enum since we now have to access several descriptors from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
24774278c9 x86: ivybridge: Add northbridge init functions
Add init for the northbridge, another part of the platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
d1ef1132bb x86: Drop some msr functions that we don't support
These are not available in U-Boot as yet, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
0c9075e9ad x86: Add LAPIC setup code
Add code to set up the Local Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:11 -07:00
Simon Glass
b636dd1079 x86: Drop old CONFIG_INTEL_CORE_ARCH code
This is no-longer used, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:03 -07:00
Bin Meng
1dae2e0eb6 x86: Refactor interrupt_init()
Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
a549f7497b x86: Remove cpu_init_r() for x86
Since cpu_init_interrupts() was moved out of cpu_init_r(), it is
useless to keep cpu_init_r() for x86, thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
4372a9eca5 x86: Call cpu_init_interrupts() from interrupt_init()
Currently cpu_init_interrupts() is called from cpu_init_r() to
setup the interrupt and exception of the cpu core, but at that
time the i8259 has not been initialized to mask all the irqs
and remap the master i8259 interrupt vector base, so the whole
system is at risk of being interrupted, and if interrupted,
wrong interrupt/exception message is shown.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
18739e2ccc x86: Add Intel speedstep and turbo mode code
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
a6d4c45306 x86: ivybridge: Set up XHCI USB
Add init for XHCI so that high-speed USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
9baeca4b89 x86: ivybridge: Set up EHCI USB
Add init for EHCI so that USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
4896f4acc8 x86: dts: Add SATA settings for link
Add the requires settings to enable SATA on link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
3ac839352d x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
05efc3961c x86: dts: Add LPC settings for link
Add some settings required to set up the LPC correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
b021e05535 x86: dts: Move PCI peripherals into a pci node
These peripherals should not be at the top level, since they exist inside
the PCI bus. We don't have a full device tree node for pci yet, but we
should at least put it at the right level.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
72cd085aae x86: ivybridge: Add additional LPC init
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
8c74a57318 x86: ivybridge: Add PCH init
Add required init for the Intel Platform Controller Hub in ivybridge.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
3e0332c0b9 x86: Add a simple header file for ACPI
We don't use many features yet, so this only has a few declarations.
It will be expanded as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
4e7a6acac7 x86: ivybridge: Add support for BD82x6x PCH
Add basic setup for the PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
a0bd851ece x86: Set up edge triggering on interrupt 9
Add this additional init in case it is needed by the OS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:00 -07:00
Simon Glass
e94ea6f656 x86: pci: Add handlers before and after a PCI hose scan
Some boards will want to do some setup before and after a PCI hose
is scanned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:00 -07:00
Simon Glass
a2f5d091cc x86: Add ioapic.h header
Add definitions for the I/O Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:33:59 -07:00
Simon Glass
a6a957849a x86: Factor out common values in the link script
Define the reset base in config.mk so that it does not need to be calculated
twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values
to fit with this new approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
091c494353 x86: Ensure that all relocation data is included in the image
Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
512e581c86 x86: Panic if there is no relocation data
This normally indicates a problem which will prevent relocation from
functioning, resulting in a hang. Panic in this case to make it easier
to debug.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
65990d5680 x86: Remove board_early_init_r()
This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
2f6d42b9df x86: Add ivybridge directory to Makefile
It is now required to add subdirectories in the x86 cpu Makefile. Add this
to fix a build breakage for chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:33:56 -07:00
Hans de Goede
7b02d9c943 sun6i: Drop some "unknown magic" from dram init
Allwinner tells us that this bit of code is the rtc ram being used to detect
coming out of "super-standby" mode, and if that is the case, going out of
self-refresh mode.

Since we do not support "super-standby" mode, this can be dropped.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Hans de Goede
eafec32000 sun6i: Add gmac support for sun6i boards
Hookup the gmac found on the sun6i / A31 SoCs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Luc Verhaegen
2d7a084ba0 sunxi: video: Add simplefb support
Add simplefb support, note this depends on the kernel having support for
the clocks property which has recently been added to the simplefb devicetree
binding.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as
 disussed on the devicetree list]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>.
2014-11-25 13:38:46 +01:00
Luc Verhaegen
7f2c521f90 sunxi: video: Add cfb console driver for sunxi
This adds a fixed mode hdmi driver for the sunxi platform. The fixed
mode is a relatively safe 1024x768, more complete EDID handling is
currently not provided. Only HDMI is supported today.

This code is enabled when HPD detects an attached monitor.

Current config is such that 8MB is shaved off at the top of the RAM.
This avoids several memory handling issues, most significant is the fact
that on linux on ARM you are not allowed to remap known RAM as IO. A
clued in display driver will be able to recycle this reserved RAM in
future though.

cfbconsole was chosen as it provides the most important functionality: a
working u-boot console, allowing for the debugging of certain issues
without the need for a UART.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Major cleanups and some small bugfixes]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Hans de Goede
0bd5125133 sunxi: Add video pll clock functions
This is a preparation patch for adding support for HDMI out.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Hans de Goede
9d4b7d0bc8 sun4i: Rename dram_clk_cfg to dram_clk_gate
The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Tom Rini
fce0a90a68 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-11-24 17:05:11 -05:00
Alison Wang
c207ff6129 arm: ls102xa: Remove bit reversing for SCFG registers
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R                                   SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31

This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:23 -08:00
Jason Jin
644bc7ec5c arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:23 -08:00
Nikhil Badola
3f041f011d drivers: usb: fsl: Define USB configs for LS102XA
Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:22 -08:00
Nikhil Badola
f3dff695e1 drivers : usb: fsl: Implement usb Erratum A007798 workaround
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:04 -08:00
Tom Rini
dee332ffb7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-11-24 12:02:12 -05:00
Tom Rini
1739564e75 Merge git://git.denx.de/u-boot-dm
Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:01:48 -05:00
Tom Rini
746667f1e5 Merge git://git.denx.de/u-boot-x86
Conflicts:
	arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:00:00 -05:00
Nikita Kiryanov
44b9841d78 arm: imx: stop sata on boot
Ideally, the Linux kernel should get the hardware in its most
untouched state. For the most part, U-Boot does not reset the various
subsystems it touches before boot, and usually Linux deals with it, but
on some boards (cm_fx6) the Linux kernel fails to detect the ssd
correctly if sata is used by U-Boot.

Power off sata on OS boot so that Linux will have a clean state to work
with.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
2014-11-24 12:10:08 +01:00
Nikita Kiryanov
10ee8ecafb sata: implement reset_sata for dwc_ahsata
Add reset_sata() to the sata driver interface and implement it
for dwc_ahsata. This function cleans up after sata_init(), and
therefore accepts a device number like sata_init() does.
A dummy implementation is provided for the rest of the drivers.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
2014-11-24 11:59:59 +01:00
Nikita Kiryanov
8d29cef588 arm: mx6: introduce disable_sata_clock
Implement disable_sata_clock for mx6 SoCs.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
2014-11-24 11:59:59 +01:00
Hans de Goede
8bc347e2ec ARM: bootm: Allow booting in secure mode on hyp capable systems
Older Linux kernels will not properly boot in hyp mode, add support for a
bootm_boot_mode environment variable, which can be set to "sec" or "nonsec"
to force booting in secure or non-secure mode when build with non-sec support.

The default behavior can be selected through CONFIG_ARMV7_BOOT_SEC_DEFAULT,
when this is set booting in secure mode is the default. The default setting
for this Kconfig option is N, preserving the current behavior of booting in
non-secure mode by default when non-secure mode is supported.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
2014-11-24 09:09:52 +01:00
Hans de Goede
ea624e1951 ARM: Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options
Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options, this is a
preparation patch for adding an env variable to choose between secure /
non-secure boot on non-secure boot capable systems, specifically this
prepares for adding CONFIG_ARMV7_BOOT_SEC_DEFAULT as a proper Kconfig option.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-24 09:09:49 +01:00
Suriyan Ramasami
96b1046d1c sandbox: Prepare API change for files greater than 2GB
Change the internal sandbox functions to use loff_t for file offsets.

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>

Acked-by: Simon Glass <sjg@chromium.org>
2014-11-23 06:49:04 -05:00
Masahiro Yamada
4efb654223 tegra: do not descend into empty directories
Some tegra makefiles only contain a dummy line to generate
a built-in.o.  Let's do not descend into such directories.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
56f31e872e kbuild: use SoC-specific CONFIG to descend into SoC directory
Use "obj-$(CONFIG_FOO) += foo/" where it is possible.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
37c9940a09 x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
165ecd26f0 kbuild: Descend into SOC directory from CPU directory
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-23 06:49:02 -05:00
Steve Rae
abb1678cca ARM: bcm: Enable five Cygnus boards
bcm911360_entphn
bcm911360_entphn-ns
bcm911360k
bcm958300k-ns
bcm958305k

- updates to support Cygnus and NSP board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-11-23 06:49:00 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Nikhil Badola
c26c80a1a4 drivers: usb: fsl: Move USB Errata checking code
Move USB Errata checking code from "arch/powerpc" to architecture independent
file "fsl_usb.h" so that errata(s) become independent of the architecture.
For each erratum checking function for PPC arch, define a nop function for
non PPC arch for successful compilation in either case

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-21 09:28:28 -08:00
Ye.Li
7a26416847 mx6: thermal: Check cpu temperature via thermal sensor
Add imx6 thermal device to mx6 soc file. Read the cpu temperature
using this device to access onchip thermal sensor.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-11-21 15:30:12 +01:00
Nitin Garg
cf202d268b mx6: clock: Add thermal clock enable function
Add api to check and enable pll3 as required
for thermal sensor driver.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-11-21 15:18:47 +01:00
Simon Glass
f8fff9dac9 dm: arm: spl: Make driver model linker lists available
The linker lists feature is useful in SPL as it holds the driver model
platform data. So don't throw away the lists.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 08:14:11 +01:00
Simon Glass
ba19599b44 dm: arm: spl: Allow simple malloc() in SPL
For SPL it is sometimes useful to have a simple malloc() just to permit
driver model to work, in the cases where the full malloc() is not made
available by the board config.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:12:39 +01:00
Simon Glass
0f65f48b64 dm: at91: Add driver model support for the serial driver
Add driver model support while retaining the existing legacy code. This
allows the driver to support boards that have converted to driver model
as well as those that have not.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:09:58 +01:00
Simon Glass
12fe7f7c2a dm: at91: Add platform data for GPIO on at91sam9260-based boards
These boards all have the same GPIO arrangement, so add some common platform
data that can be used by all boards. Remove the configs which are no longer
required.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:09:36 +01:00
Simon Glass
918354b18e dm: at91: Add driver model support for atmel GPIO driver
Modify this driver to support driver model, with platform data required to
determine the GPIOs that it controls.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:08:19 +01:00
Simon Glass
fe5b9b447c x86: Rename chromebook-x86 to coreboot
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.

So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it would be possible to remove the vendor for
now, that would be short-sighted.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:16 +01:00
Simon Glass
65dd74a674 x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
3eafce0527 x86: ivybridge: Add LAPIC support
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
a49e3c7f09 x86: Make show_boot_progress() common
This function can probably be used on all x86 boards, so move it into the
common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
437c2b7cd0 x86: chromebook_link: Enable GPIO support
Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
1b4f25ff8e x86: ivybridge: Add support for early GPIO init
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.

In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
8e0df066ff x86: ivybridge: Add early init for PCH devices
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
9c678e152a x86: dts: Add microcode updates for ivybridge CPU
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.

Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
77f9b1fb62 x86: ivybridge: Perform Intel microcode update on boot
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
94060ff278 x86: ivybridge: Check BIST value on boot
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
f5fbbe9579 x86: ivybridge: Perform initial CPU setup
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
eddbad224b x86: Add msr read/write functions that use a structure
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
3f70a6f577 x86: Add clr/setbits functions
These are available on other architectures. Make them available on x86 also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
378a8634ad x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
2b6051541b x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6fb3b72e87 x86: pci: Allow configuration before relocation
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6e5b12b614 x86: ivybridge: Enable PCI in early init
Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
7430f10864 x86: Support use of PCI before relocation
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:12 +01:00
Simon Glass
d188b18f65 x86: Refactor PCI to permit alternate init
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
70a09c6c3d x86: chromebook_link: Implement CAR support (cache as RAM)
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
d1cd045982 x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
fce7b27683 x86: Build a .rom file which can be flashed to an x86 machine
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.

Create a u-boot.rom output file for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
8ef07571a0 x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
5c1b685e46 x86: Allow timer calibration to work on ivybridge
Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.

For this CPU we know the frequency, so add another special case for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Masahiro Yamada
a5eb04db1a x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:12 +01:00
Simon Glass
727c1a9871 x86: Replace fill_processor_name() with cpu_get_name()
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
003504b6fe x86: Remove unnecessary find_fdt(), prepare_fdt() functions
These are no-longer needed so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
21b9b14b49 x86: Add processor functions to halt and get stack pointer
Add a function to get the stack pointer and another to halt the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
6cba6b9209 x86: Fix a warning with gcc 4.4.4
This warning appears even though it seems that the compiler could work it
out. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
258b1357c6 x86: Save TSC frequency in the global data
Return the saved TSC frequency in get_tbclk_mhz().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
80de049561 x86: Add quick TSC calibration via PIT
Use the same way that Linux does for quick TSC calibration via PIT
when calibration via MSR fails.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
076bb44b0e x86: Do TSC MSR calibration only for known/supported CPUs
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
52f952bf5e x86: Do CPU identification in the early phase
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:10 +01:00
Simon Glass
f67cd51e65 x86: Save the BIST value on reset
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:10 +01:00
Simon Glass
e1ffd81797 x86: Fix up some missing prototypes
Some functions are missing prototypes. Fix those that are specific to x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
8b37c7694f x86: Use the standard arch_cpu_init() function
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
07387d1769 x86: Use the standard dram_init() function
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
76f90f3020 x86: Tidy up global descriptor table setup
This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
3c00695ee1 x86: Invalidate TLB as early as possible
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
85d87328ea x86: Remove board_init16() call which is not used
This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:08 +01:00
Simon Glass
bc48806161 x86: Remove REALMODE_BASE which is no longer used
This was missed when the real mode support was dropped. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:08 +01:00
Simon Glass
e895a4b06f fdt: Allow ft_board_setup() to report failure
This function can fail if the device tree runs out of space. Rather than
silently booting with an incomplete device tree, allow the failure to be
detected.

Unfortunately this involves changing a lot of places in the code. I have
not changed behvaiour to return an error where one is not currently
returned, to avoid unexpected breakage.

Eventually it would be nice to allow boards to register functions to be
called to update the device tree. This would avoid all the many functions
to do this. However it's not clear yet if this should be done using driver
model or with a linker list. This work is left for later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-11-21 04:43:15 +01:00
Masahiro Yamada
cba1da495d include: move various macros to include/linux/kernel.h
U-Boot has imported various utility macros from Linux
scattering them to various places without consistency.

In include/common.h are min, max, min3, max3, ARRAY_SIZE, ALIGN,
container_of, DIV_ROUND_UP, etc.
In include/linux/compat.h are min_t, max_t, round_up, round_down,
etc.
We also have duplicated defines of min_t in some *.c files.

Moreover, we are suffering from too cluttered include/common.h.

This commit moves various macros that originate in
include/linux/kernel.h of Linux to their original position.

Note:
This commit simply moves the macros; the macros roundup,
min, max, min2, max3, ARRAY_SIZE are different
from those of Linux at this point.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Masahiro Yamada
4515992fc7 replace DIV_ROUND with DIV_ROUND_CLOSEST
The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible
and safer than DIV_ROUND.

For example,
  foo = DIV_ROUND_CLOSEST(x, y++)
works expectedly, but
  foo = DIV_ROUND(x, y++)
does not. (y is incremented twice.)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Masahiro Yamada
3fd968e931 ARM: remove CONFIG_ARM1136 defines
CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM1136 and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Masahiro Yamada
5d7b131d41 ARM: remove CONFIG_ARM926EJS defines
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Masahiro Yamada
f2168440de ARM: remove CONFIG_ARM920T defines
CONFIG_CPU_ARM920T was introduced into Kconfig by commit 2e07c249a6
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM920T and replaces the
only reference in drivers/usb/host/ohci-hcd.c with CONFIG_CPU_ARM920T.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00