Commit graph

11031 commits

Author SHA1 Message Date
Brad Griffis
84cf295f84 arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error
Add 1ms delay to avoid L3 timeout error during suspend resume.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05 08:48:50 -04:00
Brad Griffis
82195797a4 arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and EXT_PHY_CTRL1_SHADOW
Adjust DQS skew in case where invert_clkout=1 is used.
Match recommended values from EMIF Tools app note:

http://www.ti.com/lit/an/sprac70/sprac70.pdf

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-05-05 08:48:50 -04:00
Simon Goldschmidt
1b1d8c19f5 spl: fix linker size check off-by-one errors
This fixes SPL linker script size checks for 3 lds files where the size
checks were implemented as "x < YYY_MAX_SIZE".

Fix the size checks to be "x <= YYY_MAX_SIZE" instead.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-05 08:48:50 -04:00
Dinh Nguyen
aaa6480370 configs: socfpga: add imply pl310 cache controller
Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05 08:48:50 -04:00
Dinh Nguyen
d97d8fcae5 ARM: socfpga: use the pl310 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05 08:48:50 -04:00
Dinh Nguyen
2bac27ce94 ARM: pl310: Add macro's for handling tag and data latency mask
Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05 08:48:50 -04:00
Vignesh Raghavendra
add4967124 arch: armv8: Provide a way to disable cache maintenance ops
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.

For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:

	Start DMA to write to destination buffer
	Wait for DMA to be done (dma_receive()/dma_memcpy())
	Invalidate destination buffer (invalidate_dcache_range())
	Read from destination buffer

The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.

In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.

Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).

In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
flush_dcache_all() and invalidate_dcache_all() are exclusively used
during enabling/disabling dcache and hence are not disabled.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-05-05 08:48:50 -04:00
Marek Vasut
6b955cbaea ARM: rmobile: Always select pin control drivers on Gen3
To assure the pins on R-Car Gen3 SoCs are configured correctly, always
select pin control drivers on Gen3 SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04 19:26:49 +02:00
Robert P. J. Day
7225a27ffa delete Kbuild "select" of long-dead SPL_DISABLE_OF_CONTROL
>From way back in 2015:

  commit dffb86e468
  Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  Date:   Wed Aug 12 07:31:54 2015 +0900

    of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL

    As we discussed a couple of times, negative CONFIG options make our
    life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
    and here is another one.

    Now, there are three boards enabling OF_CONTROL on SPL:
     - socfpga_arria5_defconfig
     - socfpga_cyclone5_defconfig
     - socfpga_socrates_defconfig

    This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
    CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
    the logic.

    Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
    Reviewed-by: Tom Rini <trini@konsulko.com>
    Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-05-04 13:04:18 -04:00
Bartosz Golaszewski
cef443c166 arm: davinci: remove leftover code for dm* SoCs
The support for DaVinci DM* SoCs has been dropped a while ago. There's
still a lot of leftover code in mach-davinci though. Entirely remove
certain files and modify the common code to no longer reference
unsupported chips.

Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX
but not all define SOC_DA850 (e.g. omapl138). We can safely remove
all ifdefs for the former, but let's leave the ones for the latter.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04 13:04:10 -04:00
Bartosz Golaszewski
0c56542592 arm: davinci: remove dead code for PHYs used by DaVinci DM* boards
The support for DaVinci DM* boards has been dropped a while ago. The
code for all those PHYs is no longer used and they have their own
proper PHY drivers in drivers/net/phy anyway. Remove all dead code.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04 13:04:06 -04:00
Tom Rini
4862830b69 Merge git://git.denx.de/u-boot-socfpga
- Misc MMC, FPGA bridge, general SoCFPGA fixes
2019-05-03 14:23:01 -04:00
Tom Rini
c767b6ac98 Merge git://git.denx.de/u-boot-usb
- DaVinci updates
2019-05-03 14:22:38 -04:00
Tom Rini
90c2ebd215 Merge git://git.denx.de/u-boot-marvell
- Fix in kwbimage (return code checking) (Young Xiao)
- Misc updates to Turris Omnia (Marek)
2019-05-03 14:22:23 -04:00
Adam Ford
ff83e4c368 ARM: davinci: Remove unused functions from header
There are a few functions defined in the header file, but they are
not referenced by any Davinci code.  In order to make a general
function in the future with static function declarations, this
patch will remove the references all together.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-03 17:14:49 +02:00
Tom Rini
b362fe0848 Merge branch '2019-05-03-master-imports'
- Various btrfs fixes
- Various TI platform fixes
- Other fixes (cross build, taurus update, Kconfig help text)
2019-05-03 07:30:55 -04:00
Adam Ford
d66f4fe982 ARM: dts: logicpd-som-lv: Fix MMC1 card detect
The card detect pin was incorrectly using IRQ_TYPE_LEVEL_LOW
instead of GPIO_ACTIVE_LOW when reading the state of the CD pin.

Without this patch, MMC1 won't be detected.

This is the same patch submitted to linux-omap, but I was hoping
to get it applied to U-Boot without having to wait for the
linux adoption and then backporting.

Fixes: 5448ff33f2 ("ARM: DTS: Resync Logic PD SOM-LV 37xx
devkit with Linux 4.18-RC4")

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-03 07:30:31 -04:00
Vagrant Cascadian
59a1df084f ti: Add device-tree for am335x-pocketbeagle.
Add device-tree files from linux 5.1-rc7 needed to complete support
for PocketBeagle.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-03 07:30:31 -04:00
Andreas Dannenberg
7202af927b arm: dts: k3-am654: Sync IOPAD macros with Linux
Transition to the IOPAD macros as used in Linux in which the pin mux
mode is specified using a dedicated parameter while also dropping the
related MUX_MODEx macros that are no longer needed. This transition
will allow us to keep both Linux and U-Boot DTS in sync more easily.
While at it also align the file name of the include file itself and
update any references accordingly.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-05-03 07:30:31 -04:00
Heiko Schocher
0cac0fb022 at91: cleanup taurus port
- at91sam9g20-taurus.dts: use labels
- cleanup taurus port to compile clean with
  current mainline again. SPL has no serial
  output anymore, so it fits into SRAM.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-05-03 07:30:31 -04:00
Andreas Dannenberg
12df71cd74 armv7R: dts: k3: am654: Switch DMSC TX message thread ID
Switch from using the high priority DMSC transmit message queue used
by the secure R5 MCU island boot context to the low priority message
queue. While the change in priority is irrelevant for the current boot
architecture it however gives us access to a deeper message queue that
will allow us to buffer more messages. This is an important aspect when
sending several messages without requesting and waiting for a response
in a row which is a communication scheme used during core shutdown for
example. See AM654 TISCI User Guide for additional details.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-05-03 07:23:17 -04:00
Marek Behún
539f0242f3 arm: mvebu: turris_omnia: add RESET button handling
There is a Factory RESET button on the back side of the Turris Omnia
router. When user presses this button before powering the device up and
keeps it pressed, the microcontroller prevents the main CPU from booting
and counts how long the RESET button is being pressed (and indicates
this by lighting up front LEDs).

The idea behind this is that the user can boot the device into several
Factory RESET modes.

This patch adds support for U-Boot to read into which Factory RESET mode
the user booted the device. The value is an integer stored into the
omnia_reset environment variable. It is 0 if the button was not pressed
at all during power up, otherwise it is the number identifying the
Factory RESET mode.

This patch also changes bootcmd to a special hardcoded value if Factory
RESET button was pressed during device powerup. This special bootcmd
value sets the colors of all the LEDs on the front panel to green and
then tries to load the rescue image from the SPI flash memory and boot
it.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-05-03 08:14:39 +02:00
Marek Behún
6b26f3e312 arm: mvebu: turris_omnia: move ATSHA204A from defconfig to Kconfig
This driver is required for Turris Omnia to read ethernet addresses.
Move the dependency from turris_omnia_defconfig to Kconfig.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-05-03 08:14:39 +02:00
Marek Behún
8420edcfda arm: mvebu: turris_omnia: move I2C dependencies to Kconfig
The I2C dependencies are defined in include/configs/turris_omnia.h,
because Turris Omnia won't boot correctly without I2C support.

Move these dependencies to Kconfig, so that they are selected if Turris
Omnia is selected as target.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-05-03 08:14:39 +02:00
Tom Rini
3570ea1f98 Improvements and new features:
- improved SPI driver for better read throughput
 - refactors initialisation of debug UART init
 - restructures header file paths
 - adds pinctrl improvements
 
 Adds Kever as a co-custodian.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcyU2hAAoJECaAFcEOcohNlFsH/3ujz7paIV34ilGGA1BQPJS7
 OOnJ7KOKkWBpwl8ai03n8/sK9kkEshZ8/PQE3E2UeWbwE9knDAREwNynYRqNwv5P
 f/6HuFZ3tCCRfVBsbTpSe4b/BxIn2zavhMQVfgd8kYaSY7dWzeaBB28GbKxfApHY
 ysNF5Q5oGMwTaL322vpFOmk/a5rHrSI8KJloDzTWxAPbNRIf3fUhwl1imSbGB6RP
 wWwuBCfbTcvw9+F4bK2W3q+umSg7o9zPwwno7Invh/nPqe5ExrVuzalRG4+1vtXe
 3jBKWTVFYX2KPDBpAfaMItehGPeGJet7+mU4GcW1FaCtlyE9QqXKfZknplCfKyU=
 =NpSn
 -----END PGP SIGNATURE-----

Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchip

Improvements and new features:
- improved SPI driver for better read throughput
- refactors initialisation of debug UART init
- restructures header file paths
- adds pinctrl improvements

Adds Kever as a co-custodian.
2019-05-01 11:52:04 -04:00
Tom Rini
b4ee6daad7 Porting to DM and i.MX8
------------------------
 
 - warp7 to DM
 - kp_imx53 to DM
 - Warnings in DT
 - MX8QM support
 - colibri-imx6ull to DM
 - imx7d-pico to DM
 - ocotp for MX8
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlzDBtoPHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et3UpQL/ipaUejQOOr00oOgUBQqt3JCPZ7KNu8ruih/
 nIFUDrI8nP+4psaOhRp1sEPFJUxUjdIqODeAZD8zrlEi1pXNAgPWYrFRfbz54bzw
 jLsqqMz1/djQseLydQTcqZTSz8Ys7o+8OfKH64fdsZn+y9no9tHBN5hz5qWdXexN
 kbyykkg8TJC3eUyRZqKuULOqzDV9BAdASOXu7UTa04sEekLdVvS2+zkUdB6UVZTN
 LOAzm+7xY8Tey1BZxLuZUJDpHzFEMvPvlbbQRrxeDn/feZJwNgIP6hGcMeVOwOIf
 KEwFn/m/HI2JWS4taXb5aT+v3xmiQvyCC3jNW0XTf5rq02pbfgyPsVhGQIGyU2yY
 Fj7zIN7hVCLJNBpctvXyuAd1MjOlGEPIrHNjRnIZjtr7/iA1AIRn7Hg4cGNCHw6V
 5gdza3B/xFODN+Ts6O+UVIukI61MJ6mGGdNCueOnWDviNROOL82D7Jh02KfNNNxR
 q+yPsHSpo6rC1MGXv4SOReZtgpng/w==
 =CzWQ
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Porting to DM and i.MX8
------------------------

- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
2019-05-01 07:25:51 -04:00
Philipp Tomsich
dd320e122f rockchip: rk3288: include header for back_to_bootrom
To avoid a warning, we need to include the header defining
back_to_bootrom for us.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Philipp Tomsich
8c5805a210 rockchip: rk3399: include gpio.h
After applying the series for debug_uart_init(), Travis-CI reports:

arch/arm/mach-rockchip/rk3399/rk3399.c:90:2: error: implicit declaration of function 'spl_gpio_set_pull' [-Werror=implicit-function-declaration]
  spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  ^~~~~~~~~~~~~~~~~

This is caused by a missing header-file include.  Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Kever Yang
c79bce16e5 rockchip: rk3399: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Kever Yang
f9e8145614 rockchip: rk3399: use grf structure to access reg
Prefer to use structure to access register if we could.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
6a03335714 rockchip: rk3368: move board_debug_uart_init() to rk3368.c
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
e83e885e53 rockchip: rk3288: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
070e48b30e rockchip: rk3288: use grf structure to access soc_con2
Prefer to use structure to access register if we can.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
28fe4d5b30 rockchip: rk322x: move board_debug_uart_init() to rk322x.c
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up header-list to not break FASTBOOT:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
86d0eca451 rockchip: rk3188: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
7f3eec03d5 rockchip: rk3036: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed whitespace error:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
b0a569da08 rockchip: enable DEBUG_UART_BOARD_INIT by default
All Rockchip SoCs use DEBUG_UART_BOARD_INIT to init per board
UART IOMUX, enable it by default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:06 +02:00
Kever Yang
b1b449bf1f rockchip: correct ARCH_SOC name
The ARCH_SOC name default as 'rockchip' and we put all the
header file in 'arch/arm/include/asm/arch-rockchip/', but
the 'rockchip' is not the SOC name, let's correct it after
we update all the source file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsiich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
6916dad511 rockchip: arm: use 'arch-rockchip' for common header
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
9f09b9d3cc rockchip: arm: remove no use macro
TIMER7_BASE is no used by source code now, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Urja Rannikko
59ef021b99 rk3288-board: remove pinctrl call for debug uart
This failed and caused a boot failure on c201, and afaik
the pins should be setup by the new pinctrl driver.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
ed9c9059f2 rockchip: rk3399: Add Orangepi RK3399 support
Add initial support for Orangepi RK3399 board.

Specification
- Rockchip RK3399
- 2GB/4GB DDR3
- 16GB eMMC
- SD card slot
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- Mini PCIe
- Sensors, Keys etc
- DC12V-2A and DC5V-2A

Commit details about Linux DTS sync:
"arm64: dts: rockchip: Add support for the Orange Pi RK3399"
(sha1: d3e71487a790979057c0fdbf32f85033639c16e6)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
e05b4a4fa8 rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi
u-boot,dm-pre-reloc is required for SDMMC booted rk3399 boards and
which is U-Boot specific devicetrees binding.

Move it on global rk3399-u-boot.dtsi file and rest of the U-Boot
bindings will move it future based on the requirement.

This would help to sync the devicetrees from Linux whenever required
instead of adding specific nodes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
288dbc66da rockchip: dts: rk3399: Sync rk3399-opp from Linux
Sync rk3399-opp.dtsi from Linux.

Linux commit details about the rk3399-opp.dtsi sync:
"arm64: dts: rockchip: use SPDX-License-Identifier"
(sha1: 4ee99cebd486238ac433da823b95cc5f8d8a6905)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Simon Goldschmidt
7110259f55 dts: arm: socfpga: fix socfpga_de10_nano console
Booting this board failed as the initial console isn't found since
commit c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")

The uart0 devicetree entry was missing "clock-frequency = <100000000>:"
since that commit

Fixes: c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
Reported-by: rafael mello <rafaelmello_3@hotmail.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-29 20:33:23 +02:00
Marek Vasut
c5f4b80575 ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.

The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.

Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.

However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.

The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.

[1] 75905816ec
[2] 8ba6986b04

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:33:45 +02:00
Marek Vasut
72c347ced8 ARM: socfpga: Add support for selecting bridges in bridge command
Add optional "mask" argument to the SoCFPGA bridge command, to select
which bridges should be enabled/disabled. This allows the user to avoid
enabling bridges which are not connected into the FPGA fabric. Default
behavior is to enable/disable all bridges.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:56 +02:00
Marek Vasut
ba2cfcee88 ARM: socfpga: Fully unmap the FPGA bridges from L3 space
Instead of just putting the bridges into reset, fully remove the bridges
from the L3 main bridge space when disabling them by clearing bits in
NIC-301 remap register. Moreover, only touch the 3 LSbits in brgmodrst
register as the rest of the bits are undefined.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:55 +02:00
Marek Vasut
c1d4b464c8 ARM: socfpga: Disable bridges in SPL unless booting from FPGA
Disable bridges between L3 Main switch and FPGA unless booting
from FPGA and keep them disabled to prevent glitches and possible
hangs of the L3 Main switch.

The current version of the code could have enabled the bridges
between the L3 Main switch and FPGA for a short period of time
in board_init_f() in case the FPGA was programmed and then again
disable them at the end of board_init_f(). Replace this with a
code which only sets up the handoff registers and let the user
enable the bridges later on.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:55 +02:00
Marek Vasut
8df653c325 ARM: socfpga: Factor out handoff register configuration
Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:55 +02:00
Heinrich Schuchardt
b85d155199 arm: dts: add missing vexpress device trees
Add the device trees for

* vexpress_ca5x2_defconfig
* vexpress_ca9x4_defconfig
* vexpress_ca15_tc2_defconfig

as available in Linux 5.1 rc5.

We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig
for Travis testing via QEMU.

The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires
that an embedded board either provides a device tree or an ACPI table.

All block devices are meant to be moved to the driver model. On ARM this
requires a device tree.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-04-26 18:58:22 -04:00
Gregory CLEMENT
c8aac24629 arm: lpc32xx: Fix timer initialization
The match controller register is not cleared during
initialization. However, some bits of this register may reset the TC if
tnMRx match it.

As we can't make any assumption about how U-Boot is launched by the first
stage bootloader (such as S1L) clearing this register ensure that the
timers work as expected.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-26 18:58:20 -04:00
Andrew F. Davis
508369672c arm: mach-k3: Add secure device build support
K3 HS devices require signed binaries for boot, use the SECDEV tools
to sign the boot artifacts during build.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-26 17:51:51 -04:00
Andrew F. Davis
3a543a8084 arm: mach-k3: Add secure device support
K3 devices have High Security (HS) variants along with the non-HS already
supported. Like the previous generation devices (OMAP/Keystone2) K3
supports boot chain-of-trust by authenticating and optionally decrypting
images as they are unpacked from FIT images. Add support for this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-26 17:51:51 -04:00
Andrew F. Davis
407a219261 arm: K3: Avoid use of MCU_PSRAM0 before SYSFW is loaded
On HS devices the 512b region of reset isolated memory called
MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we
cannot use this memory. It is only used to store a single value
left at the end of SRAM by ROM that will be needed later. Save
that value to a global variable stored in the .data section.
This section is used as .bss will be cleared between saving
this value and using it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-26 17:51:51 -04:00
Tom Rini
07b68b7843 Merge git://git.denx.de/u-boot-marvell
- Add DM based generic watchdog start and reset implementation
  and remove all ad-hoc implementations (Stefan)
- Move mv_sdhci to DM (Pierre)
- Misc turris_omnia updates (Pierre)
- Change openrd targets to correctly build again (size changes
  and fixes to the dts targets) and bring it back into Travis
  builds (Stefan)
- Add Kirkwood db-88f6281-bp board (Chris)
2019-04-26 13:50:00 -04:00
Tom Rini
1c64692df2 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2019-04-26 13:49:58 -04:00
Stefan Roese
c2ff69a444 watchdog: at91sam9_wdt: Remove now superfluous wdt start and reset
With the new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).

The watchdog servicing is enabled via CONFIG_WATCHDOG.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-26 09:16:32 +02:00
Chris Packham
d55254ab77 ARM: kirkwood: add db-88f6281-bp board
This is Marvell's Kirkwood development board. It has the following
features

 - 512M DDR2
 - 2 PCI connectors
 - 1 x1 PCI-e interface
 - 1 Gigabit Ethernet Port
 - 2 SATA Ports
 - USB 2.0 Interface
 - SDIO
 - 128M NAND Flash
 - 16M SPI Flash

It can be strapped to boot from SPI or NAND so there are two defconfigs
(one per boot media).

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Stefan Roese
9408665709 arm: kirkwood: dts: Add openrd-* dtb makefile build targets
The following Kirkwood dtb build targets are currently missing:

kirkwood-openrd-base.dtb
kirkwood-openrd-client.dtb
kirkwood-openrd-ultimate.dtb

This patch adds them to the Makefile to fix the build error.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Pierre Bourdon
4ec9dd4071 mmc: mv_sdhci: add driver model support
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Pierre-Jean Texier
6b503f9e65 warp7: Switch to DM USB
This commit switches to DM USB for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:21:00 +02:00
Pierre-Jean Texier
0710726d04 warp7: Switch to DM Serial
This commit switches to DM SERIAL for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:20:32 +02:00
Marcel Ziswiler
d32273b91c ARM: dts: colibri-imx6ull: update device tree
Fix compatible node to use regular Toradex notation.
Annotate device tree with standard Colibri pin muxing comments.
Use open-drain I2C pin muxings.
Alphabetically re-order iomuxc nodes.
Rename snvs-ad7879-int-grp touch interrupt node as per Linux device tree.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:18:50 +02:00
Marcel Ziswiler
d487351959 ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl
Add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also fix indentation of pinfunc header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:18:46 +02:00
Marcel Ziswiler
7b69baea42 ARM: dts: i.MX6Q: fix avoid_unnecessary_addr_size warnings
Re-synced the device tree with Linux 5.0.

This fixes the following warnings:

w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@0:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@1:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@2:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@3:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@4:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@1:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@2:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@3:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@4:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@0: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@0: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@1: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@1: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@2: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@2: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@3: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@3: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@4: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@4: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@1: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@1: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@2: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@2: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@3: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@3: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@4: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@4: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 Failed prerequisite 'avoid_default_addr_size'

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 19:16:24 +02:00
Parthiban Nallathambi
d8d33b6d4d imx: Add variscite DART-6UL Evaluation Kit
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial@02020000
Out:   serial@02020000
Err:   serial@02020000
Net:   FEC0

Working:
 - Eth0
 - i2c
 - MMC/SD
 - eMMC
 - USB host
 - UART 1

Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html

Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-04-25 19:16:24 +02:00
Peng Fan
702339bdf4 imx: i.MX8MQ: clear ocotp error bit
In case ocotp error bit is set, clear it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:16:24 +02:00
Peng Fan
7a0c9b0888 imx: add lowlevel init for ARM64
Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:16:24 +02:00
Chris Packham
4eceb4bc8b ARM: imx: Fix typo in select option for ZMX25
Correct CPU_ARM926EJS1 to CPU_ARM926EJS.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:16:24 +02:00
Filip Brozovic
8e10571f09 dts: imx6ull: add USB aliases to support DM
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-04-25 19:16:24 +02:00
Joris Offouga
4e267b92fb pico-imx7d: Convert DM MMC
This patch enable convert DM MMC for imx7d-pico board and variant.

Before the DM conversion only usdhc3 was enabled and therefore it appeared
as MMC 0 to u-boot. After enabling MMC DM though usdhc3 defaults to MMC 2,
which left unattended would drive changes to existing pico-pi bootscripts and
environment variables that rely on mmc 0.

Setup the alias of mmc0 and usdhc3 so that existing pico-imx7d boot code will
work unmodified.

When converting to DM_MMC it is necessary that SPL initializes eMMC
by itself, so move the original eMMC initialization from U-Boot
proper to SPL.

Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:16:24 +02:00
Marcel Ziswiler
270f1fb7b2 arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3
Add support for lpuart1, lpuart2 and lpuart3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:16:24 +02:00
Marcel Ziswiler
edcd4d1b88 misc: imx8: remove duplicates from scfw api
Remove duplicate function declarations from the SCFW API header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:16:24 +02:00
Joris Offouga
7c748933e3 Arm: imx7d-pico: Import all Linux device tree for Pico i.MX7D SOM
This patch imports the Linux kernel base board imx7d-pico.dtsi,
pi board imx7d-pico-pi.dts and hobbit board imx7d-pico-hobbit.dts
from Linux v5.1-rc1.

Signed-off-by: Joris Offouga <offougajoris@gmail.com>
2019-04-25 19:16:24 +02:00
Marcel Ziswiler
9233c3d377 ARM: dts: colibri-imx6ull: fix uart-has-rtscts property
Remove vendor pre-fix fsl, from uart-has-rtscts property.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
5d67b73c1a colibri-imx6ull: migrate fec to using driver model
Migrate Ethernet FEC to using driver model.
Drop PHY_MICREL_KSZ90X1 which slipped in from Apalis iMX6.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
87b32297f5 colibri-imx6ull: migrate usb to using driver model
Migrate USB to using driver model.
Add USBH_PEN GPIO regulator.
While at it also add alias e.g. as required for UMS.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
535800d33f colibri-imx6ull: migrate mmc to using driver model
Migrate MMC to using driver model.
Migrate USDHC to using pinctrl.
While at it also add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
75b942df87 colibri_vf: fix ethernet by adding explicit phy node
The implicit fallback mechanism for searching the whole MDIO bus for at
least one PHY has been gone with the following commit b882005a18
("drivers/net/fec: phy_init: remove redundant logic"). This lead to the
Ethernet driver erroring out as follows:

Net:   Could not get PHY for FEC0: addr -19
eth-1: fec@400d1000
Colibri VFxx # dhcp
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
No ethernet found.
Could not get PHY for FEC0: addr -19
Colibri VFxx #

This commit adds an explicit PHY node which makes it work again.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Peng Fan
0d331c035a imx: support i.MX8QM MEK board
Add i.MX8QM MEK board support.
Included a basic dts, enabled SPL FIT

Boot log as below:
U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
Normal Boot
Trying to boot from MMC2_2

U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)

CPU:   NXP i.MX8QM RevB A53 at 142933 MHz

Model: Freescale i.MX8QM MEK
Board: iMX8QM MEK
Build: SCFW 9330215b
Boot:  SD1
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:
Error: ethernet@5b040000 address not set.
eth-1: ethernet@5b040000
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
4ba1b34dfe imx8: imx8-pins: add i.MX8QM
Add i.MX8QM entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
7f50af6090 imx8: add cpu support
Add cpu type and Kconfig entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
b18da229a3 arm: dts: introduce dtsi for i.MX8QM
Introduce basic dtsi for i.MX8QM, only support SDHC/FEC/LPUART.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
13e7b72f32 ARM: defconfig: kp_imx53: Enable DM_USB support on HSC|DDC boards
This commit enables the DM_USB on HSC|DDC i.MX53 based boards.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
e626fcb6e2 DTS: Enable USB host support (including regulators) on HSC|DDC boards
This commit enables the support for K&P's HSC|DDC imx53 based boards.
It was also necessary to provide device tree description for regulators
to avoid board specific code definition.

The GPIO pin description responsible for VBUS control has been moved from
"hog" group to usbh1 dedicated one.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
552b1b3142 DTS: Provide USB host DTS description for i.MX53 devices
This code has been ported from Linux kernel - tag v5.1-rc2.
The difference from the kernel is the removal of:
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;

properties, which are not needed for correct u-boot operation (as PHY
setup is done in ehci-mx5.c file itself).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
81253ebba2 ARM: Enable CONFIG_DM_MMC and CONFIG_DM_BLK on HSC and DDC boards
This commit enables DM_MMC and DM_BLK on imx53 based HSC and DDC boards.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
fc77d4d6db DTS: Add esdhc3 device tree description tuning for HSC|DDC boards
In this commit the esdhc3 controller is enabled as well as it is remaped
to mmc0 to not break legacy code.

The pinctrl setup (e.g. 0x1e4) is the same as one from in-board file
definition.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Peng Fan
e5b8f7e665 imx8qxp: mek: enable dm-spl for pm
with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.

Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
a87eb0405f imx: sip: add call_imx_sip_ret2
This function will be used by i.MX8 fuse driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 09:03:15 +02:00
Ley Foon Tan
bf068c7643 arm: socfpga: mailbox: Fix off-by-one error on command length checking
A mailbox command contains 1-u32 header + arguments. The "len" variable
only contains the length of the arguments, but not the 1-u32 header.
Include the length of header when checking the ring buffer space to
prevent off-by-one error.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
9dc61aac2d arm: socfpga: gen5: reduce SPL pre-reloc malloc
By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
aef44283ac arm: socfpga: imply/default common config options
This commit moves common config options used in all socfpga boards
to select/imply in Kconfig. This both cleans up the defconfig files
as well as makes future changes easier.

Options implied/defaulted for all sub-arches:
- SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS

Options implied/defaulted for implied for A10 & gen5:
- FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE

Options implied/defaulted for gen5:
- SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
Tom Rini
7d99406742 Various minor sandbox iumprovements
Fixes for tracing with sandbox
 Refactoring for boot_get_fdt()
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlzAfvkACgkQfxc6PpAI
 reYu9AgAjaFmydXjE8DxkSB3rR7DHZFTs1erVKAAL2v+Tdf7LDmz+j6u1M3v55WY
 6r54f/gZ1UX5TEmQgEAKLa7QvvRO/lNvSGQnLHhZhv2IVWo7uWCKAUPdQ6XVZnUK
 zO5v+ucs9Ne4HxQJHMC509HUIIBbydiRvUm8W0SeBZy4kEyJDuub4L+rpARkXNks
 IZfKuY+VS4FK73D4M9PIhoXSubZgVS4AEcapakU1DvEz0kjsN4wr4idGrp3lutPC
 455imz83JBq2+mx1oxclOGedkIDzTCq+nWQAwSftMehrJpGrp7RLNo0v4QZZUf4V
 LIXRqObIYse9yQLkYPpeBdePMc8/tQ==
 =0NJ2
 -----END PGP SIGNATURE-----

Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm

Various minor sandbox iumprovements
Fixes for tracing with sandbox
Refactoring for boot_get_fdt()
2019-04-24 12:27:29 -04:00
Tom Rini
c2bb9c5b9e STM32 MCUs update:
_ DT rework and alignment with DT kernel v4.20
 _ mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
 _ mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
 _ configs: update for F746/769 boards
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJcvxeXAAoJEMrHeC97M/+mkpgP/0Xi+pN81lXGEELdVARyu3o9
 g45Ap+xgARgMwtnwtDmx/7tbawieG7F7Gq/AcY+SOod4qIUfb+1LZ/7UMikzXfbG
 VsSFm1YtxTiHIldPAs+i5MU0OO8TphHpqEtI7kj6eAa3MwYYnhd4DTqI/qahexeU
 3FXnUZg6XhURj1Hp/k4lL+8aoEgQKrjPpSq6oKtbF2rUStwyWbZ2PDYbI19RCU6I
 So58wSQYt0W5CP/dbUDydKorjLirHEvj7ppiGMjwaFjSdipOblrinjLSJ2fVPosF
 EK5lG3AOdf4telYafuq2Ur6EXdGOP1HHdsRhUYBCbZchzGLbH2sGdAs2xHUEsxzV
 80+uE5grX46yAQAj2V8ogpIrP6E4PA4pwEZctsS+4tgUhz9NO7kxFooGmNUk5BkY
 ggtXRlYlmXEz+epoXL7Hr5XkHOObkPk5W/R8JiZqRNv4y3NovYbjqAwYYhPCG60k
 jzwT3BdZJDN28gBU57d60VPEhPQHzpoXc6v3rJ08uFhFms03iz7pj9gCsreF48A9
 jQPZ2nemFt4m4LBsKtihLhvb6t6EllOBkCvbYCD6zgebcjUOscJTq3/TnHrMiNBh
 6wUorR09Bn7iMqhs/rPzUUmwDSN9O78P6uBr/D1E8zA9t/mCPHJHVbUHzrB96UGI
 LA7QA1pWbuYtoVSYa09W
 =0eSL
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-boot

STM32 MCUs update:
- DT rework and alignment with DT kernel v4.20
- mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
- mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
- configs: update for F746/769 boards
2019-04-24 12:26:39 -04:00
Tom Rini
ceb6ddbc73 - Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
 - Add support for the Libretech-AC AML-S805X-AC board
 - Add Amlogic AXG reset compatible
 - Add I2C support for Amlogic AXG
 - Fix AXG PIN and BANK pinctrl definitions
 - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
 - Add initial support for Amlogic G12A SoC and U200 board
 - Enable PHY_REALTEK for selected boards
 - Fix Khadas VIM2 README
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJcvtmpAAoJEHfc29rIyEnRc78P/0vN7zuxfSganTctZJGyrika
 9i3aIwr03KaFJJKg2FpnjMvdoYfjbuQoJmCdtgyO5Gzw/E5m3b8zbOwxoXW0r8Mg
 56fTSh8my8XHxnrc+Ryv+qwnf8SRIDv7apNqk6vpmnq3OC6di/Z/BBi7jT/ptNm+
 fT/VvQDZkPl5Em3kO1899dpZ7mk5WBwrBeD3R8hrrHtpF45zlRXKPIA/rlcT01DD
 w1gKL7n8NNuV+PHB7fh+xYYW7XkZpINqg6RbEi4w/DpM9Piys4XlB8+W361OkU3O
 Mk0u4omb6ahVIzV7AT4/Xz7B6edO/JpuCkLF0CCIzWo6TBT4Dpkz2h0wVaUCuZBC
 /mykRIgYmFCtdFuUuklf12xKA2VzNfEqk+mzyohDwTxdpWnKZOyX+OfR6Y2PKL8Y
 qSSDYkgucf16SIDBXu8/uVI0RCLtCfza68/Py63Hu9tzFWrG3tC94j3xmXAt+gBA
 Rg25xQ+KfX6oEGbHpViBJDLDWZDzqRPlkAdp3mb08Zpq9cynQSfM5dyS02YnEod7
 80uyva2Bq8S5a2NQYtLJRim54N2rM4srgFFFS0Qw4Feqv7KRkbZl37mTraOLKFo+
 h8t2EQnlaiIzWEKwXmgd7eXS3wV3lsVDn1q/UzBdqkPgp4HQcBsUONh5dxrD5Bvq
 bm6hYo2+hqt583THUltr
 =Qb3V
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic

- Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
- Add support for the Libretech-AC AML-S805X-AC board
- Add Amlogic AXG reset compatible
- Add I2C support for Amlogic AXG
- Fix AXG PIN and BANK pinctrl definitions
- Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
- Add initial support for Amlogic G12A SoC and U200 board
- Enable PHY_REALTEK for selected boards
- Fix Khadas VIM2 README
2019-04-24 12:26:25 -04:00
Stefan Roese
f2100f6f77 dm: core: Change platform specific translation-offset handling
Testing has shown that the current DM implementation of a platform /
board specific translation offset, as its needed for the SPL on MVEBU
platforms is buggy. The translation offset is confingured too late,
after the driver bind functions are run. This may result in incorrect
address translations. With the current implementation its not possible
to configure the offset earlier, as the DM code has not run at all.

This patch now removed the set_/get_translation_offset() calls and
moves the translation offset into the GD variable translation_offset.
This variable will get used when CONFIG_TRANSLATION_OFFSET is enabled.
This option is enabled only for MVEBU on ARM32 platforms, where its
currenty needed and configured in the SPL.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pierre Bourdon <delroth@gmail.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Pierre Bourdon <delroth@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
2019-04-23 20:26:43 -06:00
Lars Povlsen
25c07c72fd ARMv8: PSCI: Fix PSCI_TABLE relocation issue
This fixes relaction isses with the PSCI_TABLE entries in
the psci_32_table and psci_64_table.

When using 32-bit adress pointers relocation was not being applied to
the tables, causing PSCI handlers to point to the un-relocated code
area. By using 64-bit data relocation is properly applied. The
handlers are thus in the "secure data" area, which is protected by
/memreserve/ in the FDT.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-04-23 17:57:28 -04:00
Fabien Parent
def2fc05f6 ARM: MediaTek: Add support for MT8516 SoC
Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Shawn Guo
7c798a11d4 poplar: enable Ethernet driver support
The 'phy' reset of gmac device in kernel device tree is not generic
enough for u-boot to use, so we need to overwrite the 'resets' property
as needed.  With this device tree fixup and poplar_defconfig changes,
Ethernet starts working on Poplar board.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:25 -04:00
Philippe Reynes
4ae0542de7 dt: bcm963158: enable led controller
Enable the led controller in the device tree
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
cfbb03be1c dt: bcm63158: add led controller
Add the led controller in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
9689921921 dt: bcm968580xref: enable led controller
Enable the led controller in the device tree
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:14 -04:00
Patrice Chotard
c89b87cbfc ARM: dts: stm32: Update sdmmc binding for stm32mp157c-ed1
Update some sdmmc properties which have been updated with
v4.19 DT bindings:
      - st,dirpol becomes st,sig-dir
      - st,negedge becomes st,neg-edge
      - st,pin-ckin becomes st,use-ckin

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:56 +02:00
Patrice Chotard
e4995e61c9 ARM: dts: stm32: Update sdmmc binding for stm32h743i-eval
Update some sdmmc properties which have been updated with
v4.19 DT bindings:
      - st,dirpol becomes st,sig-dir
      - st,negedge becomes st,neg-edge
      - st,pin-ckin becomes st,use-ckin

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:52 +02:00
Patrice Chotard
60121266c9 ARM: dts: stm32: Restore old usart1 clock bindings for stm32f7
As U-boot stm32f clock driver doesn't support new
bindings for auxiliary clocks (clocks = <&rcc 1 ....>),
restore old bindings for usart1 to get console output.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:21 +02:00
Patrice Chotard
13ba6d0e6f ARM: dts: stm32: Sync DT with v4.20 kernel for stm32h7
Synchronize stm32h7 device tree with kernel v4.20.
U-boot DT files and pinctrl bindings are updated,
useless nodes are removed and gpio compatible added.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:17 +02:00
Patrice Chotard
1056303148 ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7
In order to prepare and ease future DT synchronization with kernel
DT, migrate all U-boot specific nodes/properties/addons to
U-boot DT files.

As sdmmc is not yet supported on kernel side, sdmmc nodes
are located in eval-u-boot and disco-u-boot DT files.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:11 +02:00
Patrice Chotard
fe63d3cfb7 ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7
Synchronize stm32f7 device tree with kernel v4.20.

All pinctrl bindings are updated.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:06 +02:00
Patrice Chotard
01aabf97d1 ARM: dts: stm32: Migrate U-boot nodes to U-boot DT files for stm32f7
In order to prepare and ease future DT synchronization with kernel
DT, migrate all U-boot specific nodes/properties/addons to
U-boot DT files.

Migrate also DT nodes which are not yet available on kernel DT side
as ethernet, ltdc and qspi nodes.

Fix ethernet_mii pins and add missing qspi_pins for stm32746g-eval

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:01 +02:00
Patrice Chotard
71dfd5f3f5 ARM: dts: stm32: Sync DT files with v4.20 kernel for stm32f4
Synchronize stm32f7 device tree with kernel v4.20.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:30:57 +02:00
Patrice Chotard
933f84cab9 ARM:dts: stm32: sort nodes by alphabetical order in f4 u-boot files
Sort nodes alphabetically to be coherent with all others STM32 DT files.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:30:52 +02:00
Neil Armstrong
f9e605437e ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1
Import Linux 5.1-rc1 DT from 9e98c678c2d6 ("Linux 5.1-rc1") for the
meson-g12a-u200 board, the meson-g12a.dtsi and the corresponding bindings.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
17b7efe25b ARM: meson: add G12a support
Add support for the Amlogic G12A SoC, which is a mix between the
new physical memory mapping of AXG and the functionnalities of
the previous Amlogic GXL/GXM SoCs.

To handle the internal ethernet PHY, the Amlogic G12A SoCs now
embeds a dedicated PLL to feed the internal PHY.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
912af8423f clk: meson: add g12a support
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Philippe Reynes
7526582441 dt: bcm6858: add led controller
Add the led controller in the bcm6858 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 18:13:24 -04:00
Ibai Erkiaga
98ffbb78e1 arm: arm64 32bit address relocation
Current relocation code is limited to 21bit PC-relative addressing
which might not be enough for bigger code sizes. The following patch
increases the addressing to 32bit PC-relative. This feature is
specially interesting if U-Boot is build without optimiation (-O0) as
the text section is increased significativelly.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
2019-04-22 18:13:24 -04:00
Ibai Erkiaga
1721b82c1f arm: fix hvc call
HVC call makes use of 6 mandatory arguments rather than 7 in the same way
as SMC calls. The 7th argument is optional (Client ID) for both HVC and
SMC but is implemented as 16-bit parameter and register R7 or W7. The aim
of this patch is just fix compilation error due to an invalid asm code in
the HVC call so that's why the 7th argument is removed.

The issue does not report any error in a normal build as hvc_call is not
used at all and is optimized by the compiler. Using -O0 triggers the
error so the patch is intended to fix issues on a ongoing effor to build
U-Boot with -O0.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
2019-04-22 18:13:22 -04:00
Ang, Chee Hong
fd50eac910 ARMv8: Disable fwcall when PSCI is enabled
When PSCI is enabled, we are expecting U-Boot which now act
as EL3 software will handle all the PSCI calls. We won't need
fwcall as no further HVC or SMC are needed.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-04-22 18:13:21 -04:00
Chee Hong Ang
f6b0115a96 ARMv8: Allow SiP service extensions on top of PSCI code
Allow PSCI layer to handle any SiP service functions added by
platform vendors. PSCI layer will look for SiP service function
in the SiP function table located in '._secure_svc_tbl_entries'
section if the SMC function identifier is not found in the PSCI
standard functions table. Use DECLARE_SECURE_SVC macro to declare
and add platform specific SiP service function.
This new section '._secure_svc_tbl_entries' is located next to
'._secure.text' section. Refer to arch/arm/cpu/armv8/u-boot.lds.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2019-04-22 18:13:21 -04:00
Philippe Reynes
b2aa518a62 dt: bcm963158: enable nand controller
Enable the nand controller in the device tree
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 12:06:39 -04:00
Philippe Reynes
6242e9a82a dt: bcm63158: add nand controller
Add the nand controller in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 12:06:38 -04:00
Philippe Reynes
2463ad34b0 dt: bcm968580xref: enable nand controller
Enable the nand controller in the device tree
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 12:06:38 -04:00
Philippe Reynes
24e27a180a dt: bcm6858: add nand controller
Add the nand controller in the bcm6858 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 12:06:30 -04:00
Philippe Reynes
6478848d16 arm: asm: io.h: define readX_relaxed and writeX_relaxed
This patch port the function readX_relaxed and
writeX_relaxed from kernel 4.18.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 11:55:58 -04:00
Tom Rini
8a94262435 Second set of u-boot-atmel features and fixes for 2019.07 cycle
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcvW07AAoJEB6zHgIOrC/Iu4QH/1REDOTrsZPydd2yD/O81vPs
 RiLC8wP2J4UmqtMcNTLyvxlYwrzqoR5J6SYdyBNU/+cLEp/gdzEI+rjsfSV2uRX1
 Qb4Pk2FiI503JVjegxsbJqzASfiEP7rIg3HM5431xbhYH22MW2FH6le6yrtNxjBh
 m1WFjQYX1bpbGb6zue8TgyLIeN1IqWuqnH9kUHixUEan+xrpEhN239LDFjdvGbvC
 BvYyMtDddmMt4YDzNjgX36us993kylGZp6JijR3zgUao7I/JGVZAJrxw8MHDTnVy
 UKv3VI9F5bGLSvzqTVL2MFU6XtJW26v+niGLhGzlUhb3TTKrdKOicm3VF7tO+JU=
 =MamK
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2019.07-b' of git://git.denx.de/u-boot-atmel

Second set of u-boot-atmel features and fixes for 2019.07 cycle
2019-04-22 10:28:21 -04:00
Tom Rini
6c5f8dd540 Merge branch 'master' of git://git.denx.de/u-boot-usb
- Various fastboot, dwc2/stm32 updates
2019-04-21 19:00:04 -04:00
Tom Rini
b4fde1633e Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Various stratix10, gen5 updates
2019-04-21 18:59:30 -04:00
Patrick Delaunay
6fe7dd3327 stm32mp1: add stusb1600 support for DK1 and DK2 board
The DK1 and DK2 boards use the USB Type-C controller STUSB1600.
This patch updates:
- the device tree to add the I2C node in the DT
- the board stm32mp1 to probe this I2C device and use this controller
  to check cable detection.
- the DWC2 driver to support a new dt property
  "u-boot,force-b-session-valid" which forces B session and
  device mode; it is a workaround because the VBUS sensing and
  ID detection isn't available with stusb1600.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21 10:26:52 +02:00
Patrick Delaunay
c31000c534 stm32mp1: migrate USBOTG device to driver model
Use the DWC2 device driver with DM_USB_GADGET support and
cleanup the USB support in STM32MP1 board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:52 +02:00
Patrick Delaunay
c50151d43f phy: usbphyc: Binding update of vdda supply
Move supply vdda1v1 and vdda1v8 in usbphyc node and
no more in port

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Clément Péron
517ee64205 arm: dts: h6: Add Beelink GS1 initial support
Beelink GS1 is an Allwinner H6 based TV box,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 2GB LPDDR3 RAM
- 16GB eMMC
- AXP805 PMIC
- 1Gbps GMAC via RTL8211E
- USB 2.0 and 3.0 Host
- HDMI port
- S/PDIF port
- 5V/2A DC power supply
- Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)

Linux commit details about the sun50i-h6-beelink-gs1.dts sync:
"arm64: dts: allwinner: h6: Introduce Beelink GS1 board"
(sha1: 089bee8dd119ba084dee6b17a2e1a53df4f30193)

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-18 22:14:34 +05:30
Razvan Stefanescu
fe5963d63e ARM: dts: at91-sama5d2-icp: Add MACB node
MACB has a fixed link connection to KSZ8563 switch port.

Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com>
2019-04-18 09:43:22 +03:00
Eugen Hristev
f085452d85 board: atmel: add SAMA5D2 ICP board
The SAMA5D2 ICP Board features the SAMA5D27 SoC,
together with QSPI Flash, Wilc3000 wireless device and
EtherCat support.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-18 09:43:22 +03:00
Ley Foon Tan
2c494e62c3 arm: dts: Stratix10: Add QSPI node
Merge qspi dts node from Linux.
Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)

Add -u-boot.dtsi files for non Linux dts properties and
update properties for Uboot.
- add u-boot,dm-pre-reloc
- add alias for spi0
- change compatible for flash
- support quad read and quad write
- change maximum frequency to 100MHz

Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17 22:20:17 +02:00
Ley Foon Tan
456d45261b ddr: altera: Stratix10: Add ECC memory scrubbing
Scrub memory content if ECC is enabled and it is not
from warm reset boot.

Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17 22:20:17 +02:00
Ley Foon Tan
8ab9daabe5 arm: socfpga: stratix10: Add cpu_has_been_warmreset()
Add helper function cpu_has_been_warmreset() to check
if CPU is from warm reset boot.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17 22:20:17 +02:00
Ley Foon Tan
62e6278d1e arm: dts: Stratix10: Modify stratix10 socdk memory node
The stratix10 socdk ships with 4GB of memory.  Modify the
device tree to represent this.  Note that to access 4GB of
memory in Stratix 10, due to the IO space from 2GB to 4GB,
we use the fact that the DDR controller ignores upper address
bits outside of the configured DRAM's size.  This means that
, the 4GB DRAM is mapped to memory every 4GB.

For an 8GB memory, you can either live with the 2GB IO space,
and loose access to that memory from the processor, or use
the same trick:

Loose 2GB of memory:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* last 4GB */
                      <1 0x00000000 1 0x00000000>;
                u-boot,dm-pre-reloc;
        };

or to map it all:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* next 6GB */
                      <2 0x80000000 1 0x80000000>;
                u-boot,dm-pre-reloc;
        };

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17 22:20:17 +02:00
Ley Foon Tan
b6f7ee5d1f ddr: altera: stratix10: Move SDRAM size check to SDRAM driver
Move SDRAM size check to SDRAM driver. sdram_calculate_size()
is called in SDRAM initialization already, avoid calling
twice in size check function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17 22:20:17 +02:00
Simon Goldschmidt
c5de2b7eae arm: socfpga: implement proper peripheral reset
This commit removes ad-hoc reset handling for peripheral resets from SPL
for socfpga gen5.

This is done because as U-Boot drivers support reset handling by now.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:17 +02:00
Simon Goldschmidt
29873c74f3 arm: socfpga: move gen5 SDR driver to DM
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.

This gets us rid of one ad-hoc call to socfpga_per_reset().

The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.

SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:16 +02:00
Simon Goldschmidt
7357c2cbc0 arm: socfpga: gen5: add reset & sdr node to SPL devicetrees
The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.

In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.

This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:16 +02:00
Simon Goldschmidt
42a37d9774 arm: socfpga: gen5: sync devicetrees to Linux
This is again a sync to linux-next + pending patches in Dinh's tree at
commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset
properties")'

It adds missing peripheral reset properties to socfpga.dtsi and removes
U-Boot specific leftovers from socfpga_cyclone5_socrates.dts.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:15 +02:00
Uri Mashiach
ecb76eff56 arm: am57xx: cl-som-am57x: remove board support
U-Boot support for the CL-SOM-AM57x module is no longer required.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2019-04-17 09:20:26 -04:00
Tom Rini
4b37f36d68 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Convert DM_MMC and DM_SCSI
- A20, R40, H6 Linux dts(i) sync
- CLK, RESET support for sunxi, sun8_emac net drivers
2019-04-17 09:19:45 -04:00
Tom Rini
14b8c420b8 Xilinx/FPGA changes for v2019.07
fpga:
 - Add support for external data in FIT
 - Extend testing for external data case
 - Inform user about a need to run post config on Zynq
 
 arm:
 - Tune zynq command functions
 - Fix internal variable setting
 
 arm64:
 - Add support for zc39dr decoding
 - Disable WDT for zcu100
 - Small changes in reset_reason()
 - Some DT changes (spi)
 - Tune qspi-mini configuration
 - Remove useless eeprom setting
 - Fix two sdhci boot case
 
 spi:
 - Fix tap delay programming
 
 clk:
 - Enable i2c in SPL
 
 net:
 - Fix gem phydev handling
 - Remove phy detection code from gem driver
 
 general:
 - Correct EXT_DTB usage for MULTI_DTB_FIT configuration
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAly262oACgkQykllyylKDCH44gCbBnuxUH6ZF0B7Leuee4te7C59
 LmUAn14/bbtMt17zkMSADCjY9yGWF4au
 =mWrW
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblaze

Xilinx/FPGA changes for v2019.07

fpga:
- Add support for external data in FIT
- Extend testing for external data case
- Inform user about a need to run post config on Zynq

arm:
- Tune zynq command functions
- Fix internal variable setting

arm64:
- Add support for zc39dr decoding
- Disable WDT for zcu100
- Small changes in reset_reason()
- Some DT changes (spi)
- Tune qspi-mini configuration
- Remove useless eeprom setting
- Fix two sdhci boot case

spi:
- Fix tap delay programming

clk:
- Enable i2c in SPL

net:
- Fix gem phydev handling
- Remove phy detection code from gem driver

general:
- Correct EXT_DTB usage for MULTI_DTB_FIT configuration
2019-04-17 09:19:13 -04:00
Tom Rini
88d5ab3d67 UniPhier SoC updates for v2019.07
- Sync DT with Linux 5.1-rc4
 
 - Enable CONFIG_SUPPORT_EMMC_RPMB for uniphier_v8_defconfig
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJctlk9AAoJED2LAQed4NsGsBoP/0wXmetq2UKCn+4qWy3+2ItR
 M8hspsdpIclFTcG7D8kxeCWgMv0SH6hFbRgEo8gfnHX/kWCXnklgVc7q2rEWIk53
 0Dze8Zopr0YULhx8Esuq1viS/WVz1qPVK0cnqJc4QgBbXxLWxc9xC1WUV61G0ls2
 3oHGLbEJTtTE2cbEIJaRIu1pfravN4RoJtsiO+Gum1LEtoyQ/h7g/5f/equwJ0q3
 QwbvASuXOyoyhypcjA97PAQZru54e8cqFd1VwRJNJMryjkOOk7Tq+z77WwtFiv7G
 heDy0P0b/ykxoasUMwPOOkC7/uVjeh6lsoOqiJejQan7bcYEWPsWRPflZeFVFTIS
 ptfir+LCNaBdUddVP7IcNaRRrho11zyvhOcHLb+df7dI7UNytux9YA0CIOlgFNmZ
 /lIxKlCfXKEft20XHTxIfSoPPrlmmKzk1zyvv8+rZLsMW0yBIQkLUoXKcZL+dmSG
 3U8DrCNZlc4xHVEh69dntqHZ2+5TtpKV3KEBnEOHAwlqSdP6K0sU0no1hZ4H0gkU
 xylEihbMxwGljIAQt3VBiGb+UDlvZKvADyZDKnRt1OSO65Z3z1Vt2W4ziSrcWCTC
 bloy6jiOxaRkbXeEQSmjKfmOr3DpagyUuESjTKLFhYeFLl9dqMURh4C0FtP3M50d
 R6ivoyBE6BLnK8gOz9JL
 =YEOC
 -----END PGP SIGNATURE-----

Merge tag 'uniphier-v2019.07' of git://git.denx.de/u-boot-uniphier

UniPhier SoC updates for v2019.07

- Sync DT with Linux 5.1-rc4

- Enable CONFIG_SUPPORT_EMMC_RPMB for uniphier_v8_defconfig
2019-04-17 09:16:38 -04:00
Jagan Teki
bb3362b0ca arm: sunxi: Enable DM_MMC and DM_SCSI
- Enable DM_MMC if MMC defined
- Enable DM_SCSI if SCSI defined

globally through Allwinner platform, the effected SoC families
and boards will make use of MMC and SCSI subsystems in driver-model.

Tested DM_MMC in one board from A64, H6, H5, H3, R40, A83T, A20, A10
SoCs.

Tested-by: Pablo Sebastián Greco <pgreco@centosproject.org> # BPI-M2-Ultra
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Jagan Teki
6c90036f7b ARM: dts: sun8i-r40-bananapi-m2-berry: Enable AHCI
Enable ahci node for BPI-M2-Berry, this would require since
we have DM_SCSI enabled on the respective SoC.

Unable to sync the same node from Linux, since the similar change
is still in Linux ML.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Jagan Teki
36b53ab24e ARM: dts: a20-wits-pro-a20-dkt: Enable AHCI
Enable ahci node for a20-wits-pro-a20-dkt, this would require since
we have DM_SCSI enabled on the respective SoC.

Right now, ahci enabled in -u-boot.dtsi and will remove once same
supported by Linux.

Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Jagan Teki
328c5f09c9 ARM: dts: a20-m5: Enable AHCI
Enable ahci node for sun7i-a20-m5.dts, this would require since
we have DM_SCSI enabled on the respective SoC.

No need to send patch to Linux for this change, since this
dts is U-Boot specific.

Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Jagan Teki
0cc47a8ead arm: allwinner: dts: a20: Sync A20 dts(i) files from Linux 5.1-rc2
Sync sun7i-a20 dts(i) files from Linux 5.1-rc2

Linux commit details about the sun7i-a20* sync:
"ARM: dts: sun7i: bananapi: Add GPIO banks regulators"
(sha1: 09c6572290f018d73ec2e812e28bada34d41815f)

Here are U-Boot specific dts changes.

- s/uart0_pins_a/uart0_pb_pins for
  sun7i-a20-ainol-aw1.dts
  sun7i-a20-m5.dts
  sun7i-a20-primo73.dts
  sun7i-a20-yones-toptech-bd1078.dts
  sunxi-itead-core-common.dtsi
- s/gmac_pins_mii_a/gmac_rgmii_pins for
  sun7i-a20-m5.dts
- drop i2c0, i2c1 pins from
  sunxi-itead-core-common.dtsi
- drop mmc0 pins from
  sun7i-a20-primo73.dts

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Jagan Teki
3705d4965f arm: allwinner: r40: Sync R40 dts(i) files from Linux 5.1-rc2
Sync sun8i-r40 dts(i) files from Linux 5.1-rc2

Linux commit details about the sun8i-r40* sync:
"ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node"
(sha1: 1e5f1db4ccd8348a21da55bff82f4263000879ef)

Linux commit details about the sun8i-v40* sync:
"ARM: dts: sunxi: Fix I2C bus warnings"
(sha1: 0729b4af5753b65aa031f58c435da53dbbf56d19)

Cc: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Masahiro Yamada
cd33feda6b ARM: dts: uniphier: sync with Linux 5.1-rc4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-04-17 07:22:23 +09:00
Luca Ceresoli
350cfe79a8 arm64: zynqmp: fix preprocessor check for SPL_ZYNQMP_TWO_SDHCI
A missing CONFIG_ prefix while checking for this Kconfig variable makes the
check always fail. Fix it. While there also switch from the '#if defined'
form to the '#ifdef' form as the other checks in this function.

Fixes: 35e2b92344 ("arm64: zynqmp: Fix logic around CONFIG_ZYNQ_SDHCI")

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:52:02 +02:00
Siva Durga Prasad Paladugu
3b4146f133 arm64: zynqmp: Define label for flash node
Define a label for flash node so that it can be
referenced easily as required.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:51:34 +02:00
Siva Durga Prasad Paladugu
8bc8991f22 arm64: zynqmp: Add spi-flash compatible string to flash node
spi-flash compatible string is needed for reading tx and rx bus
widths, hence add this compatible string to flash node.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:51:34 +02:00
Michal Simek
ba4f52bd42 arm64: zynqmp: Add debug message about clearing BSS
Just have better view on system.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:51:34 +02:00
Heiko Schocher
ac578e08b1 at91sam9260.dtsi: add some labels
add labels to rtc, pinctrl and watchdog node.

This makes it possible to reference the nodes
from board dts files.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-04-15 17:18:59 +03:00
Tom Rini
75ce8c938d Move to DM
-----------
 
 - DM support in sata
 - Toradex Board to DM
 - wandboard to DM
 - tbs2910 to DM
 - GE boards to DM
 - VHybrid boards to DM
 - DM_VIDEO for i.MX
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAly0NhIPHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et3XiUMALq2W4HPjFlDaVHpaxKIvZMkqAAjF7eE6M9l
 DWivSm/Anm5jeE2UM80FpV7npdkPMcOl2YdcIjg+jMKKP6DI+4N6gEhWvxX9mEoC
 RmR2nxGC/GIc0Blb4HU9V6xMkeR5jSAQ6bxZmX3IrnG6u67BIi4NmkNrT9gdQ+WT
 PkJf2Ai7DN7+epfOzjO0d/LjS3hAVb+nesHuxoVraElwc5sEMAnoD0vIMUrXceZ2
 +V6WiU1i9jeLj3fA8P+4o6wqQpxFLlJiuC0FUNKQH/kWIqX6MGrr9ElseLUV0O+Z
 LL5nqsuTgG/fAol1r71De49fiML2Pfx7ZkAZOJ1NMUOXUKw25ulO/wi0wg8t+l2Z
 2oAQ3S84RUVYX4MFLwxkBCq3uC9hvyCfWF1GmVLV6xSEulS6PnHx0FL6OTY4uB3h
 bmVs/mutwwqYBaaoqGG4sG5L7TVSG/JxNgTVNh3Aqj5a89Fd9us+nBhLhoq6xyVl
 cEf+/gPGQ97JEj9DolAPFIFQJBvL7g==
 =KLsH
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190415' of git://git.denx.de/u-boot-imx

Move to DM
-----------

- DM support in sata
- Toradex Board to DM
- wandboard to DM
- tbs2910 to DM
- GE boards to DM
- VHybrid boards to DM
- DM_VIDEO for i.MX
2019-04-15 07:31:14 -04:00
Tom Rini
38f94d3539 Pull request for UEFI sub-system for v2019.07-rc1 (2)
In the aarch64 crash dump information about the loaded EFI images is added.
 
 In README.uefi the development target is for the UEFI subsystem is
 described as "Embedded Base Boot Requirements (EBBR) Specification"
 compliance.
 
 Several bug fixes are supplied.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAlyyzHEACgkQxIHbvCwF
 GsS+9Q/9HahVvxHFljI8ymxznml7AlFCrxWwcVo5HhftbGuQIgF3NMXRlsxmsSPM
 Z+Cc3EFni4EWWWe9yDMLqXV4NCd6bnfWYWP4UvbqAKCfeX8jScRyMypPnxZ3rNrg
 oe/8zDT9qXQnEah4sB+AQhar2VRTS1p97wKDObt3mj9c2g5pGL1zdejS/4SfnCd0
 a1BymV7p7fpykDjW8S0GQM56QAkbB9CJ4Q7nlPCDlspqJlQB318lWs46FfUn2Aue
 DNLm0uscrMZtEr/aAdT+r/96GIq4AVkexy7b5MZ0v/NDNAtmIqO1ORUmLSNSDfcM
 /cbtxq53VbeztMzMoYDdU0zNR//N4dL3GbSRKJulksvxeIExCp3dRV7gfTOwWq7J
 Lg/b43WJI1f2vgXDgEPddTO3E3SPjCGQcnCNOcVNNfTkyrtVaCmRYh69lV2BpKKF
 oQCYQyzS8yYLxj16YXixK9seyQYxh/vPYVT78ed5A8B1dmyxSQMnEJjY93jngj1g
 k5DRH9nnx12aeEqkhsWvVdHT0OBNj/+oZlzT3KGDcxhrDeZXAgqxAO1oPG85Wqnx
 kPeadyVD0T5Dd8fpMqF+tToB+GCbvyUVJsVlNqDSC7NslJ3AbxBKNDuEsMJlXgwL
 Yh4/lusg/YXzZ4ACWHgUnckZDVZGNj+58QRgEU+3mZinMjDS38E=
 =QdJl
 -----END PGP SIGNATURE-----

Merge tag 'efi-2019-07-rc1-2' of git://git.denx.de/u-boot-efi

Pull request for UEFI sub-system for v2019.07-rc1 (2)

In the aarch64 crash dump information about the loaded EFI images is added.

In README.uefi the development target is for the UEFI subsystem is
described as "Embedded Base Boot Requirements (EBBR) Specification"
compliance.

Several bug fixes are supplied.
2019-04-15 07:30:25 -04:00
Jagan Teki
a93a55044b arm64: allwinner: sun50i: Sync H6 dts(i) files from Linux
Usually the Linux dts changes were synced in specific tags in Allwinner,
to keep track for whats been synced so-far and plan for future syncs.

But this patch sync sun50i-h6* dts(i) files from Linux w/o any specific
tag since these dts(i) changes are required for new H6 boards support.

Linux commit details about the sun50i-h6* sync:
"arm64: dts: allwinner: h6: move MMC pinctrl to dtsi"
(sha1: 6ba2e45d57afdfd982d12f168edd6a79a65075d8)

Linux commit details about the sun8i-tcon-top.h sync:
"dt-bindings: display: sunxi-drm: Add TCON TOP description"
(sha1: 59a9c39544cd1e5952c2a33028d71aa8180648f8)

Part of the sync initiated by 'Clément Péron'.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-14 22:32:32 +05:30
Tom Rini
216800acf1 Merge branch 'master' of git://git.denx.de/u-boot-spi
Conflicts:
	arch/arm/dts/armada-385-amc.dts
	arch/arm/dts/armada-xp-theadorable.dts
	arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-14 00:03:06 -04:00
Anatolij Gustschin
275e8b622f imx6: dts: add wandboard dtb target to fix build error
Fix broken build:
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:10 +02:00
Anatolij Gustschin
7092e93569 imx6: tbs2910: fix dtb build error
Fix broken build:
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:10 +02:00
Marcel Ziswiler
dee535bc90 apalis/colibri_imx6: add device trees to makefile
Add device trees to Makefile to avoid newly introduced error:

Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument

make[1]: *** [dts/Makefile:28: arch/arm/dts/imx6-apalis.dtb] Error 1
make: *** [Makefile:1009: dts/dt.dtb] Error 2

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:10 +02:00
Stefan Agner
2588bf1edc arm: vf610: add uart2 clock/pinmux support
Add support for Vybrid's UART2 (Colibri UART_B).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:09 +02:00
Marcel Ziswiler
1854a9c916 ARM: dts: colibri_vf: update device trees
Update device tree in preparation of further driver model migration:
Ethernet FEC, ESDHC aka MMC/SD card, I2C, NFC aka NAND flash controller,
USBH_PEN GPIO regulator.

Add iomux resp. pinctrl entries to be removed from proprietary platform
data: DSPI, ESDHC, FEC, I2C, NFC, UART, USBH_PEN GPIO.

Introduce a U-Boot specific device tree with some required
u-boot,dm-pre-reloc properties: soc, aips0, pinctrl_ddr and uart0 incl.
pinctrl.

While at it also update the MAINTAINERS file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:09 +02:00
Marcel Ziswiler
37822a6ca1 imx: bootaux: add dependency on vf610
Allow using bootaux also on VF610 aka Vybrid.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-13 20:30:09 +02:00
Marcel Ziswiler
872fc0d8ac vf610: ddrmc: add missing include
The DDR memory controller include file for the Vybrid uses
iomux_v3_cfg_t without actually including iomux-vf610.h.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-13 20:30:09 +02:00
Anatolij Gustschin
ec837c82d7 imx6: wandboard: convert to DM_PMIC
Enable DM_PMIC_PFUZE100 driver and add PMIC description to DTS.
Rework power_init_board() code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:09 +02:00
Anatolij Gustschin
4f115e3b9b imx6: wandboard: add device tree
Add device trees from Linux in preparation for driver model
conversions.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:09 +02:00
Anatolij Gustschin
f45ec8fcfb imx6: dts: add 'u-boot, dm-pre-reloc' to soc and ipu nodes
u-boot,dm-pre-reloc is required for reserving video memory
when binding DM_VIDEO driver.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:09 +02:00
Anatolij Gustschin
57f065fee2 video: ipuv3: add DM_VIDEO support
Extend the driver to build with DM_VIDEO enabled. DTS files
must additionally include 'u-boot,dm-pre-reloc' property in
soc and ipu nodes to enable driver binding to ipu device.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-04-13 20:30:09 +02:00
Soeren Moch
b184dc077a board: tbs2910: Add device tree
... as preparation for additional driver model coonversions.

We use CONFIG_OF_EMBED here to keep u-boot.imx as final binary name. So we
maintain compatibility with the original TBS u-boot and available HOWTOs
for u-boot updates.

Signed-off-by: Soeren Moch <smoch@web.de>
2019-04-13 20:30:09 +02:00
Marcel Ziswiler
50f39bb6f2 colibri_imx6: migrate to using device tree
Migrate to using device tree required for further driver model
integration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:09 +02:00
Marcel Ziswiler
4df0292359 apalis_imx6: migrate to using device tree
Migrate to using device tree required for further driver model
integration.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:08 +02:00
Ian Ray
31c9afdd92 board: ge: ppd: Enable CONFIG_DM_MMC
Use MMC device model, and remove USDHC pin configuration code since the
pinctrl driver is used.

Signed-off-by: Ian Ray <ian.ray@ge.com>
2019-04-13 20:30:08 +02:00
Ian Ray
3cc0e327f2 arm: imx: Add esdhc3/4 nodes to imx53.dtsi
These nodes are required by mx53ppd when built with CONFIG_DM_MMC=y.
They are copied from Linux 4.20.5.

Signed-off-by: Ian Ray <ian.ray@ge.com>
2019-04-13 20:30:08 +02:00
Ian Ray
bcce411baf board: ge: ppd: Enable CONFIG_DM
Add simplified, generalised, ppd device tree and enable CONFIG_DM.

Signed-off-by: Ian Ray <ian.ray@ge.com>
2019-04-13 20:30:08 +02:00
Ian Ray
8d8d3540eb board: ge: bx50v3: Enable CONFIG_DM_SPI, CONFIG_DM_SPI_FLASH
Use SPI flash device model, and remove SPI pin configuration code since
the pinctrl driver is used.

Signed-off-by: Ian Ray <ian.ray@ge.com>
2019-04-13 20:30:08 +02:00
Ian Ray
efc260a9af board: ge: bx50v3: Enable CONFIG_DM_MMC
Use MMC device model, and remove USDHC pin configuration code since the
pinctrl driver is used.

Signed-off-by: Ian Ray <ian.ray@ge.com>
2019-04-13 20:30:08 +02:00
Ian Ray
d93e3ba6e3 board: ge: bx50v3: Enable CONFIG_DM
Add simplified, generalised, bx50v3 device tree and enable CONFIG_DM.

Signed-off-by: Ian Ray <ian.ray@ge.com>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
e5b345f30c pcm052: bk4: sdcard: Add support for SD card booting/recovery
This code allows reusing the default u-boot as in the late board init, the
default envs are restored and proper recovery scripts executed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
4c414ed361 ARM: DTS: Provide vf610-bk4r1-u-boot.dtsi for U-Boot specific properties
This commit brings a separate file in which the U-Boot specific
properties (like 'dm-pre-reloc') are provided.

Such approach allows easy sync with upstream Linux kernel in the
future.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
e78f9fd2eb ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052)
This commit provides update and renames the bk4r1.dts to vf610-bk4r1.dts
file with more on SoC HW description.
The pcm052.dts has been renamed to vf610-pcm052.dts as well.

Moreover, a new vf610-pcm052.drsi file has been introduced
to reuse the common code between devices based on Phytec's
pcm052 modules.
Ported from Linux kernel - v4.20 (tag)

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
8b47abd2e2 ARM: DTS: vybrid: Update vf.dtsi file to descibe more vf610 hardware
This patch allows moving vf610 based boards to a device tree and model.
Ported from Linux kernel - v4.20 (tag)

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
a01cc0ac62 vybrid: Define the imx_get_mac_from_fuse() as a __weak function
The proposed way of reading fused MAC in the imx_get_mac_from_fuse() may
be different for other boards.

This commit defines the imx_get_mac_from_fuse() as a weak function to allow
board file overriding it with customized function.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
7db8b854d3 vybrid: clock: Provide enable_i2c_clk() function for Vybrid
Provide function to enable I2C clocks for vf610 - in the generic code.
This function overrides the default weak function implementation (which
only returns 1).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-04-13 20:30:08 +02:00
Lukasz Majewski
da6b81a8d8 vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions
This patch provides definitions necessary for VF610 DDR pad configurations.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-04-13 20:30:08 +02:00
Tom Rini
0a5228be86 - mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
 - mscc: small fixes, add network support for JR2 and ServalT SoCs
 - bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
 - MIPS: fix redundant relocation of initrd images
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAlywtKQACgkQKPlOlyTy
 XBgYbBAAlRLhN52f2vv9Hng/tfCAuZk7c9tJ+b/5i36ZoJNozeaiOBgwVl3eeEa9
 v4SeKz4J+9FJLOSZkIPrCvX+HaACQn7Pqw/64h3JE8TEzfU5lgmV4Xk2dcXtkmEL
 L5PTQoNMZDgQaeltLtN29yIW5lVxx0NUN9O0FLY5+R/ptXlCFaAGdgSuXH36boDR
 /cvfLlaZPM/hA7l3wRUjWa17L8MNEon4+cqLkzDyTTihdHOdZA4P1O7ce/XffGQp
 BAiSta4EztB1xs0oTAOEmUJp1v8Ae7yRuFoZaCp+Dgq+0WOTbxDW4J57fTaphES1
 su3yoYjju+M/dUb/sWmOQNjeIchJPYWcpiOl9E8jQ/l2SaBJ6Oxmg7PxC3Ww0X2z
 JdF6mcKeaDH3WYO20FeC6xb9Q9FN2yX4rcW/Yg46TdeJ3T2sj8A19ZCHoeAQRl0I
 68SbAaDJw/K3fTBFPd9VyQQQawPbyhmpdQAOWtixNWBFIBbZpqI4o1DMJKJRoxqd
 Ail++ysLUICB0XXg0rGI+dFusjcu9AAeRODc11dtGa0YBh2Y28JrJ4OuV14GYQhe
 5J8BquRaDADA3iK/+3C6TUSQGhb5pFXTcsdNBC9zBPb/ePeMDfZxBcB2vCOnZDZ1
 m0kR5qnsz4IH8/rCmJ5wmMBh6JuyPoCSdiTVuuU5CuCVGYbmJuE=
 =NrV8
 -----END PGP SIGNATURE-----

Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mips

- mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
2019-04-13 08:27:26 -04:00
Heinrich Schuchardt
bba8165690 arm: print information about loaded UEFI images
If an exception occurs in a UEFI loaded image we need the start address of
the image to determine the relocation offset.

This patch adds the necessary lines after the registers in the crash dump
for armv8. A possible output would be:

UEFI image [0x00000000bffe6000:0x00000000bffe631f] pc=0x138 '/\snp.efi'

With the offset 0x138 we can now find the relevant instruction in the
disassembled 'snp.efi' binary.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-04-12 22:00:42 +02:00
Tom Rini
015289580f stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
 - stm32mp1 dts files sync'ed with Linux version
 - add STM32MP1 Discovery boards (DK1 and DK2)
 - add STMFX gpio expander driver
 - misc improvement for stm3mp1 supports
 - rename stpmu1 to stpmic1 (official name)
 - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
 - add STM32 FMC2 NAND flash controller driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcsLHKAAoJEOKyvdngqpN1iwsH/3HtFxWsIcmT8TfHgIi2USKx
 /Rpj5Mdl0Q0584LAxZXkR2m9YvzBU6n2tR/n9wQfRyiazoEps1LXMmYcZVy35mQg
 AjTNV7xWfC1EZFP0+Gvn5PFquMPoZoIeqbDy1Jk91Qr4CHIqqS64DBwlTmQfjLzf
 6vfoyBcheL5Rf/AGM5AaHMjwh1GZs89cBCeVjGVMUAPgbfFUAKBWwi2fqdgEbDD7
 b9owLl2IykLTHOhvfnZi5NeRoA39deuNB0vSfU4WcMcONhekFCfOPi3Hch5aM/os
 xXlAXkTqps8rVfYHvUUmHm/wJhk+HH69wMThAWNFev/3g94MWR5zen5rjIOBVGg=
 =9M63
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-boot

stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
- stm32mp1 dts files sync'ed with Linux version
- add STM32MP1 Discovery boards (DK1 and DK2)
- add STMFX gpio expander driver
- misc improvement for stm3mp1 supports
- rename stpmu1 to stpmic1 (official name)
- stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
- add STM32 FMC2 NAND flash controller driver
2019-04-12 15:43:19 -04:00
Tom Rini
dd758c6720 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2019-04-12 15:43:08 -04:00
Tom Rini
683754f0aa Merge branch 'master' of git://git.denx.de/u-boot-i2c 2019-04-12 15:43:04 -04:00
Tom Rini
066cc7c6cf Merge git://git.denx.de/u-boot-marvell
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
  board support (Chris)
2019-04-12 15:42:56 -04:00
Philippe Reynes
1e4a7c69fd dt: bcm963158: enable gpio controller
Enable all the gpio controllers in the device tree
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
938f10b7f6 dt: bcm63158: add gpio controller
Add 8 gpio controllers in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
2629128572 gpio: do not include <asm/arch/gpio.h> on ARCH_BCM63158
As no gpio.h is defined for this architecture, to avoid
a compilation failure, do not include <asm/arch/gpio.h>
for arch bcm63158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
396fff8da2 dt: bcm968580xref: enable gpio controller
Enable all the gpio controllers in the device tree
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
9575c7ebc8 dt: bcm6858: add gpio controller
Add 8 gpio controllers in the bcm6858 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
d96e7ed802 gpio: do not include <asm/arch/gpio.h> on ARCH_BCM6858
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcm6858.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Patrick Delaunay
1258e4667a ARM: dts: Add STMFX gpio expander support for stm32mp157c-ev1
Adds alias to set the pincontrol seq id.
For STMFX gpio expander, force sequence number after
the last bank (GPIOZ) to avoid conflict between STM32MP and STMFX
gpio bank sequence number.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12 16:09:13 +02:00
Patrice Chotard
77457fa94e ARM: dts: stm32mp1: Add adc nodes
Add adc related nodes. These nodes are used to detect the
current supplied by USB type-C power in port on DK1 and DK2
boards.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12 16:09:13 +02:00
Patrice Chotard
2366160eb2 ARM: dts: stm32: Synchronize DT with kernel one
This patch synchronizes U-boot DT with kernel one
This is based on https://patchwork.kernel.org/cover/10797115/

This patch adds initial support of STM32MP157 discovery boards:
  - Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1).
    This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios)
    and 512MB of DDR3. Several connections are available on this boards:
    4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ...

  - Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2).
    This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a)
    and Murata wifi/BT combo is added.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
c8a6668cbd stm32mp1: dts: activate psci-1.0
Updates the stm32mp157c devicetree to bind the U-Boot PSCI driver need for
power off command; TF-A for stm32mp15x supports PSCI 1.0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
c16cc4f689 stm32mp1: add command poweroff
Activate the command poweroff by default for STM32MP1:
- with PCSI from TF-A for trusted boot
- with PMIC sysreset request for basic boot (SYSRESET_POWER)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
42f01aacfd power: rename stpmu1 to official name stpmic1
Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
d46c22b3fd power: stpmu1: rename files to stpmic1
Prepare file modification for kernel alignment and
rename driver to stpmic1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
17f1f9b176 stm32mp1: Replace OTP read by SHADOW read
Replace STM32_BSEC_OTP() by STM32_BSEC_SHADOW() to
increase read performance.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
815bc8bc94 stm32mp1: bsec: shadow all the upper OTP (no secure) during boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
bfe1f08f88 stm32mp1: bsec: use device tree new compatible
Update bsec driver to use the device tree provided by Kernel.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
59a54e37a6 stm32mp1: basic boot: SPL enable access to GPIOZ bank
SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank
(open security).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
8983ba2751 stm32mp1: align serial number on bootrom
Always use upper case for serial number.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
6c09eb9e7e stm32mp1: add some syscon drivers for syscfg and etpzc
Add SYSCON driver for syscfg and etpzc and reorder in alphabetics order

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
9a2ba2838b stm32mp1: support forced boot mode
The boot mode can be forced by key press
or by TAMP register, requested in kernel by syscon-reboot-mode

tamp: tamp@5c00a000 {
	compatible = "simple-bus", "syscon", "simple-mfd";
	reg = <0x5c00a000 0x400>;

	reboot-mode {
		compatible = "syscon-reboot-mode";
		offset = <0x150>; /* reg20 */
		mask = <0xff>;
		mode-normal = <0>;
		mode-fastboot = <0x1>;
		mode-recovery = <0x2>;
		mode-stm32cubeprogrammer = <0x3>;
		mode-ums_mmc0 = <0x10>;
		mode-ums_mmc1 = <0x11>;
		mode-ums_mmc2 = <0x12>;
	};
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
105a5ad614 stm32mp1: spl: hang with trace when DDR init failed
When DDR initialization failed, print error message
and stop the SPL execution.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
b496eec65d stm32mp1: cosmetic: add comment on psci_migrate_info_type return value
Add explaination for the return value of psci_migrate_info_type:
  2 = Trusted OS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
45ccdb6fc7 stm32mp1: cosmetic cleanup Kconfig
Cosmetic cleanup in mach-stm32mp Kconfig
- remove duplicated SPL_DRIVERS_MISC_SUPPORT
- update help for TARGET_STM32MP1
- set value for NR_DRAM_BANKS
- remove one comment as DEBUG_UART is deactivated by default
- include board Kconfig at the end of the file

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
006ea18910 stm32mp1: spl: add spl_display_print
SPL displays the board model from device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
35d568f090 stm32mp1: update print_cpuinfo()
Display CPU part number and package information.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
7f63c1e687 stm32mp1: update boot mode management
- export the function get_bootmode() and reused it in spl code
- manage uart instance by alias (prepare v4.19 binding)
- solve issue on nand instance
- restore console for uart boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
b4ae34b66b stm32mp1: add runtime information in environment
Set board name with the first dts compatible found in DT
code under CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

The result with DEVICE_TREE=stm32mp157c-ev1 is:
    STM32MP> env print
    	board=stm32mp1
    	board_name=stm32mp157c-ev1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
d461f10036 stm32mp1: display board information
Implement checkboard() function to display
- the boot chain used: basic or trusted
- the board compatible in device tree
- the board identifier and revision, saved in OTP59 for ST boards

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
d859c61139 stm32mp1: bsec: access with SMC for trusted boot
As BSEC is secure aware, all register access need to be done
by TF-A for TRUSTED boot chain, when U-Boot is executed in
normal world.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
abf2678f0f stm32mp1: add trusted boot with TF-A
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
  BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32

The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power

The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Faiz Abbas
fddfd9c7b0 ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
2019-04-12 08:05:56 -04:00
Faiz Abbas
2499a04617 ARM: dts: dra7: Change pbias voltage to 3.3V
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.

Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.

[1] http://www.ti.com/lit/pdf/sprui30

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:56 -04:00
Tom Rini
9c4b0131d1 ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option.  Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
2019-04-12 08:05:55 -04:00
Andreas Dannenberg
3e9b9c1ccd armv7R: K3: am654: Trigger panic on DDR init failures
When initializing DDR from R5 SPL trigger U-Boot's panic facility
rather than simply returning from the board init function as there
is little point continuing code execution. Further, as panic implies
a board reset, so using it might potentially allow to recover from
this error in certain cases such as when the init failure was caused
by a temporary glitch of some sorts.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12 08:05:52 -04:00
Lokesh Vutla
a9a84480f4 arm: k3: Add support for updating msmc dt node
Certain parts of msmc sram can be used by DMSC or can be
marked as L3 cache. Since the available size can vary, changing
DT every time the size varies might be painful. So, query this
information using TISCI cmd and fixup the DT for kernel.
Fixing up DT does the following:
- Create a sram node if not available
- update the reg property with available size
- update ranges property
- loop through available sub nodes and delete it if:
	- mentioned size is out if available range
	- subnode represents l3 cache or dmsc usage.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12 08:05:51 -04:00
Lokesh Vutla
6ce424a920 arm: k3: Add a wrapper to get tisci handle
Create a wrapper to get the ti sci handle.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12 08:05:51 -04:00
Adam Ford
f7c1d53605 ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATA
With the memory mapping giving us some more avialable RAM, this
updates the da850-evm-u-boot.dtsi to include the serial port, SPI
and Flash nodes along with some dependent nodes in the SPL dtb.
This also removes the platform data initialization code for the
serial port and SPI Flash.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-12 08:05:49 -04:00
Sjoerd Simons
4512380420 am335x, guardian: Add support for the bosch guardian board
Add support for the Bosch Guardian board.

CPU  : AM335X-GP rev 2.1
Model: Bosch AM335x Guardian
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Felix Brack <fb@ltec.ch>
2019-04-12 08:05:48 -04:00
Sjoerd Simons
f50939647c Add support for the MT41K128M16JT125K memory modules
Add configuration for the MT41K128M16JT125K memory modules as used on the
Bosch Guardian device.

Based on a patch by:
    Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com>

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
[checkpatch.pl cleanup by Martyn Welch]
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-04-12 08:05:48 -04:00
Murali Karicheri
32d858fc4f ARM: dts: k2g-ice: add dt node for netcp
This patch adds dt node for DP83867 phy used on K2G ICE board and
also enable netcp device nodes for the board.

EVM hardware spec recommends to add 0.25 nsec delay in the tx
direction and 2.25 nsec delay in the rx direction for internal
delay in the clock path to be on the safer side.

The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode
1. Unfortunately, the phy data manual disallows this. Add
ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to
enable workaround suggested for this incorrect strap setting. This
ensures proper operation of this PHY.

The dts bindings are kept in sync with that from 4.14.y linux
kernel. This required the pinmux device related bindings to be
commented out to allow for compilation.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:47 -04:00
Murali Karicheri
b186f4b1a2 ARM: dts: k2g-evm: remove unused phy-mode property from phy node
This patch removes the unused phy-mode property from the phy dt node. On
K2G, currently link-interface determines if phy is used or not and is
already set to use rgmii. So this is not needed. Besides phy-mode should
be added to slave interface configuration of the cpsw driver, not in the
phy node.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:46 -04:00
Murali Karicheri
f748ec9d32 ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:46 -04:00
Murali Karicheri
c7206e9789 ARM: k2g-ice: Add pinmux support for rgmii interface
This add pinmux configuration for rgmii interface so that network
driver can be supported on K2G ICE boards. The pinmux configurations
for this are generated using the pinmux tool at
https://dev.ti.com/pinmux/app.html#/default

As this required some BUFFER_CLASS definitions, same is re-used
from the linux defnitions in include/dt-bindings/pinctrl/keystone.h

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:45 -04:00
Neil Armstrong
ffd4c7c2ec dts: switch spi-flash to jedec, spi-nor compatible
There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot
dts files. This compatible has been added in sf_probe, let use it.

This patch switches to jedec,spi-nor when spi-flash is used in the DTS
and DTSI files, and removed spi-flash when jedec,spi-nor is already
present.

The x86 dts are switched in a separate commit since it depends on a change
in fdtdec.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Chris Packham
937cb9d0a6 ARM: mvebu: sync db-88f6820-amc.dts with Linux v5.0
Sync armada-385-db-88f6820-amc.dts with Linux. Retain the
u-boot,dm-pre-reloc and nand differences.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:20:20 +02:00
Chris Packham
205c75e88c ARM: mvebu: rename armada-385-amc.dts to armada-385-db-88f6820-amc.dts
This board was added to u-boot first but the Linux maintainers requested
a more descriptive name. Rename the file to match the Linux usage and
update the board defconfig.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:20:10 +02:00
Leigh Brown
93b3e81212 ARM: kirkwood: remove obsolete call to icache_enable
Commit 93b283d49f ("ARM: CPU: arm926ejs: Consolidate cache routines to
common file") changed cache setup for Kirkwood such that icache_enable()
is now called from enable_caches() which is called from initr_caches()
which is in the list of functions in init_sequence_r[] prior to
arch_misc_init().  This means the call to icache_enable() in
arch_misc_init() is no longer required, so remove it.

Signed-off-by: Leigh Brown <leigh@solinno.co.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
4db944ab44 arm: mvebu: Add DB-XC3-24G4XG board
The DB-XC3-24G4XG is a switch development board from Marvell. It can
either use and external CPU card such as the db-88f6820-amc or the
internal CPU that is integrated into the switch.

Add support for running U-Boot on the internal CPU and enable the USB,
SPI and NAND peripherals. For now this needs the bin_hdr from the
Marvell U-Boot for this board.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
689f9cf6aa arm: mvebu: NAND clock support for MSYS devices
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
0d0df46ee7 arm: mvebu: Add Marvell's integrated CPUs
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Stefan Roese
237b629e4c arm: mvebu: Fix Kconfig dependency warnings
We now have MEVBU boards without SPL support (e.g. db-xc3-24g4xg).
Because of this, a new compile time warning from Kconfig is show:

WARNING: unmet direct dependencies detected for SPL_OF_CONTROL
  Depends on [n]: SUPPORT_OF_CONTROL [=y] && SPL [=n] && OF_CONTROL [=y]
  Selected by [y]:
  - ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y]

WARNING: unmet direct dependencies detected for SPL_DM
  Depends on [n]: DM [=y] && SPL [=n]
  Selected by [y]:
  - ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y]
...

This patch fixes this issue and removes these warnings.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
2019-04-12 07:04:18 +02:00
Stefan Roese
0a590243d1 arm: mvebu: AXP: Enhance PCIe port capability configuration
This patch enables the PCIe port specific link capabilities configuration
for Armada XP. The weak function board_sat_r_get() was used to return
a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This
is now changed with this patch to return a bit per PCIe port (4 bits
in this case, bit 0 for PCIe port 0, etc).

The theadorable board uses this new feature to configure PCIe port 0
as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards
using this function are not changed in the configuration and still
configure all ports as PCIe Gen2.

This patch also removes the parameter "pex_mode" from
board_serdes_cfg_get() as this parameter was not used in any of the
implementations.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
2019-04-12 07:04:18 +02:00
Baruch Siach
4b11e5f6b3 ARM: mvebu: define board_ahci_enable() for A38x
This allows the ahci_mvebu driver to do A38x platform specific
configuration at initialization.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
fa8d96f625 ARM: kirkwood: remove kw_config_adr_windows
Now that kirkwood is using the mvebu mbus this function is no longer
needed.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
8ef078b4be ARM: kirkwood: switch to using mvebu mbus
The mvebu mbus code already had most of the support required for
kirkwood. The only difference is that unlike the other mvebu targets
kirkwood doesn't have a bridge control block so the code related to
managing that needs to be compiled out.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
35f1ee6474 ARM: kirkwood: remove KW_DEFADR_PCI_IO_REMAP
KW_DEFADR_PCI_IO_REMAP has the same value as KW_DEFADR_PCI_IO and is
only used to set up a 1:1 mapping. Remove it and update the mapping to
use KW_DEFADR_PCI_IO.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
d131ac4845 ARM: kirkwood: rename KW_CPU_WIN_BASE to MVEBU_CPU_WIN_BASE
This will allow the kirkwood platforms to use more common code with the
other mvebu SoCs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
7ceefcbaca arm: mvebu: x530: Enable watchdog in SPL and U-Boot
Enable the hardware watchdog to guard against system lock ups when
running in the SPL or U-Boot. Stop the watchdog just before booting so
that the OS can re-enable it if needed.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
3c265bbe4d arm: sync armada-xp dts files from Linux 5.0
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't
got the new NAND driver the updating binding has not been included.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Grygorii Strashko
736b6c3f87 arm64: dts: ti: k3-am65: add mcu navss nodes
Add DT node for MCU NAVSS its components to get DMA working on AM654
SoC.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11 20:07:12 -04:00
Vignesh R
91dba55ca6 soc: keystone: Merge into ti specific directory
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11 20:07:12 -04:00
Grygorii Strashko
fd6b40b1ba firmware: ti_sci: Add support for NAVSS resource management
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.

This patch adds support for requesting and configuring such resources
from TI-SCI firmware.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11 20:07:12 -04:00
Tom Rini
f95fdf237d Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various rmobile fixes
2019-04-11 14:29:22 -04:00
Lukasz Majewski
9eba5e4160 DTS: imx53: Add imx53-kp-u-boot.dtsi file with u-boot specific property
This file adds the "u-boot,i2c-transaction-bytes" to mc34708 PMIC.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-11 15:21:33 +02:00
Neil Armstrong
91fe071cd0 ARM: dts: Import libretech-ac DT from Linux 5.0
Import Linux 5.0 DT from 1c163f4c7b3f ("Linux 5.0") for the
meson-gxl-s805x-libretech-ac board and the corresponding changes
in meson-gxl.dtsi.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:50:46 +02:00
Julien Masson
f41d723b9f ARM: meson: display Amlogic SoC Information
The Amlogic SoCs have a registers containing the die revision
and packaging type to determine the SoC family and package marketing
name like S905X for the GXL SoC Family.

This code is taken from the Linux meson-gx-socinfo driver and adapted
to U-Boot printing.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: also updated new p200/p201 defconfigs]
2019-04-10 16:48:31 +02:00
Mohammad Rasim
56c74b6ce2 ARM: dts: meson: add u-boot.dtsi for p200 and p201
This adds *-u-boot.dtsi files for p200 and p201 boards
These are just copies of arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:48:31 +02:00
Mohammad Rasim
92e5f31b04 ARM: dts: meson: add p200 and p201 boards
This adds the device trees for p200 and p201 boards.
Synced from kernel 5.0.0
Commit: a667cb7a94d4 ("Merge branch 'akpm' (patches from Andrew)")

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:48:31 +02:00
Mohammad Rasim
4778afcbe7 ARM: board: meson: rename odroid-c2 to p200
This renames the odroid-c2 to p200 and set it as the default GXBB board
Other boards (odroid-c2 and nanopi-k2) will inherit from p200

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:48:31 +02:00
Andre Przywara
067e0b9684 sunxi: Allow booting from 128KB SD/eMMC offset
On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can
actually load the SPL also from sector 256 (128KB) of an SD card or eMMC
chip. For more details, see [1].
In this case the boot source indicator (written at offset 0x28 of SRAM A1)
has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC.

Add those new values to the existing boot source check to allow booting
the SPL from those "high" disk offsets as well. For this to work, the
value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted,
for instance to 0x140 (right after the high SPL). Doing this dynamically
sounds desirable, but looks nasty to implement.

[1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9d0f9e8374 arm: sunxi: Enable DRAM ODT by default on H3/H5
Most of the boards we support with H3/H5 enable DRAM on-die termination,
which is consistent with the high DRAM clocks that are used.

Make it the default (like it's done for other similar platforms) instead
of defining it in each defconfig.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
882b71e47d arm: sunxi: Set the default DRAM ZQ value to 3881979 on H3/H5
Most H3/H5 boards we support have the DRAM ZQ value set to 3881979,
which is also consistent with the default set for the R40.

Make this value the default on H3/H5 instead of 123.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9c2b0ddc41 arm: sunxi: Allow per-platform DRAM ZQ configuration on sun8i
A few sun8i platforms define specific default DRAM ZQ values, but they
are not taken in account because of MACH_SUN8I being used for the 123
default first.

Replace MACH_SUN8I with the list of platforms that don't have specific
DRAM ZQ values, to avoid overwriting the default for those that do.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Michael Trimarchi
ddd6930215 sunxi: dram_sun8i: Fix A33 memory initialization
While the exact problem is not known, based on discussion between
Philipp Tomsich and André Przywara it is guessed that exit self-refresh
timing is not set with correct value. There may be implicit enter or
exit Self-Refresh anywhere as part of some training phase.

In ZynqMP register guide [1], which is close to the various
Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL
tXS is bits [6:0]: Self refresh exit delay. So it could be safely
increased and it only affects the time after the self-refresh “exit”,
which happens only after (re-)initialisation.

There was no document for cpu in question so based on oscilloscope
readings [2][3] and observed result by comparing allwinner architecture.
So set it same as  Allwinner H5 silicon.

Before this patch, failure rate of was 7%.

This was tested on A33 allwinner cpu, dual rank connection connected
with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3
1.5V

And also this is tested in A33-OLinuXino dev board.

[1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html
[2] https://ibb.co/R70zmyS
[3] https://ibb.co/HVVCGQ8

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:32:59 +05:30
Jagan Teki
1692c73ccb sun50i: a64: Add Oceanic 5205 5inMFD initial support
Oceanic 5205 5inMFD is a 5 inch Multi function display baseboard
designed to mount SoPine SOM.

Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- SD Slot
- SPI-NOR flash
- EMAC, RTL8211E
- MCP2515 CAN
- 4-lane, MIPI-DSI panel
- Goodix 911 CTP
- USB Host
- 12V DC power supply

Linux commit details about the sun50i-a64-oceanic-5205-5inmfd.dts sync:
"arm64: allwinner: a64: Add Oceanic 5205 5inMFD initial support"
(sha1: 00f7980a3bd53d12abc34f68146a8eed0e894248)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-10 15:25:38 +05:30
Marek Vasut
81abfa68f1 ARM: dts: rmobile: Enable USB on E2 Alt
The E2 Alt board has two USB ports, add missing DT nodes to make the
USB available.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
317d13ac63 ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0
Synchronize R-Car Gen3 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
3abd800eb9 ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.0
Synchronize R-Car Gen2 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
b414ab70cd ARM: dts: rmobile: Import R8A77965 M3NULCB DTs
Import R8A77965 M3N ULCB device trees from Linux 5.0 ,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
c6435c317a pinctrl: renesas: Add R8A77965 pin control tables
Add pin control tables for R8A77965 from Linux 5.0 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
933143997b clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
ce417a2f23 ARM: rmobile: Add dedicated R8A77965 SoC support
Add dedicated entry for R8A77965 M3N SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
bdafee778d ARM: rmobile: Enable multi-DTB fit LZO compression
Enable LZO compression of the multi-DTB fitImages, since the U-Boot
with multiple DTs enabled is becoming quite large and the DTs can
be well compressed. The LZO compression saves almost 200 kiB on the
Salvator-X(S) and ULCB targets.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
4fa8375ffe ARM: renesas: Save boot parameters passed in by ATF
The ATF can pass additional information via the first four registers,
x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer
to a device tree with platform information. Save these registers for
future use.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:09 +02:00
Stefan Roese
a71e2f933b arm: at91: Add gardena-gateway-at91sam support
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
d4c8873f93 arm: at91: at91sam9x5.dtsi: Add watchdog handle
This makes it possible to reference the watchdog DT node via "&watchdog"
from board dts files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
da8a771241 arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds
This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
256c2ff0cc arm: at91: Enable watchdog support
This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09 09:28:50 +03:00
Stefan Roese
ce4d04af99 arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled
This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
e6a2769360 arm: at91: Makefile: Compile lowlevel_init only when really necessary
Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Ilko Iliev
d9bd42900c board: pm9g45: Migrate to CONFIG_DM
Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2019-04-09 09:28:50 +03:00
Alexander Dahl
7dee1848d7 ARM: at91: sama5d2: Wrap cpu detection to fix macb driver
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?

That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:

	#ifndef cpu_is_sama5d2
	#define cpu_is_sama5d2() 0
	#endif

That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.

The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:

	=> dhcp
	ethernet@f8008000: PHY present at 1
	ethernet@f8008000: Starting autonegotiation...
	ethernet@f8008000: Autonegotiation complete
	ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
	BOOTP broadcast 1
	BOOTP broadcast 2
	BOOTP broadcast 3
	BOOTP broadcast 4
	BOOTP broadcast 5
	BOOTP broadcast 6
	BOOTP broadcast 7
	BOOTP broadcast 8
	BOOTP broadcast 9
	BOOTP broadcast 10
	BOOTP broadcast 11
	BOOTP broadcast 12
	BOOTP broadcast 13
	BOOTP broadcast 14
	BOOTP broadcast 15
	BOOTP broadcast 16
	BOOTP broadcast 17

	Retry time exceeded; starting again

Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!

The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.

Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-04-09 09:28:50 +03:00
Jagan Teki
85c3d46322 arm: sunxi: Enable DM_MMC on required SoCs
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html

Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-08 16:35:15 -04:00
Andrejs Cainikovs
e82fa10b3e dts: imx8qxp-mek: Add PHY post reset delay
PHY cannot be detected unless we wait about 150 ms.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-08 15:24:39 +02:00
Tom Rini
0e62d5b2ab Fixes for 2019.04
- fix bashism for MX8
 	- fix ethernet for MX53
 	- fix docs for i.MX8
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlynLM8PHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et38/QL/Rc3p1pF6Dr9zKzxA0rcMoBo9MzzTrUP6XrN
 8syDBJNo2u93Msv78xHTQMCcfxRR3bkTYiWPEzWphC4Qk2IZIe2sETxu2BqsmWRI
 qzK5+L7oU3qJYqY8mZTUKPhmNxDu7E6yGXI1cWboWSR+/DMTxrUHZU5gjQyaQ/WN
 Diko1+lyaygZyPv0FzBdx7Vv+agQusGXGu4XbRkOXhrE6ytMv2ZjCzUtMYRIUg8H
 057DtJfwgU+zfimUoeuiltAwywh9UGxmlR4kb6rF5VZWX0Xn/XoVbMR6qRQXaFIz
 PzlNu3FEpOmvBQ5W5xySHS0CzbeTisIopJehZbkCc+XaEr80GplN995rGWGIN5av
 nlYS7rWHyIcVxoQNT61JTfVC1blFu6+tiokINWFI8as0fMrEAU4okzT4oBaGxdun
 CVcZDo9ytxKWLqtpD0MIQW4r4kJ27yWe3s4ot+v/+jb+XwkatX2J6oaiKviFFhuc
 BwniIb9lsi3ESIOaQXjpJ+qAw9gWYA==
 =//jr
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imx

Fixes for 2019.04

	- fix bashism for MX8
	- fix ethernet for MX53
	- fix docs for i.MX8
2019-04-05 09:09:56 -04:00
Lukasz Majewski
da60b4301c DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)
After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b79106

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-02 13:44:18 +02:00
Tom Rini
da06f9a185 Merge branch 'master' of git://git.denx.de/u-boot-sh
Minor fixes for the Alt board and PHY use on Gen2.
2019-04-01 23:30:00 -04:00
Marek Vasut
e3b086cf04 ARM: dts: rmobile: Activate I2C7 on Alt
Activate I2C7 on Alt to allow access to the PMIC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-30 08:28:25 +01:00
Philipp Tomsich
a2893baa47 Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"
Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.

This reverts commit 0d968ceb1f.
2019-03-29 09:21:13 +01:00
Tom Rini
d32519ac8a Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various fixes for bugs found by u-boot test.py
2019-03-26 23:19:11 -04:00
Patrick Delaunay
abe66b1b5d Convert CONFIG_ENV_SPI_* to Kconfig
This converts the following to Kconfig:
  CONFIG_ENV_SPI_BUS
  CONFIG_ENV_SPI_CS
  CONFIG_ENV_SPI_MAX_HZ
  CONFIG_ENV_SPI_MODE

Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:36:59 -04:00
Patrick Delaunay
ac31d0d873 exynos: replace CONFIG_ENV_SPI_BASE by CONFIG_SYS_SPI_BASE
Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:35:52 -04:00
Marek Vasut
c49d0ac38a ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator
An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc
pin that the usual toggling of regulator to power the card off and on
is insufficient. When the card is calibrated into UHS SDR104 mode, it
will remain in that mode across the power cycle and subsequent attempt
to communicate with the card will fail.

The test with this card is to insert it into an SDHI slot and perform
"mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail.

Fix this problem by increasing the off-on delay from 0 to 20 mS.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Masahiro Yamada
89c2b5c020 ARM: fix arch/arm/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

As a result, a lot of wrong code have been merged unnoticed.

I am going to revert that commit, and lots of hidden issues have
come to light:

[1] Typos

  armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts

  use the extension ".dts" instead of ".dtb"

[2] DTB is associated to undefined CONFIG option

  For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
  associates its device tree to CONFIG_MX6SL, which is undefined.

[3] Lots of entries are missing

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
[trini: add imx6ul pico dtbs]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-03-22 12:15:09 -04:00
Alexander Graf
ef331e3685 armv8: Disable exception vectors in SPL by default
Commit 1416e2d225 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.

Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.

So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-22 12:15:03 -04:00
Keerthy
6dad56d733 arm: lib: bootm: Push the Starting kernel print to the end
Push the Starting kernel print to the end just before the
dm_remove_devices call.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-22 08:35:50 -04:00
Tom Rini
a00d15757d Merge git://git.denx.de/u-boot-marvell
- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)
2019-03-19 19:58:48 -04:00
Tom Rini
810ae23fbc Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2019-03-19 07:13:23 -04:00
Chris Packham
599f7aa541 ARM: kirkwood: disable dcache for Kirkwood boards
Prior to commit 93b283d49f ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.

Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
825dd50f59 ARM: mvebu: use correct name for pcie controller
When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.

Reported-by: Влад Мао <vlaomao@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
5860532264 ARM: kirkwood: add spi0 alias for dreamplug
The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.

Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Ley Foon Tan
ff0005b56a ARM: dts: socfpga: Add missing altr,sysmgr-syscon for EMAC
Syscon register is required in dts to select correct
PHY interface.

Fix error below:

Net:   Failed to get syscon: -2

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-03-16 13:30:03 +01:00
Tom Rini
8303467e80 Merge git://git.denx.de/u-boot-fsl-qoriq
- DPAA2 fixes and DDR errata workaround for LS1021A
2019-03-15 11:58:17 -04:00
Alison Wang
158097052a armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Tom Rini
9659eb46af Merge branch 'master' of git://git.denx.de/u-boot-samsung 2019-03-14 11:37:11 -04:00
Adam Ford
8d0370905c arm: dts: imx6qdl-u-boot: Enable spba-bus@2000000 simple bus
spba-bus has a few nodes under it including the UART1 and
some ESPI buses.  In order to use them in SPL, the
u-boot,dm-spl flag needs to be added to the spba-bus@2000000
container.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
75cd09cb18 imx8qxp: Fix the reported CPU frequency
Currently the CPU frequency is incorrectly reported:

CPU:   NXP i.MX8QXP RevB A35 at 147228 MHz

Fix this problem by using a direct call to the SCU firmware to
retrieve the Cortex A35 CPU frequency.

With this change applied the CPU frequency is displayed correctly:

CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz

Tested-by: Marcelo Macedo <marcelo.macedo@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
737d8bd820 pico-imx6ul: Convert to DM MMC
Select CONFIG_DM_MMC=y in order to support MMC driver model.

This allows the MMC board related code to be removed.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2019-03-13 09:14:35 +01:00
Fabio Estevam
e5c2244fc8 pico-imx6ul: Import dts files from kernel
Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2019-03-13 09:14:35 +01:00
Krzysztof Kozlowski
be26c4af3a arm: dts: exynos: Adjust whitespace around status property
Just add spaces around '=' sign for clarity.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:36 +09:00
Krzysztof Kozlowski
ae781d56fe arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 family
Add startup time to LDO regulators of S2MPS11 PMIC on Odroid XU3/XU4/HC1
family of boards to be sure the voltage is proper before relying on the
regulator.

The datasheet for all the S2MPS1x family is inconsistent here and does
not specify unambiguously the value of ramp delay for LDO.  It mentions
30 mV/us in one timing diagram but then omits it completely in LDO
regulator characteristics table (it is specified for bucks).

However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12
mV/us or 24 mV/us.

Without the ramp delay value the consumers do not wait for voltage
settle after changing it.  Although the proper value of ramp delay for
LDOs is unknown, it seems safer to use at least some value from
reference kernel than to leave it unset.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Krzysztof Kozlowski
b5d3faa9f9 arm: dts: exynos: Add supply for ADC block to Odroid XU3 family
The ADC block requires VDD supply to be on so provide one.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Tom Rini
19c8c9c103 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
2019-03-10 10:16:07 -04:00
Marek Vasut
7544ad0303 ARM: socfpga: Disable D cache in SPL
The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 17:59:13 +01:00
Dinh Nguyen
532a54e652 ARM: socfpga: fix data and tag latency values for pl310 cache controller
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-03-09 17:59:13 +01:00
Eugeniu Rosca
3a4511ce4a ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N
v2019.01 commit cbff9f80ce ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.

Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
 - f529bc551b ("ARM: dts: rmobile: Extract USB nodes on M3N")
 - 830b94f768 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")

Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
 - not needed if no U-boot-specific changes are needed in those nodes.
 - potentially dangerous/error-prone, since the duplicated properties
   override the properties originally defined in <soc>.dtsi. One
   possible consequence is that <soc>.dtsi is getting an update from
   Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
   the obsolete property values from <soc>-u-boot.dtsi will take
   precedence masking some of the <soc>.dtsi updates, potentially
   leading to all kind of obscure issues.

Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).

What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.

$> dtdiff before-r8a77965-salvator-x-u-boot.dtb \
           after-r8a77965-salvator-x-u-boot.dtb
 --- /dev/fd/63  2019-03-09 12:57:40.877963983 +0100
 +++ /dev/fd/62  2019-03-09 12:57:40.877963983 +0100
 @@ -1471,7 +1471,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x51 0xc 0x1>;
        clocks = <0x6 0x1 0x13a>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa5 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x4d>;
 @@ -1492,7 +1492,7 @@

      sd@ee120000 {
        clocks = <0x6 0x1 0x139>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa6 0x4>;
        max-frequency = <0xbebc200>;
        power-domains = <0x1 0x20>;
 @@ -1504,7 +1504,7 @@
      sd@ee140000 {
        bus-width = <0x8>;
        clocks = <0x6 0x1 0x138>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        fixed-emmc-driver-type = <0x1>;
        interrupts = <0x0 0xa7 0x4>;
        max-frequency = <0xbebc200>;
 @@ -1526,7 +1526,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x5a 0xf 0x1>;
        clocks = <0x6 0x1 0x137>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa8 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x56>;
 @@ -1868,14 +1868,14 @@

      usb-phy@ee0a0200 {
        #phy-cells = <0x0>;
 -      clocks = <0x6 0x1 0x2be>;
 +      clocks = <0x6 0x1 0x2bf>;
        compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy";
        phandle = <0x47>;
        pinctrl-0 = <0x4c>;
        pinctrl-names = "default";
        power-domains = <0x1 0x20>;
        reg = <0x0 0xee0a0200 0x0 0x700>;
 -      resets = <0x6 0x2be>;
 +      resets = <0x6 0x2bf>;
        status = "okay";
      };

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-03-09 17:57:04 +01:00
Marek Vasut
fc3ed156f9 ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPI
U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until
we can do better using the new SPI NOR framework.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-09 17:57:04 +01:00
Laurentiu Tudor
7122f79141 armv8: fsl-layerscape: avoid DT fixup warning
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:

WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.

Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:14 +05:30
Laurentiu Tudor
e82d9ee73a armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:09 +05:30
Rajesh Bhagat
32413125b3 configs: fsl: move DDR specific defines to Kconfig
Moves below DDR specific defines to Kconfig:

CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 20:56:01 +05:30
Tom Rini
cfba74d0be Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA cache/gpio fixes
2019-02-28 18:57:32 -05:00
Tom Rini
35b05146f6 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28 18:57:17 -05:00
Tom Rini
da206916a1 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Various Bananapi fixes
2019-02-28 14:22:50 -05:00
Marek Vasut
86dc480d73 ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2019-02-28 14:21:46 -05:00
Marek Vasut
30b62ca086 ARM: rmobile: Imply SoC per board
Imply all SoCs supported by a given board. This allows building single
U-Boot binary for boards which can have multiple SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
669367f6a4 ARM: rmobile: Imply pinctrl drivers per SoC
Imply preferred pin control driver per SoC, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
46467ceaf4 ARM: rmobile: Imply clock drivers per SoC
Imply preferred clock driver per SoC, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
4a9743f73c ARM: socfpga: Clear PL310 early in SPL
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.

The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.

This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.

The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25 16:07:36 +01:00
Marek Vasut
2c0b300bc3 ARM: socfpga: Configure PL310 latencies
Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25 16:07:36 +01:00
Marek Vasut
b275c9aba6 ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
2019-02-25 16:07:36 +01:00
Tom Rini
888f9aa5ca Merge branch 'master' of git://git.denx.de/u-boot-tegra 2019-02-20 12:28:57 -05:00
Tom Rini
176b32cd4f Merge git://git.denx.de/u-boot-fsl-qoriq
- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
2019-02-20 12:26:05 -05:00
Tristan Bastian
8105816cbb ARM: tegra: enable ums on nyan boards
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef.
But the nyan devices never received that functionality.

Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Tristan Bastian
74a7d9af3f nyan-big: change spi delay
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button.
With this patch keyboard is working by only pressing [power] button.

Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Derald D. Woods
36a75344d7 ARM: omap3: evm: Update DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties
- Enable SPL_OF_CONTROL

This commit is based on the following series:

https://patchwork.ozlabs.org/project/uboot/list/?series=92472
https://patchwork.ozlabs.org/project/uboot/list/?series=92462

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-19 16:58:24 -05:00
Tom Rini
e0cc7df9fd omap3_beagle: Update for DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties.
- Remove a few SPL features to free up more SRAM space.
- Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to
  worry about X-Loader at this point anymore.
- A few related updates to SPL options as part of switching to DM SPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19 16:58:23 -05:00
Adam Ford
0cd9465c0b ARM: omap3_logic: Enable SPL booting device tree
With the generic omap3-u-boot.dtsi file available, this patch
increased the memory of the various incarnations of the omap3_logic
board, and points their respective u-boot.dtsi files to the newly
created generic one, and removes the PLATDATA from the board file.

These are all done at once because the're all utilizing the same
omap3logic.c board file.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-19 16:58:23 -05:00
Adam Ford
ed59a76db0 ARM: DTS: omap3-u-boot.dtsi
Create generic omap3-u-boot.dtsi file that omap3 based boards
can include to generate device tree in SPL for booting MLO.

Credit should go to Tom Rini.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19 16:58:23 -05:00
Hannes Schmelzer
eaba7df704 board/BuR/brxre1: convert do DM
This commit converts the brxre1 board to DM,
for this we have todo following things:

- add a devicetree-file for this board
- drop all obsolete settings from board header-file
- use dm_i2c_xxx calls for read/write to the resetcontroller
- request gpios before operate them

Serues-cc: trini@konsulko.com
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-19 08:55:43 -05:00
Peng Ma
f11e492aea armv8: ls1043a: move SCSI_AHCI and SCSI to arm/Kconfig
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface
support.
this changed is to fixed the ls1043ardb compile warning as fallows:

===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the
v2019.07 release. Failure to update by the deadline may
result in board removal.See doc/driver-model/MIGRATION.txt
for more info.
====================================================

Signed-off-by: Peng Ma <peng.ma@nxp.com>
[PK: reword the patch subject]
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
5c08d96f3a armv8: layerscape: move CONFIG_LAYERSCAPE to Kconfig
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
bbf5b25282 armv8: layerscape: move TZASC and TZPC configs to Kconfig
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30