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ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7

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Synchronize stm32f7 device tree with kernel v4.20.

All pinctrl bindings are updated.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard 2019-02-19 16:49:05 +01:00
parent 01aabf97d1
commit fe63d3cfb7
12 changed files with 1315 additions and 1869 deletions
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161
arch/arm/dts/stm32746g-eval-u-boot.dtsi
View file

@ -19,7 +19,7 @@
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdio;
mmc0 = &sdio1;
spi0 = &qspi;
};
@ -66,97 +66,114 @@
&pinctrl {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F746_PA2_FUNC_ETH_MDIO>,
<STM32F746_PC1_FUNC_ETH_MDC>,
<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
pinmux = <STM32_PINMUX('A', 0, AF11)>, /*ETH_MII_CRS */
<STM32_PINMUX('A', 1, AF11)>, /*ETH_MII_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>, /*ETH_MII_RX_DV */
<STM32_PINMUX('A', 8, AF0)>, /*ETH_MII_MCO1 */
<STM32_PINMUX('G',13, AF11)>, /*ETH_MII_TXD0 */
<STM32_PINMUX('G',14, AF11)>, /*ETH_MII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /*ETH_MII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /*ETH_MII_TXD3 */
<STM32_PINMUX('C', 3, AF11)>, /*ETH_MII_TX_CLK */
<STM32_PINMUX('C', 4, AF11)>, /*ETH_MII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /*ETH_MII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /*ETH_MII_RXD2 */
<STM32_PINMUX('H', 7, AF11)>, /*ETH_MII_RXD3 */
<STM32_PINMUX('G',11, AF11)>, /*ETH_MII_TX_EN */
<STM32_PINMUX('C', 1, AF11)>, /*ETH_MII_MDC */
<STM32_PINMUX('A', 2, AF11)>; /*ETH_MII_MDIO */
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
<STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
<STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
<STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
<STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
<STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
<STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
<STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
<STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
<STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
<STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
<STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
<STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
<STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
<STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
<STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
<STM32_PINMUX('I', 9, AF12)>, /* D30 */
<STM32_PINMUX('I', 7, AF12)>, /* D29 */
<STM32_PINMUX('I', 6, AF12)>, /* D28 */
<STM32_PINMUX('I', 3, AF12)>, /* D27 */
<STM32_PINMUX('I', 2, AF12)>, /* D26 */
<STM32_PINMUX('I', 1, AF12)>, /* D25 */
<STM32_PINMUX('I', 0, AF12)>, /* D24 */
<STM32_PINMUX('H',15, AF12)>, /* D23 */
<STM32_PINMUX('H',14, AF12)>, /* D22 */
<STM32_PINMUX('H',13, AF12)>, /* D21 */
<STM32_PINMUX('H',12, AF12)>, /* D20 */
<STM32_PINMUX('H',11, AF12)>, /* D19 */
<STM32_PINMUX('H',10, AF12)>, /* D18 */
<STM32_PINMUX('H', 9, AF12)>, /* D17 */
<STM32_PINMUX('H', 8, AF12)>, /* D16 */
<STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
<STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
<STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
<STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
<STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
<STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
<STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
<STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
<STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
<STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
<STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
<STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
<STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
<STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
<STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
<STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
<STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
<STM32_PINMUX('E',15, AF12)>, /* D12 */
<STM32_PINMUX('E',14, AF12)>, /* D11 */
<STM32_PINMUX('E',13, AF12)>, /* D10 */
<STM32_PINMUX('E',12, AF12)>, /* D9 */
<STM32_PINMUX('E',11, AF12)>, /* D8 */
<STM32_PINMUX('E',10, AF12)>, /* D7 */
<STM32_PINMUX('E', 9, AF12)>, /* D6 */
<STM32_PINMUX('E', 8, AF12)>, /* D5 */
<STM32_PINMUX('E', 7, AF12)>, /* D4 */
<STM32_PINMUX('D', 1, AF12)>, /* D3 */
<STM32_PINMUX('D', 0, AF12)>, /* D2 */
<STM32_PINMUX('D',15, AF12)>, /* D1 */
<STM32_PINMUX('D',14, AF12)>, /* D0 */
<STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
<STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
<STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
<STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
<STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
<STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
<STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
<STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
<STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
<STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
<STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
<STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
<STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
<STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
<STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
<STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
<STM32_PINMUX('F',15, AF12)>, /* A9 */
<STM32_PINMUX('F',14, AF12)>, /* A8 */
<STM32_PINMUX('F',13, AF12)>, /* A7 */
<STM32_PINMUX('F',12, AF12)>, /* A6 */
<STM32_PINMUX('F', 5, AF12)>, /* A5 */
<STM32_PINMUX('F', 4, AF12)>, /* A4 */
<STM32_PINMUX('F', 3, AF12)>, /* A3 */
<STM32_PINMUX('F', 2, AF12)>, /* A2 */
<STM32_PINMUX('F', 1, AF12)>, /* A1 */
<STM32_PINMUX('F', 0, AF12)>, /* A0 */
<STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
<STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
<STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
<STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
<STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
<STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
<STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
<STM32F746_PF8_FUNC_QUADSPI_BK1_IO0>,
<STM32F746_PF9_FUNC_QUADSPI_BK1_IO1>,
<STM32F746_PF6_FUNC_QUADSPI_BK1_IO3>,
<STM32F746_PF7_FUNC_QUADSPI_BK1_IO2>;
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* _FUNC_QUADSPI_CLK */
<STM32_PINMUX('B', 6, AF10)>, /*_FUNC_QUADSPI_BK1_NCS */
<STM32_PINMUX('F', 8, AF10)>, /* _FUNC_QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* _FUNC_QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 6, AF9)>, /* AF_FUNC_QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 7, AF9)>; /* _FUNC_QUADSPI_BK1_IO2 */
slew-rate = <2>;
};
};
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
};
&qspi {

102
arch/arm/dts/stm32746g-eval.dts
View file

@ -1,9 +1,5 @@
/*
* Copyright 2018 - Christophe Priouzeau <christophe.priouzeau@st.com>
*
* Based on:
* stm32f746-disco.dts from U-boot 2018.01
* Copyright 2016 - Lee Jones <lee.jones@linaro.org>
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -46,42 +42,92 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32F746G-EVAL board";
compatible = "st,stm32f746g-eval", "st,stm32f746";
model = "STMicroelectronics STM32746g-EVAL board";
compatible = "st,stm32746g-eval", "st,stm32f746";
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0xC0000000 0x2000000>;
reg = <0xc0000000 0x2000000>;
};
aliases {
serial0 = &usart1;
};
leds {
compatible = "gpio-leds";
green {
gpios = <&gpiof 10 1>;
linux,default-trigger = "heartbeat";
};
red {
gpios = <&gpiob 7 1>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>;
};
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
mmc_vcard: mmc_vcard {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&clk_hse {
clock-frequency = <25000000>;
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
&crc {
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&rtc {
status = "okay";
};
&sdio1 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
broken-cd;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_a>;
pinctrl-1 = <&sdio_pins_od_a>;
bus-width = <4>;
};
&usart1 {
@ -90,11 +136,11 @@
status = "okay";
};
&sdio {
&usbotg_hs {
dr_mode = "otg";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
status = "okay";
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
bus-width = <4>;
max-frequency = <25000000>;
};

289
arch/arm/dts/stm32f7-pinctrl.dtsi Normal file
View file

@ -0,0 +1,289 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
soc {
pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
cec_pins_a: cec@0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
slew-rate = <0>;
drive-open-drain;
bias-disable;
};
};
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_pins_b: usart1@1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
bias-disable;
};
};
i2c1_pins_b: i2c1@0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
usbotg_hs_pins_a: usbotg-hs@0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_hs_pins_b: usbotg-hs@1 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_fs_pins_a: usbotg-fs@0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_a: sdio_pins_a@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od_a: sdio_pins_od_a@0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
drive-open-drain;
slew-rate = <2>;
};
};
sdio_pins_b: sdio_pins_b@0 {
pins {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
<STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
<STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od_b: sdio_pins_od_b@0 {
pins1 {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
<STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
drive-open-drain;
slew-rate = <2>;
};
};
};
};
};

11
arch/arm/dts/stm32f7-u-boot.dtsi
View file

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/memory/stm32-sdram.h>
/{
soc {
u-boot,dm-pre-reloc;
@ -126,16 +127,6 @@
u-boot,dm-pre-reloc;
};
};
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
};
&pwrcfg {

166
arch/arm/dts/stm32f746-disco-u-boot.dtsi
View file

@ -19,7 +19,7 @@
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdio;
mmc0 = &sdio1;
spi0 = &qspi;
};
@ -109,15 +109,15 @@
&pinctrl {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F746_PA2_FUNC_ETH_MDIO>,
<STM32F746_PC1_FUNC_ETH_MDC>,
<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
slew-rate = <2>;
};
};
@ -126,99 +126,99 @@
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
<STM32F746_PD9_FUNC_FMC_D14>,
<STM32F746_PD8_FUNC_FMC_D13>,
<STM32F746_PE15_FUNC_FMC_D12>,
<STM32F746_PE14_FUNC_FMC_D11>,
<STM32F746_PE13_FUNC_FMC_D10>,
<STM32F746_PE12_FUNC_FMC_D9>,
<STM32F746_PE11_FUNC_FMC_D8>,
<STM32F746_PE10_FUNC_FMC_D7>,
<STM32F746_PE9_FUNC_FMC_D6>,
<STM32F746_PE8_FUNC_FMC_D5>,
<STM32F746_PE7_FUNC_FMC_D4>,
<STM32F746_PD1_FUNC_FMC_D3>,
<STM32F746_PD0_FUNC_FMC_D2>,
<STM32F746_PD15_FUNC_FMC_D1>,
<STM32F746_PD14_FUNC_FMC_D0>,
pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
<STM32_PINMUX('E',15, AF12)>, /* D12 */
<STM32_PINMUX('E',14, AF12)>, /* D11 */
<STM32_PINMUX('E',13, AF12)>, /* D10 */
<STM32_PINMUX('E',12, AF12)>, /* D9 */
<STM32_PINMUX('E',11, AF12)>, /* D8 */
<STM32_PINMUX('E',10, AF12)>, /* D7 */
<STM32_PINMUX('E', 9, AF12)>, /* D6 */
<STM32_PINMUX('E', 8, AF12)>, /* D5 */
<STM32_PINMUX('E', 7, AF12)>, /* D4 */
<STM32_PINMUX('D', 1, AF12)>, /* D3 */
<STM32_PINMUX('D', 0, AF12)>, /* D2 */
<STM32_PINMUX('D',15, AF12)>, /* D1 */
<STM32_PINMUX('D',14, AF12)>, /* D0 */
<STM32F746_PE1_FUNC_FMC_NBL1>,
<STM32F746_PE0_FUNC_FMC_NBL0>,
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
<STM32F746_PG1_FUNC_FMC_A11>,
<STM32F746_PG0_FUNC_FMC_A10>,
<STM32F746_PF15_FUNC_FMC_A9>,
<STM32F746_PF14_FUNC_FMC_A8>,
<STM32F746_PF13_FUNC_FMC_A7>,
<STM32F746_PF12_FUNC_FMC_A6>,
<STM32F746_PF5_FUNC_FMC_A5>,
<STM32F746_PF4_FUNC_FMC_A4>,
<STM32F746_PF3_FUNC_FMC_A3>,
<STM32F746_PF2_FUNC_FMC_A2>,
<STM32F746_PF1_FUNC_FMC_A1>,
<STM32F746_PF0_FUNC_FMC_A0>,
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
<STM32_PINMUX('F',15, AF12)>, /* A9 */
<STM32_PINMUX('F',14, AF12)>, /* A8 */
<STM32_PINMUX('F',13, AF12)>, /* A7 */
<STM32_PINMUX('F',12, AF12)>, /* A6 */
<STM32_PINMUX('F', 5, AF12)>, /* A5 */
<STM32_PINMUX('F', 4, AF12)>, /* A4 */
<STM32_PINMUX('F', 3, AF12)>, /* A3 */
<STM32_PINMUX('F', 2, AF12)>, /* A2 */
<STM32_PINMUX('F', 1, AF12)>, /* A1 */
<STM32_PINMUX('F', 0, AF12)>, /* A0 */
<STM32F746_PH3_FUNC_FMC_SDNE0>,
<STM32F746_PH5_FUNC_FMC_SDNWE>,
<STM32F746_PF11_FUNC_FMC_SDNRAS>,
<STM32F746_PG15_FUNC_FMC_SDNCAS>,
<STM32F746_PC3_FUNC_FMC_SDCKE0>,
<STM32F746_PG8_FUNC_FMC_SDCLK>;
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
<STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
<STM32F746_PG12_FUNC_LCD_B4>,
<STM32F746_PI9_FUNC_LCD_VSYNC>,
<STM32F746_PI10_FUNC_LCD_HSYNC>,
<STM32F746_PI14_FUNC_LCD_CLK>,
<STM32F746_PI15_FUNC_LCD_R0>,
<STM32F746_PJ0_FUNC_LCD_R1>,
<STM32F746_PJ1_FUNC_LCD_R2>,
<STM32F746_PJ2_FUNC_LCD_R3>,
<STM32F746_PJ3_FUNC_LCD_R4>,
<STM32F746_PJ4_FUNC_LCD_R5>,
<STM32F746_PJ5_FUNC_LCD_R6>,
<STM32F746_PJ6_FUNC_LCD_R7>,
<STM32F746_PJ7_FUNC_LCD_G0>,
<STM32F746_PJ8_FUNC_LCD_G1>,
<STM32F746_PJ9_FUNC_LCD_G2>,
<STM32F746_PJ10_FUNC_LCD_G3>,
<STM32F746_PJ11_FUNC_LCD_G4>,
<STM32F746_PJ13_FUNC_LCD_B1>,
<STM32F746_PJ14_FUNC_LCD_B2>,
<STM32F746_PJ15_FUNC_LCD_B3>,
<STM32F746_PK0_FUNC_LCD_G5>,
<STM32F746_PK1_FUNC_LCD_G6>,
<STM32F746_PK2_FUNC_LCD_G7>,
<STM32F746_PK4_FUNC_LCD_B5>,
<STM32F746_PK5_FUNC_LCD_B6>,
<STM32F746_PK6_FUNC_LCD_B7>,
<STM32F746_PK7_FUNC_LCD_DE>;
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
<STM32_PINMUX('G',12, AF14)>, /* B4 */
<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* CLK */
<STM32_PINMUX('I',15, AF14)>, /* R0 */
<STM32_PINMUX('J', 0, AF14)>, /* R1 */
<STM32_PINMUX('J', 1, AF14)>, /* R2 */
<STM32_PINMUX('J', 2, AF14)>, /* R3 */
<STM32_PINMUX('J', 3, AF14)>, /* R4 */
<STM32_PINMUX('J', 4, AF14)>, /* R5 */
<STM32_PINMUX('J', 5, AF14)>, /* R6 */
<STM32_PINMUX('J', 6, AF14)>, /* R7 */
<STM32_PINMUX('J', 7, AF14)>, /* G0 */
<STM32_PINMUX('J', 8, AF14)>, /* G1 */
<STM32_PINMUX('J', 9, AF14)>, /* G2 */
<STM32_PINMUX('J',10, AF14)>, /* G3 */
<STM32_PINMUX('J',11, AF14)>, /* G4 */
<STM32_PINMUX('J',13, AF14)>, /* B1 */
<STM32_PINMUX('J',14, AF14)>, /* B2 */
<STM32_PINMUX('J',15, AF14)>, /* B3 */
<STM32_PINMUX('K', 0, AF14)>, /* G5 */
<STM32_PINMUX('K', 1, AF14)>, /* G6 */
<STM32_PINMUX('K', 2, AF14)>, /* G7 */
<STM32_PINMUX('K', 4, AF14)>, /* B5 */
<STM32_PINMUX('K', 5, AF14)>, /* B6 */
<STM32_PINMUX('K', 6, AF14)>, /* B7 */
<STM32_PINMUX('K', 7, AF14)>; /* DE */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
<STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
<STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
<STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
<STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
<STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
<STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
slew-rate = <2>;
};
};
usart1_pins_a: usart1@0 {
usart1_pins_b: usart1@1 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;

84
arch/arm/dts/stm32f746-disco.dts
View file

@ -1,10 +1,5 @@
/*
* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
*
* Based on:
* stm32f469-disco.dts from Linux
* Copyright 2016 - Lee Jones <lee.jones@linaro.org>
* Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -47,7 +42,8 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@ -55,7 +51,7 @@
compatible = "st,stm32f746-disco", "st,stm32f746";
chosen {
bootargs = "root=/dev/ram rdinit=/linuxrc";
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
@ -67,39 +63,69 @@
serial0 = &usart1;
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
/* This turns on vbus for otg fs for host mode (dwc2) */
vcc5v_otg_fs: vcc5v-otg-fs-regulator {
compatible = "regulator-fixed";
gpio = <&gpiod 5 0>;
regulator-name = "vcc5_host1";
regulator-always-on;
};
mmc_vcard: mmc_vcard {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&clk_hse {
clock-frequency = <25000000>;
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
bias-disable;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&sdio1 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_a>;
pinctrl-1 = <&sdio_pins_od_a>;
bus-width = <4>;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-0 = <&usart1_pins_b>;
pinctrl-names = "default";
status = "okay";
};
&sdio {
&usbotg_fs {
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&usbotg_hs {
dr_mode = "host";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_b>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
bus-width = <4>;
max-frequency = <25000000>;
};

11
arch/arm/dts/stm32f746-pinctrl.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include "stm32f7-pinctrl.dtsi"
&pinctrl{
compatible = "st,stm32f746-pinctrl";
};

769
arch/arm/dts/stm32f746.dtsi
View file

@ -1,9 +1,4 @@
/*
* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
*
* Based on:
* stm32f429.dtsi from Linux
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
@ -45,8 +40,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@ -57,223 +52,112 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_i2s_ckin: clk-i2s-ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
};
soc {
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
pwrcfg: power-config@58024800 {
compatible = "syscon";
reg = <0x40007000 0x400>;
};
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
st,syscfg = <&pwrcfg>;
};
pinctrl: pin-controller {
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f746-pinctrl";
ranges = <0 0x40020000 0x3000>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
sdio_pins: sdio_pins@0 {
pins {
pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
<STM32F746_PC9_FUNC_SDMMC1_D1>,
<STM32F746_PC10_FUNC_SDMMC1_D2>,
<STM32F746_PC11_FUNC_SDMMC1_D3>,
<STM32F746_PC12_FUNC_SDMMC1_CK>,
<STM32F746_PD2_FUNC_SDMMC1_CMD>;
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od: sdio_pins_od@0 {
pins1 {
pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
<STM32F746_PC9_FUNC_SDMMC1_D1>,
<STM32F746_PC10_FUNC_SDMMC1_D2>,
<STM32F746_PC11_FUNC_SDMMC1_D3>,
<STM32F746_PC12_FUNC_SDMMC1_CK>;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
drive-open-drain;
slew-rate = <2>;
};
};
sdio_pins_b: sdio_pins_b@0 {
pins {
pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
<STM32F769_PG10_FUNC_SDMMC2_D1>,
<STM32F769_PB3_FUNC_SDMMC2_D2>,
<STM32F769_PB4_FUNC_SDMMC2_D3>,
<STM32F769_PD6_FUNC_SDMMC2_CLK>,
<STM32F769_PD7_FUNC_SDMMC2_CMD>;
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od_b: sdio_pins_od_b@0 {
pins1 {
pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
<STM32F769_PG10_FUNC_SDMMC2_D1>,
<STM32F769_PB3_FUNC_SDMMC2_D2>,
<STM32F769_PB4_FUNC_SDMMC2_D3>,
<STM32F769_PD6_FUNC_SDMMC2_CLK>;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
drive-open-drain;
slew-rate = <2>;
};
};
};
sdio: sdio@40012c00 {
compatible = "st,stm32f4xx-sdio";
reg = <0x40012c00 0x400>;
clocks = <&rcc 0 171>;
interrupts = <49>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
clock-names = "int";
status = "disabled";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@1 {
compatible = "st,stm32-timer-trigger";
reg = <1>;
status = "disabled";
};
};
sdio2: sdio2@40011c00 {
compatible = "st,stm32f4xx-sdio";
reg = <0x40011c00 0x400>;
clocks = <&rcc 0 167>;
interrupts = <103>;
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
pinctrl-0 = <&sdio_pins_b>;
pinctrl-1 = <&sdio_pins_od_b>;
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
};
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@2 {
compatible = "st,stm32-timer-trigger";
reg = <2>;
status = "disabled";
};
};
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@3 {
compatible = "st,stm32-timer-trigger";
reg = <3>;
status = "disabled";
};
};
timer5: timer@40000c00 {
@ -282,9 +166,470 @@
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@4 {
compatible = "st,stm32-timer-trigger";
reg = <4>;
status = "disabled";
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
clock-names = "int";
status = "disabled";
timer@5 {
compatible = "st,stm32-timer-trigger";
reg = <5>;
status = "disabled";
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
clock-names = "int";
status = "disabled";
timer@6 {
compatible = "st,stm32-timer-trigger";
reg = <6>;
status = "disabled";
};
};
timers12: timers@40001800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@11 {
compatible = "st,stm32-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
clocks = <&rcc 1 CLK_USART2>;
status = "disabled";
};
usart3: serial@40004800 {
compatible = "st,stm32f7-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
clocks = <&rcc 1 CLK_USART3>;
status = "disabled";
};
usart4: serial@40004c00 {
compatible = "st,stm32f7-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
clocks = <&rcc 1 CLK_UART4>;
status = "disabled";
};
usart5: serial@40005000 {
compatible = "st,stm32f7-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
clocks = <&rcc 1 CLK_UART5>;
status = "disabled";
};
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
reg = <0x40005400 0x400>;
interrupts = <31>,
<32>;
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@40005800 {
compatible = "st,stm32f7-i2c";
reg = <0x40005800 0x400>;
interrupts = <33>,
<34>;
resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@40005C00 {
compatible = "st,stm32f7-i2c";
reg = <0x40005C00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@40006000 {
compatible = "st,stm32f7-i2c";
reg = <0x40006000 0x400>;
interrupts = <95>,
<96>;
resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cec: cec@40006c00 {
compatible = "st,stm32-cec";
reg = <0x40006C00 0x400>;
interrupts = <94>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
usart7: serial@40007800 {
compatible = "st,stm32f7-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
clocks = <&rcc 1 CLK_UART7>;
status = "disabled";
};
usart8: serial@40007c00 {
compatible = "st,stm32f7-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
clocks = <&rcc 1 CLK_UART8>;
status = "disabled";
};
timers1: timers@40010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@0 {
compatible = "st,stm32-timer-trigger";
reg = <0>;
status = "disabled";
};
};
timers8: timers@40010400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@7 {
compatible = "st,stm32-timer-trigger";
reg = <7>;
status = "disabled";
};
};
usart1: serial@40011000 {
compatible = "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 1 CLK_USART1>;
status = "disabled";
};
usart6: serial@40011400 {
compatible = "st,stm32f7-uart";
reg = <0x40011400 0x400>;
interrupts = <71>;
clocks = <&rcc 1 CLK_USART6>;
status = "disabled";
};
sdio2: sdio2@40011c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40011c00 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
clock-names = "apb_pclk";
interrupts = <103>;
max-frequency = <48000000>;
status = "disabled";
};
sdio1: sdio1@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
clock-names = "apb_pclk";
interrupts = <49>;
max-frequency = <48000000>;
status = "disabled";
};
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
};
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40013C00 0x400>;
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
timers9: timers@40014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@8 {
compatible = "st,stm32-timer-trigger";
reg = <8>;
status = "disabled";
};
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
pwrcfg: power-config@40007000 {
compatible = "syscon";
reg = <0x40007000 0x400>;
};
crc: crc@40023000 {
compatible = "st,stm32f7-crc";
reg = <0x40023000 0x400>;
clocks = <&rcc 0 12>;
status = "disabled";
};
rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <1000000>;
};
dma1: dma@40026000 {
compatible = "st,stm32-dma";
reg = <0x40026000 0x400>;
interrupts = <11>,
<12>,
<13>,
<14>,
<15>,
<16>,
<17>,
<47>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
#dma-cells = <4>;
status = "disabled";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma";
reg = <0x40026400 0x400>;
interrupts = <56>,
<57>,
<58>,
<59>,
<60>,
<68>,
<69>,
<70>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
#dma-cells = <4>;
st,mem2mem;
status = "disabled";
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32f7-hsotg";
reg = <0x40040000 0x40000>;
interrupts = <77>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
clock-names = "otg";
g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
status = "disabled";
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32f4x9-fsotg";
reg = <0x50000000 0x40000>;
interrupts = <67>;
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
clock-names = "otg";
status = "disabled";
};
};
};
&systick {
clocks = <&rcc 1 0>;
status = "okay";
};

142
arch/arm/dts/stm32f769-disco-u-boot.dtsi
View file

@ -61,94 +61,94 @@
&pinctrl {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F746_PA2_FUNC_ETH_MDIO>,
<STM32F746_PC1_FUNC_ETH_MDC>,
<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
<STM32F746_PI9_FUNC_FMC_D30>,
<STM32F746_PI7_FUNC_FMC_D29>,
<STM32F746_PI6_FUNC_FMC_D28>,
<STM32F746_PI3_FUNC_FMC_D27>,
<STM32F746_PI2_FUNC_FMC_D26>,
<STM32F746_PI1_FUNC_FMC_D25>,
<STM32F746_PI0_FUNC_FMC_D24>,
<STM32F746_PH15_FUNC_FMC_D23>,
<STM32F746_PH14_FUNC_FMC_D22>,
<STM32F746_PH13_FUNC_FMC_D21>,
<STM32F746_PH12_FUNC_FMC_D20>,
<STM32F746_PH11_FUNC_FMC_D19>,
<STM32F746_PH10_FUNC_FMC_D18>,
<STM32F746_PH9_FUNC_FMC_D17>,
<STM32F746_PH8_FUNC_FMC_D16>,
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
<STM32_PINMUX('I', 9, AF12)>, /* D30 */
<STM32_PINMUX('I', 7, AF12)>, /* D29 */
<STM32_PINMUX('I', 6, AF12)>, /* D28 */
<STM32_PINMUX('I', 3, AF12)>, /* D27 */
<STM32_PINMUX('I', 2, AF12)>, /* D26 */
<STM32_PINMUX('I', 1, AF12)>, /* D25 */
<STM32_PINMUX('I', 0, AF12)>, /* D24 */
<STM32_PINMUX('H',15, AF12)>, /* D23 */
<STM32_PINMUX('H',14, AF12)>, /* D22 */
<STM32_PINMUX('H',13, AF12)>, /* D21 */
<STM32_PINMUX('H',12, AF12)>, /* D20 */
<STM32_PINMUX('H',11, AF12)>, /* D19 */
<STM32_PINMUX('H',10, AF12)>, /* D18 */
<STM32_PINMUX('H', 9, AF12)>, /* D17 */
<STM32_PINMUX('H', 8, AF12)>, /* D16 */
<STM32F746_PD10_FUNC_FMC_D15>,
<STM32F746_PD9_FUNC_FMC_D14>,
<STM32F746_PD8_FUNC_FMC_D13>,
<STM32F746_PE15_FUNC_FMC_D12>,
<STM32F746_PE14_FUNC_FMC_D11>,
<STM32F746_PE13_FUNC_FMC_D10>,
<STM32F746_PE12_FUNC_FMC_D9>,
<STM32F746_PE11_FUNC_FMC_D8>,
<STM32F746_PE10_FUNC_FMC_D7>,
<STM32F746_PE9_FUNC_FMC_D6>,
<STM32F746_PE8_FUNC_FMC_D5>,
<STM32F746_PE7_FUNC_FMC_D4>,
<STM32F746_PD1_FUNC_FMC_D3>,
<STM32F746_PD0_FUNC_FMC_D2>,
<STM32F746_PD15_FUNC_FMC_D1>,
<STM32F746_PD14_FUNC_FMC_D0>,
<STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
<STM32_PINMUX('E',15, AF12)>, /* D12 */
<STM32_PINMUX('E',14, AF12)>, /* D11 */
<STM32_PINMUX('E',13, AF12)>, /* D10 */
<STM32_PINMUX('E',12, AF12)>, /* D9 */
<STM32_PINMUX('E',11, AF12)>, /* D8 */
<STM32_PINMUX('E',10, AF12)>, /* D7 */
<STM32_PINMUX('E', 9, AF12)>, /* D6 */
<STM32_PINMUX('E', 8, AF12)>, /* D5 */
<STM32_PINMUX('E', 7, AF12)>, /* D4 */
<STM32_PINMUX('D', 1, AF12)>, /* D3 */
<STM32_PINMUX('D', 0, AF12)>, /* D2 */
<STM32_PINMUX('D',15, AF12)>, /* D1 */
<STM32_PINMUX('D',14, AF12)>, /* D0 */
<STM32F746_PI5_FUNC_FMC_NBL3>,
<STM32F746_PI4_FUNC_FMC_NBL2>,
<STM32F746_PE1_FUNC_FMC_NBL1>,
<STM32F746_PE0_FUNC_FMC_NBL0>,
<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
<STM32F746_PG1_FUNC_FMC_A11>,
<STM32F746_PG0_FUNC_FMC_A10>,
<STM32F746_PF15_FUNC_FMC_A9>,
<STM32F746_PF14_FUNC_FMC_A8>,
<STM32F746_PF13_FUNC_FMC_A7>,
<STM32F746_PF12_FUNC_FMC_A6>,
<STM32F746_PF5_FUNC_FMC_A5>,
<STM32F746_PF4_FUNC_FMC_A4>,
<STM32F746_PF3_FUNC_FMC_A3>,
<STM32F746_PF2_FUNC_FMC_A2>,
<STM32F746_PF1_FUNC_FMC_A1>,
<STM32F746_PF0_FUNC_FMC_A0>,
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
<STM32_PINMUX('F',15, AF12)>, /* A9 */
<STM32_PINMUX('F',14, AF12)>, /* A8 */
<STM32_PINMUX('F',13, AF12)>, /* A7 */
<STM32_PINMUX('F',12, AF12)>, /* A6 */
<STM32_PINMUX('F', 5, AF12)>, /* A5 */
<STM32_PINMUX('F', 4, AF12)>, /* A4 */
<STM32_PINMUX('F', 3, AF12)>, /* A3 */
<STM32_PINMUX('F', 2, AF12)>, /* A2 */
<STM32_PINMUX('F', 1, AF12)>, /* A1 */
<STM32_PINMUX('F', 0, AF12)>, /* A0 */
<STM32F746_PH3_FUNC_FMC_SDNE0>,
<STM32F746_PH5_FUNC_FMC_SDNWE>,
<STM32F746_PF11_FUNC_FMC_SDNRAS>,
<STM32F746_PG15_FUNC_FMC_SDNCAS>,
<STM32F746_PH2_FUNC_FMC_SDCKE0>,
<STM32F746_PG8_FUNC_FMC_SDCLK>;
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
<STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
<STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
<STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
<STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
<STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
<STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
slew-rate = <2>;
};
};

97
arch/arm/dts/stm32f769-disco.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright 2016 - Vikas Manocha <vikas.manocha@st.com>
* Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -42,14 +42,16 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
#include "stm32f769-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F769-DISCO board";
compatible = "st,stm32f769-disco", "st,stm32f7";
compatible = "st,stm32f769-disco", "st,stm32f769";
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
@ -60,26 +62,76 @@
aliases {
serial0 = &usart1;
};
leds {
compatible = "gpio-leds";
green {
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
red {
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
};
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
mmc_vcard: mmc_vcard {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cec {
pinctrl-0 = <&cec_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&clk_hse {
clock-frequency = <25000000>;
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&rtc {
status = "okay";
};
&sdio2 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_b>;
pinctrl-1 = <&sdio_pins_od_b>;
bus-width = <4>;
};
&usart1 {
@ -88,12 +140,11 @@
status = "okay";
};
&sdio2 {
&usbotg_hs {
dr_mode = "otg";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_b>;
pinctrl-1 = <&sdio_pins_od_b>;
bus-width = <4>;
max-frequency = <25000000>;
};

11
arch/arm/dts/stm32f769-pinctrl.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include "stm32f7-pinctrl.dtsi"
&pinctrl{
compatible = "st,stm32f769-pinctrl";
};

1341
include/dt-bindings/pinctrl/stm32f746-pinfunc.h
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