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ARM: socfpga: fix data and tag latency values for pl310 cache controller

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The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Dinh Nguyen 2019-03-03 11:02:10 -06:00 committed by Marek Vasut
parent e8e3f2d2d4
commit 532a54e652
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-socfpga/misc.c
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@ -62,8 +62,8 @@ void v7_outer_cache_enable(void)
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x111, &pl310->pl310_tag_latency_ctrl);
writel(0x121, &pl310->pl310_data_latency_ctrl);
writel(0x0, &pl310->pl310_tag_latency_ctrl);
writel(0x10, &pl310->pl310_data_latency_ctrl);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,