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ARM: mvebu: sync db-88f6820-amc.dts with Linux v5.0

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Sync armada-385-db-88f6820-amc.dts with Linux. Retain the
u-boot,dm-pre-reloc and nand differences.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham 2019-04-12 08:47:05 +12:00 committed by Stefan Roese
parent 205c75e88c
commit 937cb9d0a6
1 changed files with 94 additions and 114 deletions
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208
arch/arm/dts/armada-385-db-88f6820-amc.dts
View file

@ -1,51 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 385 development board
* Device Tree file for Marvell Armada 385 AMC board
* (DB-88F6820-AMC)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* Copyright (C) 2017 Allied Telesis Labs
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 AMC";
compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
@ -60,90 +28,88 @@
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
reg = <0x00000000 0x80000000>; /* 2GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
i2c@11000 {
clock-frequency = <100000>;
u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
serial@12000 {
/*
* Exported on the micro USB connector CON16
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
ethernet@34000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
usb@58000 {
status = "okay";
};
ethernet@70000 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
mdio@72004 {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
flash@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
};
pcie {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
&i2c0 {
u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&uart0 {
/*
* Exported on the micro USB connector CON3
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
&eth0 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
&usb0 {
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
&nand_controller {
status = "okay";
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
&pciec {
status = "okay";
};
&pcie1 {
/* Port 0, Lane 0 */
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
@ -154,10 +120,24 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@100000 {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
};
};
};