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armv8: fsl-layerscape: fix SEC QI ICID setup

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The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Laurentiu Tudor 2019-02-26 13:18:33 +02:00 committed by Prabhakar Kushwaha
parent d8d5fdb7b2
commit e82d9ee73a
3 changed files with 3 additions and 4 deletions
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2
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
View file

@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = {
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
SET_QE_ICID(FSL_QE_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),

2
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
View file

@ -41,7 +41,7 @@ struct icid_id_table icid_tbl[] = {
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),

3
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View file

@ -93,8 +93,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, qilcr_ls) + \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)