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ARM: CPU: arm926ejs: Consolidate cache routines to common file

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Four different boards had different options for enabling cache
that were virtually all the same.  This consolidates these
common functions into arch/arm/cpu/arm926ejs/cache.c

This also has the positive side-effect of enabling cache on
the Davinci (da850) boards.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add mach-at91 to the list of consolidations]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Adam Ford 2018-08-16 13:23:11 -05:00 committed by Tom Rini
parent 5f133bb7c5
commit 93b283d49f
7 changed files with 23 additions and 65 deletions
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23
arch/arm/cpu/arm926ejs/cache.c
View file

@ -65,3 +65,26 @@ __weak void l2_cache_disable(void) {}
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
__weak void invalidate_l2_cache(void) {}
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
}
#else
void invalidate_icache_all(void) {}
#endif
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}

8
arch/arm/cpu/arm926ejs/mx25/generic.c
View file

@ -214,14 +214,6 @@ int print_cpuinfo(void)
}
#endif
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
}
#if defined(CONFIG_FEC_MXC)
/*
* Initializes on-chip ethernet controllers.

8
arch/arm/cpu/arm926ejs/mx27/generic.c
View file

@ -374,11 +374,3 @@ void mx27_sd2_init_pins(void)
}
#endif /* CONFIG_MMC_MXC */
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif /* CONFIG_SYS_DCACHE_OFF */

10
arch/arm/cpu/arm926ejs/mxs/mxs.c
View file

@ -49,16 +49,6 @@ void reset_cpu(ulong ignored)
;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
/*
* This function will craft a jumptable at 0x0 which will redirect interrupt
* vectoring to proper location of U-Boot in RAM.

10
arch/arm/cpu/arm926ejs/spear/cpu.c
View file

@ -55,16 +55,6 @@ int arch_cpu_init(void)
return 0;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{

1
arch/arm/mach-at91/arm926ejs/Makefile
View file

@ -16,7 +16,6 @@ obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
obj-y += cache.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o

28
arch/arm/mach-at91/arm926ejs/cache.c
View file

@ -1,28 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#include <linux/types.h>
#include <common.h>
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
}
#ifndef CONFIG_SYS_ICACHE_OFF
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
}
#else
void invalidate_icache_all(void)
{
}
#endif