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- Add support for Amlogic p200 & p201 Reference Designs

Browse source 
- Add Amlogic SoC information display
 - Add support for the Libretech-AC AML-S805X-AC board
 - Add Amlogic AXG reset compatible
 - Add I2C support for Amlogic AXG
 - Fix AXG PIN and BANK pinctrl definitions
 - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
 - Add initial support for Amlogic G12A SoC and U200 board
 - Enable PHY_REALTEK for selected boards
 - Fix Khadas VIM2 README
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Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic

- Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
- Add support for the Libretech-AC AML-S805X-AC board
- Add Amlogic AXG reset compatible
- Add I2C support for Amlogic AXG
- Fix AXG PIN and BANK pinctrl definitions
- Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
- Add initial support for Amlogic G12A SoC and U200 board
- Enable PHY_REALTEK for selected boards
- Fix Khadas VIM2 README
This commit is contained in:
Tom Rini 2019-04-24 12:26:25 -04:00
commit ceb6ddbc73
73 changed files with 4488 additions and 224 deletions
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2
MAINTAINERS
View file

@ -101,7 +101,7 @@ L: u-boot-amlogic@groups.io
T: git git://git.denx.de/u-boot-amlogic.git
F: arch/arm/mach-meson/
F: arch/arm/include/asm/arch-meson/
F: drivers/clk/clk_meson*
F: drivers/clk/meson/
F: drivers/serial/serial_meson.c
F: drivers/reset/reset-meson.c
F: drivers/i2c/meson_i2c.c

6
arch/arm/dts/Makefile
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@ -97,11 +97,15 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
meson-gxl-s905x-p212.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxm-khadas-vim2.dtb \
meson-axg-s400.dtb
meson-axg-s400.dtb \
meson-g12a-u200.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

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arch/arm/dts/meson-g12a-u200.dts Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
/dts-v1/;
#include "meson-g12a.dtsi"
/ {
compatible = "amlogic,u200", "amlogic,g12a";
model = "Amlogic Meson G12A U200 Development Board";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&uart_AO {
status = "okay";
};

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arch/arm/dts/meson-g12a.dtsi Normal file
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@ -0,0 +1,192 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "amlogic,g12a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apb: bus@ff600000 {
compatible = "simple-bus";
reg = <0x0 0xff600000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
periphs: bus@34400 {
compatible = "simple-bus";
reg = <0x0 0x34400 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
};
hiu: bus@3c000 {
compatible = "simple-bus";
reg = <0x0 0x3c000 0x0 0x1400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
hhi: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl",
"simple-mfd", "syscon";
reg = <0 0 0 0x400>;
clkc: clock-controller {
compatible = "amlogic,g12a-clkc";
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "xtal";
};
};
};
};
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_AO_B: serial@4000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
};

7
arch/arm/dts/meson-gxbb-p200-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-gx-u-boot.dtsi"

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arch/arm/dts/meson-gxbb-p200.dts Normal file
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@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
#include <dt-bindings/input/input.h>
/ {
compatible = "amlogic,p200", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P200 Development Board";
avdd18_usb_adc: regulator-avdd18_usb_adc {
compatible = "regulator-fixed";
regulator-name = "AVDD18_USB_ADC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
adc_keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
button-home {
label = "Home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <900000>; /* 50% */
};
button-esc {
label = "Esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <684000>; /* 38% */
};
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <468000>; /* 26% */
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <252000>; /* 14% */
};
button-menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <0>; /* 0% */
};
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c_B {
status = "okay";
pinctrl-0 = <&i2c_b_pins>;
pinctrl-names = "default";
};
&saradc {
status = "okay";
vref-supply = <&avdd18_usb_adc>;
};

7
arch/arm/dts/meson-gxbb-p201-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-gx-u-boot.dtsi"

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arch/arm/dts/meson-gxbb-p201.dts Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
/ {
compatible = "amlogic,p201", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P201 Development Board";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rmii_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
};

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arch/arm/dts/meson-gxbb-p20x.dtsi Normal file
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@ -0,0 +1,247 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*/
#include "meson-gxbb.dtsi"
/ {
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
usb_pwr: regulator-usb-pwrs {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
/* signal name in schematic: USB_PWR_EN */
gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddio_card: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
states = <1800000 0
3300000 1>;
regulator-settling-time-up-us = <10000>;
regulator-settling-time-down-us = <150000>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
cvbs_connector: cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&cec_AO {
status = "okay";
pinctrl-0 = <&ao_cec_pins>;
pinctrl-names = "default";
hdmi-phandle = <&hdmi_tx>;
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_card>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

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arch/arm/dts/meson-gxl-s805x-libretech-ac.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905x.dtsi"
/ {
compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
"amlogic,meson-gxl";
model = "Libre Computer Board AML-S805X-AC";
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
spi0 = &spifc;
};
chosen {
stdout-path = "serial0:115200n8";
};
cvbs-connector {
/*
* The pads are present but no connector is soldered on
* 2J2, so keep this off by default.
*/
status = "disabled";
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
dc_5v: regulator-dc_5v {
compatible = "regulator-fixed";
regulator-name = "DC_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};
vcck: regulator-vcck {
compatible = "regulator-fixed";
regulator-name = "VCCK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_5v>;
/*
* This is controlled by GPIOAO_9 we reserve this but
* claiming it as done below reset the board anyway
* Need to investigate this
*
* gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
* enable-active-high;
*/
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_5v>;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
};
&cec_AO {
status = "okay";
pinctrl-0 = <&ao_cec_pins>;
pinctrl-names = "default";
hdmi-phandle = <&hdmi_tx>;
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
status = "okay";
};
&internal_phy {
pinctrl-0 = <&eth_link_led_pins>, <&eth_act_led_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&gpio_ao {
gpio-line-names = "UART TX",
"UART RX",
"7J1 Header Pin31",
"", "", "", "",
"IR In",
"HDMI CEC",
"5V VCCK Regulator",
/* GPIO_TEST_N */
"";
};
&gpio {
gpio-line-names = /* Bank GPIOZ */
"", "", "", "", "", "", "",
"", "", "", "", "", "", "",
"Eth Link LED", "Eth Activity LED",
/* Bank GPIOH */
"HDMI HPD", "HDMI SDA", "HDMI SCL",
"", "7J1 Header Pin13",
"7J1 Header Pin15",
"7J1 Header Pin7",
"7J1 Header Pin12",
"7J1 Header Pin16",
"7J1 Header Pin18",
/* Bank BOOT */
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
"eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
"eMMC Clk", "eMMC Reset", "eMMC CMD",
"SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk",
"", "SPI NOR Chip Select",
/* Bank CARD */
"", "", "", "", "", "", "",
/* Bank GPIODV */
"", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "",
"7J1 Header Pin27", "7J1 Header Pin28", "",
"7J1 Header Pin29",
"VCCK Regulator", "VDDEE Regulator",
/* Bank GPIOX */
"7J1 Header Pin22", "7J1 Header Pin26",
"7J1 Header Pin36", "7J1 Header Pin38",
"7J1 Header Pin40", "7J1 Header Pin37",
"7J1 Header Pin33", "7J1 Header Pin35",
"7J1 Header Pin19", "7J1 Header Pin21",
"7J1 Header Pin24", "7J1 Header Pin23",
"7J1 Header Pin8", "7J1 Header Pin10",
"", "", "7J1 Header Pin32", "", "",
/* Bank GPIOCLK */
"", "";
};
&saradc {
status = "okay";
vref-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&spifc {
status = "okay";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <3000000>;
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0 {
status = "okay";
};

70
arch/arm/dts/meson-gxl.dtsi
View file

@ -75,6 +75,10 @@
};
};
&efuse {
clocks = <&clkc CLKID_EFUSE>;
};
&ethmac {
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
@ -112,6 +116,7 @@
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
bias-disable;
};
};
@ -120,6 +125,7 @@
groups = "uart_cts_ao_a",
"uart_rts_ao_a";
function = "uart_ao";
bias-disable;
};
};
@ -127,6 +133,7 @@
mux {
groups = "uart_tx_ao_b", "uart_rx_ao_b";
function = "uart_ao_b";
bias-disable;
};
};
@ -134,6 +141,7 @@
mux {
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
function = "uart_ao_b";
bias-disable;
};
};
@ -142,6 +150,7 @@
groups = "uart_cts_ao_b",
"uart_rts_ao_b";
function = "uart_ao_b";
bias-disable;
};
};
@ -149,6 +158,7 @@
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
bias-disable;
};
};
@ -157,6 +167,7 @@
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
bias-disable;
};
};
@ -164,6 +175,7 @@
mux {
groups = "pwm_ao_a_3";
function = "pwm_ao_a";
bias-disable;
};
};
@ -171,6 +183,7 @@
mux {
groups = "pwm_ao_a_8";
function = "pwm_ao_a";
bias-disable;
};
};
@ -178,6 +191,7 @@
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
bias-disable;
};
};
@ -185,6 +199,7 @@
mux {
groups = "pwm_ao_b_6";
function = "pwm_ao_b";
bias-disable;
};
};
@ -192,6 +207,7 @@
mux {
groups = "i2s_out_ch23_ao";
function = "i2s_out_ao";
bias-disable;
};
};
@ -199,6 +215,7 @@
mux {
groups = "i2s_out_ch45_ao";
function = "i2s_out_ao";
bias-disable;
};
};
@ -206,6 +223,7 @@
mux {
groups = "spdif_out_ao_6";
function = "spdif_out_ao";
bias-disable;
};
};
@ -213,6 +231,7 @@
mux {
groups = "spdif_out_ao_9";
function = "spdif_out_ao";
bias-disable;
};
};
@ -220,6 +239,7 @@
mux {
groups = "ao_cec";
function = "cec_ao";
bias-disable;
};
};
@ -227,6 +247,7 @@
mux {
groups = "ee_cec";
function = "cec_ao";
bias-disable;
};
};
};
@ -239,6 +260,8 @@
&clkc_AO {
compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
&gpio_intc {
@ -263,6 +286,8 @@
clkc: clock-controller {
compatible = "amlogic,gxl-clkc";
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "xtal";
};
};
@ -306,6 +331,7 @@
"emmc_cmd",
"emmc_clk";
function = "emmc";
bias-disable;
};
};
@ -313,6 +339,7 @@
mux {
groups = "emmc_ds";
function = "emmc";
bias-disable;
};
};
@ -320,9 +347,6 @@
mux {
groups = "BOOT_8";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "BOOT_8";
bias-pull-down;
};
};
@ -334,6 +358,7 @@
"nor_c",
"nor_cs";
function = "nor";
bias-disable;
};
};
@ -343,6 +368,7 @@
"spi_mosi",
"spi_sclk";
function = "spi";
bias-disable;
};
};
@ -350,6 +376,7 @@
mux {
groups = "spi_ss0";
function = "spi";
bias-disable;
};
};
@ -362,6 +389,7 @@
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
bias-disable;
};
};
@ -369,9 +397,6 @@
mux {
groups = "CARD_2";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "CARD_2";
bias-pull-down;
};
};
@ -385,6 +410,7 @@
"sdio_cmd",
"sdio_clk";
function = "sdio";
bias-disable;
};
};
@ -392,9 +418,6 @@
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "GPIOX_4";
bias-pull-down;
};
};
@ -403,6 +426,7 @@
mux {
groups = "sdio_irq";
function = "sdio";
bias-disable;
};
};
@ -411,6 +435,7 @@
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
bias-disable;
};
};
@ -419,6 +444,7 @@
groups = "uart_cts_a",
"uart_rts_a";
function = "uart_a";
bias-disable;
};
};
@ -427,6 +453,7 @@
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
bias-disable;
};
};
@ -435,6 +462,7 @@
groups = "uart_cts_b",
"uart_rts_b";
function = "uart_b";
bias-disable;
};
};
@ -443,6 +471,7 @@
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
bias-disable;
};
};
@ -451,6 +480,7 @@
groups = "uart_cts_c",
"uart_rts_c";
function = "uart_c";
bias-disable;
};
};
@ -459,6 +489,7 @@
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
bias-disable;
};
};
@ -467,6 +498,7 @@
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
bias-disable;
};
};
@ -475,6 +507,7 @@
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
bias-disable;
};
};
@ -495,6 +528,7 @@
"eth_txd2",
"eth_txd3";
function = "eth";
bias-disable;
};
};
@ -502,6 +536,7 @@
mux {
groups = "eth_link_led";
function = "eth_led";
bias-disable;
};
};
@ -516,6 +551,7 @@
mux {
groups = "pwm_a";
function = "pwm_a";
bias-disable;
};
};
@ -523,6 +559,7 @@
mux {
groups = "pwm_b";
function = "pwm_b";
bias-disable;
};
};
@ -530,6 +567,7 @@
mux {
groups = "pwm_c";
function = "pwm_c";
bias-disable;
};
};
@ -537,6 +575,7 @@
mux {
groups = "pwm_d";
function = "pwm_d";
bias-disable;
};
};
@ -544,6 +583,7 @@
mux {
groups = "pwm_e";
function = "pwm_e";
bias-disable;
};
};
@ -551,6 +591,7 @@
mux {
groups = "pwm_f_clk";
function = "pwm_f";
bias-disable;
};
};
@ -558,6 +599,7 @@
mux {
groups = "pwm_f_x";
function = "pwm_f";
bias-disable;
};
};
@ -565,6 +607,7 @@
mux {
groups = "hdmi_hpd";
function = "hdmi_hpd";
bias-disable;
};
};
@ -572,6 +615,7 @@
mux {
groups = "hdmi_sda", "hdmi_scl";
function = "hdmi_i2c";
bias-disable;
};
};
@ -579,6 +623,7 @@
mux {
groups = "i2s_am_clk";
function = "i2s_out";
bias-disable;
};
};
@ -586,6 +631,7 @@
mux {
groups = "i2s_out_ao_clk";
function = "i2s_out";
bias-disable;
};
};
@ -593,6 +639,7 @@
mux {
groups = "i2s_out_lr_clk";
function = "i2s_out";
bias-disable;
};
};
@ -600,12 +647,14 @@
mux {
groups = "i2s_out_ch01";
function = "i2s_out";
bias-disable;
};
};
i2sout_ch23_z_pins: i2sout_ch23_z {
mux {
groups = "i2sout_ch23_z";
function = "i2s_out";
bias-disable;
};
};
@ -613,6 +662,7 @@
mux {
groups = "i2sout_ch45_z";
function = "i2s_out";
bias-disable;
};
};
@ -620,6 +670,7 @@
mux {
groups = "i2sout_ch67_z";
function = "i2s_out";
bias-disable;
};
};
@ -627,6 +678,7 @@
mux {
groups = "spdif_out_h";
function = "spdif_out";
bias-disable;
};
};
};

104
arch/arm/include/asm/arch-meson/clock-g12a.h Normal file
View file

@ -0,0 +1,104 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 - AmLogic, Inc.
* Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
* Copyright 2018 - BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef _ARCH_MESON_CLOCK_G12A_H_
#define _ARCH_MESON_CLOCK_G12A_H_
/*
* Clock controller register offsets
*
* Register offsets from the data sheet are listed in comment blocks below.
* Those offsets must be multiplied by 4 before adding them to the base address
* to get the right value
*/
#define HHI_MIPI_CNTL0 0x000
#define HHI_MIPI_CNTL1 0x004
#define HHI_MIPI_CNTL2 0x008
#define HHI_MIPI_STS 0x00C
#define HHI_GP0_PLL_CNTL0 0x040
#define HHI_GP0_PLL_CNTL1 0x044
#define HHI_GP0_PLL_CNTL2 0x048
#define HHI_GP0_PLL_CNTL3 0x04C
#define HHI_GP0_PLL_CNTL4 0x050
#define HHI_GP0_PLL_CNTL5 0x054
#define HHI_GP0_PLL_CNTL6 0x058
#define HHI_GP0_PLL_STS 0x05C
#define HHI_PCIE_PLL_CNTL0 0x098
#define HHI_PCIE_PLL_CNTL1 0x09C
#define HHI_PCIE_PLL_CNTL2 0x0A0
#define HHI_PCIE_PLL_CNTL3 0x0A4
#define HHI_PCIE_PLL_CNTL4 0x0A8
#define HHI_PCIE_PLL_CNTL5 0x0AC
#define HHI_PCIE_PLL_STS 0x0B8
#define HHI_HIFI_PLL_CNTL0 0x0D8
#define HHI_HIFI_PLL_CNTL1 0x0DC
#define HHI_HIFI_PLL_CNTL2 0x0E0
#define HHI_HIFI_PLL_CNTL3 0x0E4
#define HHI_HIFI_PLL_CNTL4 0x0E8
#define HHI_HIFI_PLL_CNTL5 0x0EC
#define HHI_HIFI_PLL_CNTL6 0x0F0
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12C
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_OTHER2 0x154
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1A0
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_HDMI_CLK_CNTL 0x1CC
#define HHI_VDEC_CLK_CNTL 0x1E0
#define HHI_VDEC2_CLK_CNTL 0x1E4
#define HHI_VDEC3_CLK_CNTL 0x1E8
#define HHI_VDEC4_CLK_CNTL 0x1EC
#define HHI_HDCP22_CLK_CNTL 0x1F0
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_VPU_CLKB_CNTL 0x20C
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL0 0x278
#define HHI_MPLL_CNTL1 0x27C
#define HHI_MPLL_CNTL2 0x280
#define HHI_MPLL_CNTL3 0x284
#define HHI_MPLL_CNTL4 0x288
#define HHI_MPLL_CNTL5 0x28c
#define HHI_MPLL_CNTL6 0x290
#define HHI_MPLL_CNTL7 0x294
#define HHI_MPLL_CNTL8 0x298
#define HHI_FIX_PLL_CNTL0 0x2A0
#define HHI_FIX_PLL_CNTL1 0x2A4
#define HHI_FIX_PLL_CNTL3 0x2AC
#define HHI_SYS_PLL_CNTL0 0x2f4
#define HHI_SYS_PLL_CNTL1 0x2f8
#define HHI_SYS_PLL_CNTL2 0x2fc
#define HHI_SYS_PLL_CNTL3 0x300
#define HHI_SYS_PLL_CNTL4 0x304
#define HHI_SYS_PLL_CNTL5 0x308
#define HHI_SYS_PLL_CNTL6 0x30c
#define HHI_HDMI_PLL_CNTL0 0x320
#define HHI_HDMI_PLL_CNTL1 0x324
#define HHI_HDMI_PLL_CNTL2 0x328
#define HHI_HDMI_PLL_CNTL3 0x32c
#define HHI_HDMI_PLL_CNTL4 0x330
#define HHI_HDMI_PLL_CNTL5 0x334
#define HHI_HDMI_PLL_CNTL6 0x338
#define HHI_SPICC_CLK_CNTL 0x3dc
#endif

66
arch/arm/include/asm/arch-meson/g12a.h Normal file
View file

@ -0,0 +1,66 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __G12A_H__
#define __G12A_H__
#define G12A_AOBUS_BASE 0xff800000
#define G12A_PERIPHS_BASE 0xff634400
#define G12A_HIU_BASE 0xff63c000
#define G12A_ETH_PHY_BASE 0xff64c000
#define G12A_ETH_BASE 0xff3f0000
/* Always-On Peripherals registers */
#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
#define G12A_AO_BOOT_DEVICE 0xF
#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
#define G12A_AO_MEM_SIZE_SHIFT 16
#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
/* Peripherals registers */
#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
#define G12A_ETH_REG_0_CLK_EN BIT(12)
#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
/* HIU registers */
#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
/* Ethernet memory power domain */
#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
#endif /* __G12A_H__ */

11
arch/arm/mach-meson/Kconfig
View file

@ -41,7 +41,13 @@ config MESON_AXG
bool "AXG"
select MESON64_COMMON
help
Select this if your SoC is an A113X/D
Select this if your SoC is an A113X/D
config MESON_G12A
bool "G12A"
select MESON64_COMMON
help
Select this if your SoC is an S905X/D2
endchoice
@ -61,10 +67,11 @@ config SYS_VENDOR
config SYS_BOARD
string "Board name"
default "odroid-c2" if MESON_GXBB
default "p200" if MESON_GXBB
default "p212" if MESON_GXL
default "q200" if MESON_GXM
default "s400" if MESON_AXG
default "u200" if MESON_G12A
default ""
help
This option contains information about board name.

3
arch/arm/mach-meson/Makefile
View file

@ -2,6 +2,7 @@
#
# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
obj-y += board-common.o sm.o
obj-y += board-common.o sm.o board-info.o
obj-$(CONFIG_MESON_GX) += board-gx.o
obj-$(CONFIG_MESON_AXG) += board-axg.o
obj-$(CONFIG_MESON_G12A) += board-g12a.o

150
arch/arm/mach-meson/board-g12a.c Normal file
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@ -0,0 +1,150 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
#include <asm/arch/g12a.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
int meson_get_boot_device(void)
{
return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
}
/* Configure the reserved memory zones exported by the secure registers
* into EFI and DTB reserved memory entries.
*/
void meson_init_reserved_memory(void *fdt)
{
u64 bl31_size, bl31_start;
u64 bl32_size, bl32_start;
u32 reg;
/*
* Get ARM Trusted Firmware reserved memory zones in :
* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
*/
reg = readl(G12A_AO_SEC_GP_CFG3);
bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
>> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
bl31_start = readl(G12A_AO_SEC_GP_CFG5);
bl32_start = readl(G12A_AO_SEC_GP_CFG4);
/* Add BL31 reserved zone */
if (bl31_start && bl31_size)
meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
/* Add BL32 reserved zone */
if (bl32_start && bl32_size)
meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
}
phys_size_t get_effective_memsize(void)
{
/* Size is reported in MiB, convert it in bytes */
return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
}
static struct mm_region g12a_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xf0000000UL,
.phys = 0xf0000000UL,
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = g12a_mem_map;
static void g12a_enable_external_mdio(void)
{
writel(0x0, ETH_PHY_CNTL2);
}
static void g12a_enable_internal_mdio(void)
{
/* Fire up the PHY PLL */
writel(0x29c0040a, ETH_PLL_CNTL0);
writel(0x927e0000, ETH_PLL_CNTL1);
writel(0xac5f49e5, ETH_PLL_CNTL2);
writel(0x00000000, ETH_PLL_CNTL3);
writel(0x00000000, ETH_PLL_CNTL4);
writel(0x20200000, ETH_PLL_CNTL5);
writel(0x0000c002, ETH_PLL_CNTL6);
writel(0x00000023, ETH_PLL_CNTL7);
writel(0x39c0040a, ETH_PLL_CNTL0);
writel(0x19c0040a, ETH_PLL_CNTL0);
/* Select the internal MDIO */
writel(0x33000180, ETH_PHY_CNTL0);
writel(0x00074043, ETH_PHY_CNTL1);
writel(0x00000260, ETH_PHY_CNTL2);
}
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
G12A_ETH_REG_0_TX_PHASE(1) |
G12A_ETH_REG_0_TX_RATIO(4) |
G12A_ETH_REG_0_PHY_CLK_EN |
G12A_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
G12A_ETH_REG_0_INVERT_RMII_CLK |
G12A_ETH_REG_0_CLK_EN);
/* Use G12A RMII Internal PHY */
if (flags & MESON_USE_INTERNAL_RMII_PHY)
g12a_enable_internal_mdio();
else
g12a_enable_external_mdio();
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
/* Enable power gate */
clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
}

166
arch/arm/mach-meson/board-info.c Normal file
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@ -0,0 +1,166 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Julien Masson <jmasson@baylibre.com>
* (C) Copyright 2019 Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <asm/io.h>
#include <dm.h>
#include <linux/bitfield.h>
#include <regmap.h>
#include <syscon.h>
#define AO_SEC_SD_CFG8 0xe0
#define AO_SEC_SOCINFO_OFFSET AO_SEC_SD_CFG8
#define SOCINFO_MAJOR GENMASK(31, 24)
#define SOCINFO_PACK GENMASK(23, 16)
#define SOCINFO_MINOR GENMASK(15, 8)
#define SOCINFO_MISC GENMASK(7, 0)
static const struct meson_gx_soc_id {
const char *name;
unsigned int id;
} soc_ids[] = {
{ "GXBB", 0x1f },
{ "GXTVBB", 0x20 },
{ "GXL", 0x21 },
{ "GXM", 0x22 },
{ "TXL", 0x23 },
{ "TXLX", 0x24 },
{ "AXG", 0x25 },
{ "GXLX", 0x26 },
{ "TXHD", 0x27 },
{ "G12A", 0x28 },
{ "G12B", 0x29 },
};
static const struct meson_gx_package_id {
const char *name;
unsigned int major_id;
unsigned int pack_id;
unsigned int pack_mask;
} soc_packages[] = {
{ "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */
{ "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */
{ "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */
{ "S905D", 0x21, 0, 0xf0 },
{ "S905X", 0x21, 0x80, 0xf0 },
{ "S905W", 0x21, 0xa0, 0xf0 },
{ "S905L", 0x21, 0xc0, 0xf0 },
{ "S905M2", 0x21, 0xe0, 0xf0 },
{ "S805X", 0x21, 0x30, 0xf0 },
{ "S805Y", 0x21, 0xb0, 0xf0 },
{ "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */
{ "962X", 0x24, 0x10, 0xf0 },
{ "962E", 0x24, 0x20, 0xf0 },
{ "A113X", 0x25, 0x37, 0xff },
{ "A113D", 0x25, 0x22, 0xff },
{ "S905D2", 0x28, 0x10, 0xf0 },
{ "S905X2", 0x28, 0x40, 0xf0 },
{ "S922X", 0x29, 0x40, 0xf0 },
};
DECLARE_GLOBAL_DATA_PTR;
static inline unsigned int socinfo_to_major(u32 socinfo)
{
return FIELD_GET(SOCINFO_MAJOR, socinfo);
}
static inline unsigned int socinfo_to_minor(u32 socinfo)
{
return FIELD_GET(SOCINFO_MINOR, socinfo);
}
static inline unsigned int socinfo_to_pack(u32 socinfo)
{
return FIELD_GET(SOCINFO_PACK, socinfo);
}
static inline unsigned int socinfo_to_misc(u32 socinfo)
{
return FIELD_GET(SOCINFO_MISC, socinfo);
}
static const char *socinfo_to_package_id(u32 socinfo)
{
unsigned int pack = socinfo_to_pack(socinfo);
unsigned int major = socinfo_to_major(socinfo);
int i;
for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
if (soc_packages[i].major_id == major &&
soc_packages[i].pack_id ==
(pack & soc_packages[i].pack_mask))
return soc_packages[i].name;
}
return "Unknown";
}
static const char *socinfo_to_soc_id(u32 socinfo)
{
unsigned int id = socinfo_to_major(socinfo);
int i;
for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
if (soc_ids[i].id == id)
return soc_ids[i].name;
}
return "Unknown";
}
static void print_board_model(void)
{
const char *model;
model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
printf("Model: %s\n", model ? model : "Unknown");
}
int show_board_info(void)
{
struct regmap *regmap;
int nodeoffset, ret;
ofnode node;
unsigned int socinfo;
/* find the offset of compatible node */
nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"amlogic,meson-gx-ao-secure");
if (nodeoffset < 0)
return 0;
/* check if chip-id is available */
if (!fdt_getprop(gd->fdt_blob, nodeoffset, "amlogic,has-chip-id", NULL))
return 0;
/* get regmap from the syscon node */
node = offset_to_ofnode(nodeoffset);
regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap)) {
printf("%s: failed to get regmap\n", __func__);
return 0;
}
/* read soc info */
ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo);
if (ret && !socinfo) {
printf("%s: invalid chipid value\n", __func__);
return 0;
}
/* print board information */
print_board_model();
printf("Soc: Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n",
socinfo_to_soc_id(socinfo),
socinfo_to_package_id(socinfo),
socinfo_to_major(socinfo),
socinfo_to_minor(socinfo),
socinfo_to_pack(socinfo),
socinfo_to_misc(socinfo));
return 0;
}

8
arch/sandbox/include/asm/test.h
View file

@ -59,14 +59,6 @@ void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
/*
* sandbox_timer_add_offset()
*
* Allow tests to add to the time reported through lib/time.c functions
* offset: number of milliseconds to advance the system time
*/
void sandbox_timer_add_offset(unsigned long offset);
/**
* sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
*

6
board/amlogic/odroid-c2/MAINTAINERS → board/amlogic/p200/MAINTAINERS
View file

@ -1,8 +1,8 @@
ODROID-C2
P200
M: Beniamino Galvani <b.galvani@gmail.com>
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/odroid-c2/
F: include/configs/odroid-c2.h
F: board/amlogic/p200/
F: configs/nanopi-k2_defconfig
F: configs/odroid-c2_defconfig
F: configs/p200_defconfig

2
board/amlogic/odroid-c2/Makefile → board/amlogic/p200/Makefile
View file

@ -2,4 +2,4 @@
#
# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
obj-y := odroid-c2.o
obj-y := p200.o

0
board/amlogic/odroid-c2/README.nanopi-k2 → board/amlogic/p200/README.nanopi-k2
View file

0
board/amlogic/odroid-c2/README.odroid-c2 → board/amlogic/p200/README.odroid-c2
View file

103
board/amlogic/p200/README.p200 Normal file
View file

@ -0,0 +1,103 @@
U-Boot for Amlogic P200
=======================
P200 is a reference board manufactured by Amlogic with the following
specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- Gigabit Ethernet
- HDMI 2.0 4K/60Hz display
- 2 x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
- SDIO WiFi Module
- CVBS+Stereo Audio Jack
Schematics are available from Amlogic on demand.
Currently the u-boot port supports the following devices:
- serial
- eMMC, microSD
- Ethernet
- I2C
- Regulators
- Reset controller
- Clock controller
- USB Host
- ADC
u-boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make p200_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
> cd amlogic-u-boot
> make gxb_p200_v1_defconfig
> make
> export FIPDIR=$PWD/fip
Go back to mainline U-boot source tree then :
> mkdir fip
> cp $FIPDIR/gxl/bl2.bin fip/
> cp $FIPDIR/gxl/acs.bin fip/
> cp $FIPDIR/gxl/bl21.bin fip/
> cp $FIPDIR/gxl/bl30.bin fip/
> cp $FIPDIR/gxl/bl301.bin fip/
> cp $FIPDIR/gxl/bl31.img fip/
> cp u-boot.bin fip/bl33.bin
> $FIPDIR/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
> $FIPDIR/blx_fix.sh \
fip/bl2_acs.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/bl21.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
> $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
> $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

0
board/amlogic/odroid-c2/odroid-c2.c → board/amlogic/p200/p200.c
View file

5
board/amlogic/p201/MAINTAINERS Normal file
View file

@ -0,0 +1,5 @@
P201
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/p201/
F: configs/p201_defconfig

5
board/amlogic/p201/Makefile Normal file
View file

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
obj-y := p201.o

103
board/amlogic/p201/README.p201 Normal file
View file

@ -0,0 +1,103 @@
U-Boot for Amlogic P201
=======================
P201 is a reference board manufactured by Amlogic with the following
specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- 10/100 Ethernet
- HDMI 2.0 4K/60Hz display
- 2 x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
- SDIO WiFi Module
- CVBS+Stereo Audio Jack
Schematics are available from Amlogic on demand.
Currently the u-boot port supports the following devices:
- serial
- eMMC, microSD
- Ethernet
- I2C
- Regulators
- Reset controller
- Clock controller
- USB Host
- ADC
u-boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make p201_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
> cd amlogic-u-boot
> make gxb_p201_v1_defconfig
> make
> export FIPDIR=$PWD/fip
Go back to mainline U-boot source tree then :
> mkdir fip
> cp $FIPDIR/gxl/bl2.bin fip/
> cp $FIPDIR/gxl/acs.bin fip/
> cp $FIPDIR/gxl/bl21.bin fip/
> cp $FIPDIR/gxl/bl30.bin fip/
> cp $FIPDIR/gxl/bl301.bin fip/
> cp $FIPDIR/gxl/bl31.img fip/
> cp u-boot.bin fip/bl33.bin
> $FIPDIR/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
> $FIPDIR/blx_fix.sh \
fip/bl2_acs.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/bl21.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
> $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
> $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
> $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

43
board/amlogic/p201/p201.c Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
#include <asm/arch/mem.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
#define EFUSE_MAC_OFFSET 52
#define EFUSE_MAC_SIZE 6
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_eth_init(PHY_INTERFACE_MODE_RMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
return 0;
}

1
board/amlogic/p212/MAINTAINERS
View file

@ -4,5 +4,6 @@ S: Maintained
F: board/amlogic/p212/
F: include/configs/p212.h
F: configs/khadas-vim_defconfig
F: configs/libretech-ac_defconfig
F: configs/libretech-cc_defconfig
F: configs/p212_defconfig

103
board/amlogic/p212/README.libretech-ac Normal file
View file

@ -0,0 +1,103 @@
U-Boot for LibreTech AC
=======================
LibreTech AC is a single board computer manufactured by Libre Technology
with the following specifications:
- Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
- ARM Mali 450 GPU
- 512MiB DDR4 SDRAM
- 10/100 Ethernet
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 4 x USB 2.0 Host
- eMMC, SPI NOR Flash
- Infrared receiver
Schematics are available on the manufacturer website.
Currently the U-Boot port supports the following devices:
- serial
- eMMC
- Ethernet
- USB
U-Boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make libretech-ac_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot
> cd amlogic-u-boot
> wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh
> make libretech_ac_defconfig
> make
> export UBOOTDIR=$PWD
Download the latest Amlogic Buildroot package, and extract it :
> wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz
> tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
> export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
Go back to mainline U-Boot source tree then :
> mkdir fip
> cp $UBOOTDIR/build/scp_task/bl301.bin fip/
> cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/
> cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/
> cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/
> cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/
> cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/
> cp u-boot.bin fip/bl33.bin
> sh $UBOOTDIR/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
> sh $UBOOTDIR/blx_fix.sh \
fip/bl2_acs.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/bl21.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
> $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
> $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
> $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
> $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

4
board/amlogic/q200/README.khadas-vim2
View file

@ -48,9 +48,9 @@ the git tree published by the board vendor:
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
> git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot
> cd vim-u-boot
> make kvim_defconfig
> make kvim2_defconfig
> make
> export FIPDIR=$PWD/fip

5
board/amlogic/u200/MAINTAINERS Normal file
View file

@ -0,0 +1,5 @@
U200
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
F: board/amlogic/u200/
F: configs/u200_defconfig

6
board/amlogic/u200/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2016 BayLibre, SAS
# Author: Neil Armstrong <narmstrong@baylibre.com>
obj-y := u200.o

128
board/amlogic/u200/README Normal file
View file

@ -0,0 +1,128 @@
U-Boot for Amlogic U200
=======================
U200 is a reference board manufactured by Amlogic with the following
specifications:
- Amlogic S905D2 ARM Cortex-A53 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- 1 x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module
- MIPI DSI Connector
- Audio HAT Connector
- PCI-E M.2 Connector
Schematics are available from Amlogic on demand.
Currently the u-boot port supports the following devices:
- serial
- Ethernet
- Regulators
- Clock controller
u-boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make u200_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
> cd amlogic-u-boot
> make g12a_u200_v1_defconfig
> make
> export UBOOTDIR=$PWD
Download the latest Amlogic Buildroot package, and extract it :
> wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
> tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
> export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
> export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
Go back to mainline U-Boot source tree then :
> mkdir fip
> wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
> cp $UBOOTDIR/build/scp_task/bl301.bin fip/
> cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
> cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
> cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
> cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
> cp $FIPDIR/g12a/ddr3_1d.fw fip/
> cp $FIPDIR/g12a/ddr4_1d.fw fip/
> cp $FIPDIR/g12a/ddr4_2d.fw fip/
> cp $FIPDIR/g12a/diag_lpddr4.fw fip/
> cp $FIPDIR/g12a/lpddr4_1d.fw fip/
> cp $FIPDIR/g12a/lpddr4_2d.fw fip/
> cp $FIPDIR/g12a/piei.fw fip/
> cp u-boot.bin fip/bl33.bin
> sh fip/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> sh fip/blx_fix.sh \
fip/bl2.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/acs.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
--output fip/bl30_new.bin.g12a.enc \
--level v3
> $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
--output fip/bl30_new.bin.enc \
--level v3 --type bl30
> $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
--output fip/bl31.img.enc \
--level v3 --type bl31
> $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
--output fip/bl33.bin.enc \
--level v3 --type bl33
> $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
--output fip/bl2.n.bin.sig
> $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc \
--ddrfw1 fip/ddr4_1d.fw \
--ddrfw2 fip/ddr4_2d.fw \
--ddrfw3 fip/ddr3_1d.fw \
--ddrfw4 fip/piei.fw \
--ddrfw5 fip/lpddr4_1d.fw \
--ddrfw6 fip/lpddr4_2d.fw \
--ddrfw7 fip/diag_lpddr4.fw \
--level v3
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

22
board/amlogic/u200/u200.c Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/arch/axg.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
#include <asm/arch/mem.h>
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_USE_INTERNAL_RMII_PHY);
return 0;
}

2
board/sandbox/sandbox.c
View file

@ -31,7 +31,7 @@ void flush_cache(unsigned long start, unsigned long size)
/* system timer offset in ms */
static unsigned long sandbox_timer_offset;
void sandbox_timer_add_offset(unsigned long offset)
void timer_test_add_offset(unsigned long offset)
{
sandbox_timer_offset += offset;
}

3
configs/khadas-vim2_defconfig
View file

@ -11,7 +11,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
@ -31,6 +31,7 @@ CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y

2
configs/khadas-vim_defconfig
View file

@ -11,7 +11,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y

74
configs/libretech-ac_defconfig Normal file
View file

@ -0,0 +1,74 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="libretech-ac"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_GXL=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" libretech-ac"
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_MESON=y
CONFIG_VIDEO_DT_SIMPLEFB=y
CONFIG_OF_LIBFDT_OVERLAY=y

2
configs/libretech-cc_defconfig
View file

@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ADC=y

3
configs/nanopi-k2_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
@ -28,6 +28,7 @@ CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y

3
configs/odroid-c2_defconfig
View file

@ -10,7 +10,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
@ -29,6 +29,7 @@ CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y

41
configs/p200_defconfig Normal file
View file

@ -0,0 +1,41 @@
CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p200"
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p200"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_BOARD="p200"

41
configs/p201_defconfig Normal file
View file

@ -0,0 +1,41 @@
CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" p201"
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p201"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_BOARD="p201"

2
configs/p212_defconfig
View file

@ -11,7 +11,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y

3
configs/s400_defconfig
View file

@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
@ -26,6 +26,7 @@ CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_DM_REGULATOR=y

40
configs/u200_defconfig Normal file
View file

@ -0,0 +1,40 @@
CONFIG_ARM=y
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_G12A=y
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" u200"
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=8
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
drivers/clk/Kconfig
View file

@ -101,6 +101,7 @@ config CLK_STM32MP1
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"

2
drivers/clk/Makefile
View file

@ -12,7 +12,7 @@ obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o
obj-$(CONFIG_ARCH_MESON) += meson/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/

23
drivers/clk/meson/Kconfig Normal file
View file

@ -0,0 +1,23 @@
config CLK_MESON_GX
bool "Enable clock support for Amlogic GX"
depends on CLK && ARCH_MESON
default MESON_GX
help
Enable clock support for the Amlogic GX SoC family, such as
the S905, S905X/D and S912.
config CLK_MESON_AXG
bool "Enable clock support for Amlogic AXG"
depends on CLK && ARCH_MESON
default MESON_AXG
help
Enable clock support for the Amlogic AXG SoC family, such as
the A113X/D
config CLK_MESON_G12A
bool "Enable clock support for Amlogic G12A"
depends on CLK && ARCH_MESON
default MESON_G12A
help
Enable clock support for the Amlogic G12A SoC family, such as
the S905X/D2

9
drivers/clk/meson/Makefile Normal file
View file

@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2019 Baylibre, SAS
# Jerome Brunet <jbrunet@baylibre.com>
obj-$(CONFIG_CLK_MESON_GX) += gxbb.o
obj-$(CONFIG_CLK_MESON_AXG) += axg.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o

0
drivers/clk/clk_meson_axg.c → drivers/clk/meson/axg.c
View file

0
drivers/clk/clk_meson.h → drivers/clk/meson/clk_meson.h
View file

315
drivers/clk/meson/g12a.c Normal file
View file

@ -0,0 +1,315 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
* (C) Copyright 2018 - BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <asm/arch/clock-g12a.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <dm.h>
#include <regmap.h>
#include <syscon.h>
#include <div64.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include "clk_meson.h"
#define XTAL_RATE 24000000
struct meson_clk {
struct regmap *map;
};
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
#define NUM_CLKS 178
static struct meson_gate gates[NUM_CLKS] = {
/* Everything Else (EE) domain gates */
MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
/* Peripheral Gates */
MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
};
static int meson_set_gate(struct clk *clk, bool on)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct meson_gate *gate;
if (clk->id >= ARRAY_SIZE(gates))
return -ENOENT;
gate = &gates[clk->id];
if (gate->reg == 0)
return 0;
regmap_update_bits(priv->map, gate->reg,
BIT(gate->bit), on ? BIT(gate->bit) : 0);
return 0;
}
static int meson_clk_enable(struct clk *clk)
{
return meson_set_gate(clk, true);
}
static int meson_clk_disable(struct clk *clk)
{
return meson_set_gate(clk, false);
}
static unsigned long meson_clk81_get_rate(struct clk *clk)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
unsigned long parent_rate;
uint reg;
int parents[] = {
-1,
-1,
CLKID_FCLK_DIV7,
CLKID_MPLL1,
CLKID_MPLL2,
CLKID_FCLK_DIV4,
CLKID_FCLK_DIV3,
CLKID_FCLK_DIV5
};
/* mux */
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
reg = (reg >> 12) & 7;
switch (reg) {
case 0:
parent_rate = XTAL_RATE;
break;
case 1:
return -ENOENT;
default:
parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
}
/* divider */
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
reg = reg & ((1 << 7) - 1);
return parent_rate / reg;
}
static long mpll_rate_from_params(unsigned long parent_rate,
unsigned long sdm,
unsigned long n2)
{
unsigned long divisor = (SDM_DEN * n2) + sdm;
if (n2 < N2_MIN)
return -EINVAL;
return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
}
static struct parm meson_mpll0_parm[2] = {
{HHI_MPLL_CNTL1, 0, 14}, /* psdm */
{HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
};
static struct parm meson_mpll1_parm[2] = {
{HHI_MPLL_CNTL3, 0, 14}, /* psdm */
{HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
};
static struct parm meson_mpll2_parm[2] = {
{HHI_MPLL_CNTL5, 0, 14}, /* psdm */
{HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
};
/*
* MultiPhase Locked Loops are outputs from a PLL with additional frequency
* scaling capabilities. MPLL rates are calculated as:
*
* f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
*/
static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *psdm, *pn2;
unsigned long sdm, n2;
unsigned long parent_rate;
uint reg;
switch (id) {
case CLKID_MPLL0:
psdm = &meson_mpll0_parm[0];
pn2 = &meson_mpll0_parm[1];
break;
case CLKID_MPLL1:
psdm = &meson_mpll1_parm[0];
pn2 = &meson_mpll1_parm[1];
break;
case CLKID_MPLL2:
psdm = &meson_mpll2_parm[0];
pn2 = &meson_mpll2_parm[1];
break;
default:
return -ENOENT;
}
parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
if (IS_ERR_VALUE(parent_rate))
return parent_rate;
regmap_read(priv->map, psdm->reg_off, &reg);
sdm = PARM_GET(psdm->width, psdm->shift, reg);
regmap_read(priv->map, pn2->reg_off, &reg);
n2 = PARM_GET(pn2->width, pn2->shift, reg);
return mpll_rate_from_params(parent_rate, sdm, n2);
}
static struct parm meson_fixed_pll_parm[3] = {
{HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */
{HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
{HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
};
static struct parm meson_sys_pll_parm[3] = {
{HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */
{HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
{HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */
};
static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *pm, *pn, *pod;
unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
u16 n, m, od;
uint reg;
/*
* FIXME: Between the unit conversion and the missing frac, we know
* rate will be slightly off ...
*/
switch (id) {
case CLKID_FIXED_PLL:
pm = &meson_fixed_pll_parm[0];
pn = &meson_fixed_pll_parm[1];
pod = &meson_fixed_pll_parm[2];
break;
case CLKID_SYS_PLL:
pm = &meson_sys_pll_parm[0];
pn = &meson_sys_pll_parm[1];
pod = &meson_sys_pll_parm[2];
break;
default:
return -ENOENT;
}
regmap_read(priv->map, pn->reg_off, &reg);
n = PARM_GET(pn->width, pn->shift, reg);
regmap_read(priv->map, pm->reg_off, &reg);
m = PARM_GET(pm->width, pm->shift, reg);
regmap_read(priv->map, pod->reg_off, &reg);
od = PARM_GET(pod->width, pod->shift, reg);
return ((parent_rate_mhz * m / n) >> od) * 1000000;
}
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
{
ulong rate;
switch (id) {
case CLKID_FIXED_PLL:
case CLKID_SYS_PLL:
rate = meson_pll_get_rate(clk, id);
break;
case CLKID_FCLK_DIV2:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
break;
case CLKID_FCLK_DIV3:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
break;
case CLKID_FCLK_DIV4:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
break;
case CLKID_FCLK_DIV5:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
break;
case CLKID_FCLK_DIV7:
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
break;
case CLKID_MPLL0:
case CLKID_MPLL1:
case CLKID_MPLL2:
rate = meson_mpll_get_rate(clk, id);
break;
case CLKID_CLK81:
rate = meson_clk81_get_rate(clk);
break;
default:
if (gates[id].reg != 0) {
/* a clock gate */
rate = meson_clk81_get_rate(clk);
break;
}
return -ENOENT;
}
debug("clock %lu has rate %lu\n", id, rate);
return rate;
}
static ulong meson_clk_get_rate(struct clk *clk)
{
return meson_clk_get_rate_by_id(clk, clk->id);
}
static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
debug("meson-clk-g12a: probed\n");
return 0;
}
static struct clk_ops meson_clk_ops = {
.disable = meson_clk_disable,
.enable = meson_clk_enable,
.get_rate = meson_clk_get_rate,
};
static const struct udevice_id meson_clk_ids[] = {
{ .compatible = "amlogic,g12a-clkc" },
{ }
};
U_BOOT_DRIVER(meson_clk_g12a) = {
.name = "meson_clk_g12a",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
.priv_auto_alloc_size = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};

0
drivers/clk/clk_meson.c → drivers/clk/meson/gxbb.c
View file

30
drivers/i2c/meson_i2c.c
View file

@ -41,7 +41,12 @@ struct i2c_regs {
u32 tok_rdata1;
};
struct meson_i2c_data {
unsigned char div_factor;
};
struct meson_i2c {
const struct meson_i2c_data *data;
struct clk clk;
struct i2c_regs *regs;
struct i2c_msg *msg; /* Current I2C message */
@ -229,7 +234,7 @@ static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
if (IS_ERR_VALUE(clk_rate))
return -EINVAL;
div = DIV_ROUND_UP(clk_rate, speed * 4);
div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor);
/* clock divider has 12 bits */
if (div >= (1 << 12)) {
@ -253,6 +258,8 @@ static int meson_i2c_probe(struct udevice *bus)
struct meson_i2c *i2c = dev_get_priv(bus);
int ret;
i2c->data = (const struct meson_i2c_data *)dev_get_driver_data(bus);
ret = clk_get_by_index(bus, 0, &i2c->clk);
if (ret < 0)
return ret;
@ -272,11 +279,24 @@ static const struct dm_i2c_ops meson_i2c_ops = {
.set_bus_speed = meson_i2c_set_bus_speed,
};
static const struct meson_i2c_data i2c_meson6_data = {
.div_factor = 4,
};
static const struct meson_i2c_data i2c_gxbb_data = {
.div_factor = 4,
};
static const struct meson_i2c_data i2c_axg_data = {
.div_factor = 3,
};
static const struct udevice_id meson_i2c_ids[] = {
{ .compatible = "amlogic,meson6-i2c" },
{ .compatible = "amlogic,meson-gx-i2c" },
{ .compatible = "amlogic,meson-gxbb-i2c" },
{ }
{.compatible = "amlogic,meson6-i2c", .data = (ulong)&i2c_meson6_data},
{.compatible = "amlogic,meson-gx-i2c", .data = (ulong)&i2c_gxbb_data},
{.compatible = "amlogic,meson-gxbb-i2c", .data = (ulong)&i2c_gxbb_data},
{.compatible = "amlogic,meson-axg-i2c", .data = (ulong)&i2c_axg_data},
{}
};
U_BOOT_DRIVER(i2c_meson) = {

2
drivers/net/sandbox.c
View file

@ -350,7 +350,7 @@ static int sb_eth_recv(struct udevice *dev, int flags, uchar **packetp)
struct eth_sandbox_priv *priv = dev_get_priv(dev);
if (skip_timeout) {
sandbox_timer_add_offset(11000UL);
timer_test_add_offset(11000UL);
skip_timeout = false;
}

4
drivers/pinctrl/meson/Kconfig
View file

@ -25,4 +25,8 @@ config PINCTRL_MESON_AXG
bool "Amlogic Meson AXG SoC pinctrl driver"
select PINCTRL_MESON_AXG_PMX
config PINCTRL_MESON_G12A
bool "Amlogic Meson G12a SoC pinctrl driver"
select PINCTRL_MESON_AXG_PMX
endif

1
drivers/pinctrl/meson/Makefile
View file

@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o

348
drivers/pinctrl/meson/pinctrl-meson-axg.c
View file

@ -17,239 +17,239 @@
#define EE_OFF 15
/* emmc */
static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
static const unsigned int emmc_nand_d0_pins[] = { PIN(BOOT_0, EE_OFF) };
static const unsigned int emmc_nand_d1_pins[] = { PIN(BOOT_1, EE_OFF) };
static const unsigned int emmc_nand_d2_pins[] = { PIN(BOOT_2, EE_OFF) };
static const unsigned int emmc_nand_d3_pins[] = { PIN(BOOT_3, EE_OFF) };
static const unsigned int emmc_nand_d4_pins[] = { PIN(BOOT_4, EE_OFF) };
static const unsigned int emmc_nand_d5_pins[] = { PIN(BOOT_5, EE_OFF) };
static const unsigned int emmc_nand_d6_pins[] = { PIN(BOOT_6, EE_OFF) };
static const unsigned int emmc_nand_d7_pins[] = { PIN(BOOT_7, EE_OFF) };
static const unsigned int emmc_clk_pins[] = {BOOT_8};
static const unsigned int emmc_cmd_pins[] = {BOOT_10};
static const unsigned int emmc_ds_pins[] = {BOOT_13};
static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
static const unsigned int emmc_ds_pins[] = { PIN(BOOT_13, EE_OFF) };
/* nand */
static const unsigned int nand_ce0_pins[] = {BOOT_8};
static const unsigned int nand_ale_pins[] = {BOOT_9};
static const unsigned int nand_cle_pins[] = {BOOT_10};
static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
static const unsigned int nand_rb0_pins[] = {BOOT_13};
static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
static const unsigned int nand_ale_pins[] = { PIN(BOOT_9, EE_OFF) };
static const unsigned int nand_cle_pins[] = { PIN(BOOT_10, EE_OFF) };
static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_11, EE_OFF) };
static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_12, EE_OFF) };
static const unsigned int nand_rb0_pins[] = { PIN(BOOT_13, EE_OFF) };
/* nor */
static const unsigned int nor_hold_pins[] = {BOOT_3};
static const unsigned int nor_d_pins[] = {BOOT_4};
static const unsigned int nor_q_pins[] = {BOOT_5};
static const unsigned int nor_c_pins[] = {BOOT_6};
static const unsigned int nor_wp_pins[] = {BOOT_9};
static const unsigned int nor_cs_pins[] = {BOOT_14};
static const unsigned int nor_hold_pins[] = { PIN(BOOT_3, EE_OFF) };
static const unsigned int nor_d_pins[] = { PIN(BOOT_4, EE_OFF) };
static const unsigned int nor_q_pins[] = { PIN(BOOT_5, EE_OFF) };
static const unsigned int nor_c_pins[] = { PIN(BOOT_6, EE_OFF) };
static const unsigned int nor_wp_pins[] = { PIN(BOOT_9, EE_OFF) };
static const unsigned int nor_cs_pins[] = { PIN(BOOT_14, EE_OFF) };
/* sdio */
static const unsigned int sdio_d0_pins[] = {GPIOX_0};
static const unsigned int sdio_d1_pins[] = {GPIOX_1};
static const unsigned int sdio_d2_pins[] = {GPIOX_2};
static const unsigned int sdio_d3_pins[] = {GPIOX_3};
static const unsigned int sdio_clk_pins[] = {GPIOX_4};
static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };
static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };
static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };
static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };
static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_4, EE_OFF) };
static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_5, EE_OFF) };
/* spi0 */
static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
static const unsigned int spi0_clk_pins[] = { PIN(GPIOZ_0, EE_OFF) };
static const unsigned int spi0_mosi_pins[] = { PIN(GPIOZ_1, EE_OFF) };
static const unsigned int spi0_miso_pins[] = { PIN(GPIOZ_2, EE_OFF) };
static const unsigned int spi0_ss0_pins[] = { PIN(GPIOZ_3, EE_OFF) };
static const unsigned int spi0_ss1_pins[] = { PIN(GPIOZ_4, EE_OFF) };
static const unsigned int spi0_ss2_pins[] = { PIN(GPIOZ_5, EE_OFF) };
/* spi1 */
static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
static const unsigned int spi1_clk_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
static const unsigned int spi1_mosi_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
static const unsigned int spi1_miso_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
static const unsigned int spi1_ss0_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
static const unsigned int spi1_clk_a_pins[] = { PIN(GPIOA_4, EE_OFF) };
static const unsigned int spi1_mosi_a_pins[] = { PIN(GPIOA_2, EE_OFF) };
static const unsigned int spi1_miso_a_pins[] = { PIN(GPIOA_3, EE_OFF) };
static const unsigned int spi1_ss0_a_pins[] = { PIN(GPIOA_5, EE_OFF) };
static const unsigned int spi1_ss1_pins[] = { PIN(GPIOA_6, EE_OFF) };
/* i2c0 */
static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
static const unsigned int i2c0_sck_pins[] = { PIN(GPIOZ_6, EE_OFF) };
static const unsigned int i2c0_sda_pins[] = { PIN(GPIOZ_7, EE_OFF) };
/* i2c1 */
static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
static const unsigned int i2c1_sck_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
static const unsigned int i2c1_sda_z_pins[] = { PIN(GPIOZ_9, EE_OFF) };
static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
static const unsigned int i2c1_sck_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
static const unsigned int i2c1_sda_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
/* i2c2 */
static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
static const unsigned int i2c2_sck_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
static const unsigned int i2c2_sda_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
static const unsigned int i2c2_sda_a_pins[] = { PIN(GPIOA_17, EE_OFF) };
static const unsigned int i2c2_sck_a_pins[] = { PIN(GPIOA_18, EE_OFF) };
/* i2c3 */
static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
static const unsigned int i2c3_sda_a6_pins[] = { PIN(GPIOA_6, EE_OFF) };
static const unsigned int i2c3_sck_a7_pins[] = { PIN(GPIOA_7, EE_OFF) };
static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
static const unsigned int i2c3_sda_a12_pins[] = { PIN(GPIOA_12, EE_OFF) };
static const unsigned int i2c3_sck_a13_pins[] = { PIN(GPIOA_13, EE_OFF) };
static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
static const unsigned int i2c3_sda_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
static const unsigned int i2c3_sck_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
/* uart_a */
static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_11, EE_OFF) };
static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_10, EE_OFF) };
static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_8, EE_OFF) };
static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_9, EE_OFF) };
/* uart_b */
static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
static const unsigned int uart_rts_b_z_pins[] = { PIN(GPIOZ_0, EE_OFF) };
static const unsigned int uart_cts_b_z_pins[] = { PIN(GPIOZ_1, EE_OFF) };
static const unsigned int uart_tx_b_z_pins[] = { PIN(GPIOZ_2, EE_OFF) };
static const unsigned int uart_rx_b_z_pins[] = { PIN(GPIOZ_3, EE_OFF) };
static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
static const unsigned int uart_rts_b_x_pins[] = { PIN(GPIOX_18, EE_OFF) };
static const unsigned int uart_cts_b_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
static const unsigned int uart_tx_b_x_pins[] = { PIN(GPIOX_16, EE_OFF) };
static const unsigned int uart_rx_b_x_pins[] = { PIN(GPIOX_17, EE_OFF) };
/* uart_ao_b */
static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
static const unsigned int uart_ao_tx_b_z_pins[] = { PIN(GPIOZ_8, EE_OFF) };
static const unsigned int uart_ao_rx_b_z_pins[] = { PIN(GPIOZ_9, EE_OFF) };
static const unsigned int uart_ao_cts_b_z_pins[] = { PIN(GPIOZ_6, EE_OFF) };
static const unsigned int uart_ao_rts_b_z_pins[] = { PIN(GPIOZ_7, EE_OFF) };
/* pwm_a */
static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
static const unsigned int pwm_a_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
static const unsigned int pwm_a_x18_pins[] = { PIN(GPIOX_18, EE_OFF) };
static const unsigned int pwm_a_x20_pins[] = { PIN(GPIOX_20, EE_OFF) };
static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
static const unsigned int pwm_a_a_pins[] = { PIN(GPIOA_14, EE_OFF) };
/* pwm_b */
static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_19, EE_OFF) };
static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
static const unsigned int pwm_b_a_pins[] = { PIN(GPIOA_15, EE_OFF) };
/* pwm_c */
static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
static const unsigned int pwm_c_x10_pins[] = { PIN(GPIOX_10, EE_OFF) };
static const unsigned int pwm_c_x17_pins[] = { PIN(GPIOX_17, EE_OFF) };
static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
static const unsigned int pwm_c_a_pins[] = { PIN(GPIOA_16, EE_OFF) };
/* pwm_d */
static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
static const unsigned int pwm_d_x11_pins[] = { PIN(GPIOX_11, EE_OFF) };
static const unsigned int pwm_d_x16_pins[] = { PIN(GPIOX_16, EE_OFF) };
/* pwm_vs */
static const unsigned int pwm_vs_pins[] = {GPIOA_0};
static const unsigned int pwm_vs_pins[] = { PIN(GPIOA_0, EE_OFF) };
/* spdif_in */
static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
static const unsigned int spdif_in_z_pins[] = { PIN(GPIOZ_4, EE_OFF) };
static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
static const unsigned int spdif_in_a1_pins[] = { PIN(GPIOA_1, EE_OFF) };
static const unsigned int spdif_in_a7_pins[] = { PIN(GPIOA_7, EE_OFF) };
static const unsigned int spdif_in_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
static const unsigned int spdif_in_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
/* spdif_out */
static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
static const unsigned int spdif_out_z_pins[] = { PIN(GPIOZ_5, EE_OFF) };
static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
static const unsigned int spdif_out_a1_pins[] = { PIN(GPIOA_1, EE_OFF) };
static const unsigned int spdif_out_a11_pins[] = { PIN(GPIOA_11, EE_OFF) };
static const unsigned int spdif_out_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
static const unsigned int spdif_out_a20_pins[] = { PIN(GPIOA_20, EE_OFF) };
/* jtag_ee */
static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
static const unsigned int jtag_tdo_x_pins[] = { PIN(GPIOX_0, EE_OFF) };
static const unsigned int jtag_tdi_x_pins[] = { PIN(GPIOX_1, EE_OFF) };
static const unsigned int jtag_clk_x_pins[] = { PIN(GPIOX_4, EE_OFF) };
static const unsigned int jtag_tms_x_pins[] = { PIN(GPIOX_5, EE_OFF) };
/* eth */
static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
static const unsigned int eth_txd0_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
static const unsigned int eth_txd1_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
static const unsigned int eth_txen_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
static const unsigned int eth_rgmii_rx_clk_x_pins[] = { PIN(GPIOX_12, EE_OFF) };
static const unsigned int eth_rxd0_x_pins[] = { PIN(GPIOX_13, EE_OFF) };
static const unsigned int eth_rxd1_x_pins[] = { PIN(GPIOX_14, EE_OFF) };
static const unsigned int eth_rx_dv_x_pins[] = { PIN(GPIOX_15, EE_OFF) };
static const unsigned int eth_mdio_x_pins[] = { PIN(GPIOX_21, EE_OFF) };
static const unsigned int eth_mdc_x_pins[] = { PIN(GPIOX_22, EE_OFF) };
static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
static const unsigned int eth_txd0_y_pins[] = { PIN(GPIOY_10, EE_OFF) };
static const unsigned int eth_txd1_y_pins[] = { PIN(GPIOY_11, EE_OFF) };
static const unsigned int eth_txen_y_pins[] = { PIN(GPIOY_9, EE_OFF) };
static const unsigned int eth_rgmii_rx_clk_y_pins[] = { PIN(GPIOY_2, EE_OFF) };
static const unsigned int eth_rxd0_y_pins[] = { PIN(GPIOY_4, EE_OFF) };
static const unsigned int eth_rxd1_y_pins[] = { PIN(GPIOY_5, EE_OFF) };
static const unsigned int eth_rx_dv_y_pins[] = { PIN(GPIOY_3, EE_OFF) };
static const unsigned int eth_mdio_y_pins[] = { PIN(GPIOY_0, EE_OFF) };
static const unsigned int eth_mdc_y_pins[] = { PIN(GPIOY_1, EE_OFF) };
static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
static const unsigned int eth_rxd2_rgmii_pins[] = { PIN(GPIOY_6, EE_OFF) };
static const unsigned int eth_rxd3_rgmii_pins[] = { PIN(GPIOY_7, EE_OFF) };
static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOY_8, EE_OFF) };
static const unsigned int eth_txd2_rgmii_pins[] = { PIN(GPIOY_12, EE_OFF) };
static const unsigned int eth_txd3_rgmii_pins[] = { PIN(GPIOY_13, EE_OFF) };
/* pdm */
static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
static const unsigned int pdm_din0_pins[] = {GPIOA_15};
static const unsigned int pdm_din1_pins[] = {GPIOA_16};
static const unsigned int pdm_din2_pins[] = {GPIOA_17};
static const unsigned int pdm_din3_pins[] = {GPIOA_18};
static const unsigned int pdm_dclk_a14_pins[] = { PIN(GPIOA_14, EE_OFF) };
static const unsigned int pdm_dclk_a19_pins[] = { PIN(GPIOA_19, EE_OFF) };
static const unsigned int pdm_din0_pins[] = { PIN(GPIOA_15, EE_OFF) };
static const unsigned int pdm_din1_pins[] = { PIN(GPIOA_16, EE_OFF) };
static const unsigned int pdm_din2_pins[] = { PIN(GPIOA_17, EE_OFF) };
static const unsigned int pdm_din3_pins[] = { PIN(GPIOA_18, EE_OFF) };
/* mclk */
static const unsigned int mclk_c_pins[] = {GPIOA_0};
static const unsigned int mclk_b_pins[] = {GPIOA_1};
static const unsigned int mclk_c_pins[] = { PIN(GPIOA_0, EE_OFF) };
static const unsigned int mclk_b_pins[] = { PIN(GPIOA_1, EE_OFF) };
/* tdm */
static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
static const unsigned int tdma_fs_pins[] = {GPIOX_13};
static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
static const unsigned int tdma_din0_pins[] = {GPIOX_14};
static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
static const unsigned int tdma_din1_pins[] = {GPIOX_15};
static const unsigned int tdma_sclk_pins[] = { PIN(GPIOX_12, EE_OFF) };
static const unsigned int tdma_sclk_slv_pins[] = { PIN(GPIOX_12, EE_OFF) };
static const unsigned int tdma_fs_pins[] = { PIN(GPIOX_13, EE_OFF) };
static const unsigned int tdma_fs_slv_pins[] = { PIN(GPIOX_13, EE_OFF) };
static const unsigned int tdma_din0_pins[] = { PIN(GPIOX_14, EE_OFF) };
static const unsigned int tdma_dout0_x14_pins[] = { PIN(GPIOX_14, EE_OFF) };
static const unsigned int tdma_dout0_x15_pins[] = { PIN(GPIOX_15, EE_OFF) };
static const unsigned int tdma_dout1_pins[] = { PIN(GPIOX_15, EE_OFF) };
static const unsigned int tdma_din1_pins[] = { PIN(GPIOX_15, EE_OFF) };
static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
static const unsigned int tdmc_sclk_pins[] = { PIN(GPIOA_2, EE_OFF) };
static const unsigned int tdmc_sclk_slv_pins[] = { PIN(GPIOA_2, EE_OFF) };
static const unsigned int tdmc_fs_pins[] = { PIN(GPIOA_3, EE_OFF) };
static const unsigned int tdmc_fs_slv_pins[] = { PIN(GPIOA_3, EE_OFF) };
static const unsigned int tdmc_din0_pins[] = { PIN(GPIOA_4, EE_OFF) };
static const unsigned int tdmc_dout0_pins[] = { PIN(GPIOA_4, EE_OFF) };
static const unsigned int tdmc_din1_pins[] = { PIN(GPIOA_5, EE_OFF) };
static const unsigned int tdmc_dout1_pins[] = { PIN(GPIOA_5, EE_OFF) };
static const unsigned int tdmc_din2_pins[] = { PIN(GPIOA_6, EE_OFF) };
static const unsigned int tdmc_dout2_pins[] = { PIN(GPIOA_6, EE_OFF) };
static const unsigned int tdmc_din3_pins[] = { PIN(GPIOA_7, EE_OFF) };
static const unsigned int tdmc_dout3_pins[] = { PIN(GPIOA_7, EE_OFF) };
static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
static const unsigned int tdmb_sclk_pins[] = { PIN(GPIOA_8, EE_OFF) };
static const unsigned int tdmb_sclk_slv_pins[] = { PIN(GPIOA_8, EE_OFF) };
static const unsigned int tdmb_fs_pins[] = { PIN(GPIOA_9, EE_OFF) };
static const unsigned int tdmb_fs_slv_pins[] = { PIN(GPIOA_9, EE_OFF) };
static const unsigned int tdmb_din0_pins[] = { PIN(GPIOA_10, EE_OFF) };
static const unsigned int tdmb_dout0_pins[] = { PIN(GPIOA_10, EE_OFF) };
static const unsigned int tdmb_din1_pins[] = { PIN(GPIOA_11, EE_OFF) };
static const unsigned int tdmb_dout1_pins[] = { PIN(GPIOA_11, EE_OFF) };
static const unsigned int tdmb_din2_pins[] = { PIN(GPIOA_12, EE_OFF) };
static const unsigned int tdmb_dout2_pins[] = { PIN(GPIOA_12, EE_OFF) };
static const unsigned int tdmb_din3_pins[] = { PIN(GPIOA_13, EE_OFF) };
static const unsigned int tdmb_dout3_pins[] = { PIN(GPIOA_13, EE_OFF) };
static struct meson_pmx_group meson_axg_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0, EE_OFF),
@ -907,12 +907,12 @@ static struct meson_bank meson_axg_aobus_banks[] = {
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
/* name first lask reg offset */
BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0),
BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0),
BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
/* name first last reg offset */
BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0),
BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0),
BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0),
BANK_PMX("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 0x4, 0),
BANK_PMX("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), 0x8, 0),
};
static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
@ -931,7 +931,7 @@ static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.name = "periphs-banks",
.pin_base = 15,
.pin_base = EE_OFF,
.groups = meson_axg_periphs_groups,
.funcs = meson_axg_periphs_functions,
.banks = meson_axg_periphs_banks,

1294
drivers/pinctrl/meson/pinctrl-meson-g12a.c Normal file
View file

File diff suppressed because it is too large Load diff

17
drivers/pinctrl/meson/pinctrl-meson.c
View file

@ -314,11 +314,11 @@ int meson_pinctrl_probe(struct udevice *dev)
priv->reg_gpio = (void __iomem *)addr;
addr = parse_address(gpio, "pull", na, ns);
if (addr == FDT_ADDR_T_NONE) {
debug("pull address not found\n");
return -EINVAL;
}
priv->reg_pull = (void __iomem *)addr;
/* Use gpio region if pull one is not present */
if (addr == FDT_ADDR_T_NONE)
priv->reg_pull = priv->reg_gpio;
else
priv->reg_pull = (void __iomem *)addr;
addr = parse_address(gpio, "pull-enable", na, ns);
/* Use pull region if pull-enable one is not present */
@ -327,6 +327,13 @@ int meson_pinctrl_probe(struct udevice *dev)
else
priv->reg_pullen = (void __iomem *)addr;
addr = parse_address(gpio, "ds", na, ns);
/* Drive strength region is optional */
if (addr == FDT_ADDR_T_NONE)
priv->reg_ds = NULL;
else
priv->reg_ds = (void __iomem *)addr;
priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
/* Lookup GPIO driver */

1
drivers/pinctrl/meson/pinctrl-meson.h
View file

@ -41,6 +41,7 @@ struct meson_pinctrl {
void __iomem *reg_gpio;
void __iomem *reg_pull;
void __iomem *reg_pullen;
void __iomem *reg_ds;
};
/**

1
drivers/reset/reset-meson.c
View file

@ -69,6 +69,7 @@ struct reset_ops meson_reset_ops = {
static const struct udevice_id meson_reset_ids[] = {
{ .compatible = "amlogic,meson-gxbb-reset" },
{ .compatible = "amlogic,meson-axg-reset" },
{ }
};

2
drivers/timer/sandbox_timer.c
View file

@ -14,7 +14,7 @@
/* system timer offset in ms */
static unsigned long sandbox_timer_offset;
void sandbox_timer_add_offset(unsigned long offset)
void timer_test_add_offset(unsigned long offset)
{
sandbox_timer_offset += offset;
}

24
include/configs/libretech-ac.h Normal file
View file

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for LibreTech AC
*
* Copyright (C) 2017 Baylibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OFFSET (-0x10000)
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
func(MMC, mmc, 0) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#include <configs/meson64.h>
#endif /* __CONFIG_H */

34
include/dt-bindings/clock/g12a-aoclkc.h Normal file
View file

@ -0,0 +1,34 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*/
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define CLKID_AO_AHB 0
#define CLKID_AO_IR_IN 1
#define CLKID_AO_I2C_M0 2
#define CLKID_AO_I2C_S0 3
#define CLKID_AO_UART 4
#define CLKID_AO_PROD_I2C 5
#define CLKID_AO_UART2 6
#define CLKID_AO_IR_OUT 7
#define CLKID_AO_SAR_ADC 8
#define CLKID_AO_MAILBOX 9
#define CLKID_AO_M3 10
#define CLKID_AO_AHB_SRAM 11
#define CLKID_AO_RTI 12
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28
#endif

135
include/dt-bindings/clock/g12a-clkc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* Meson-G12A clock tree IDs
*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
#ifndef __G12A_CLKC_H
#define __G12A_CLKC_H
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
#define CLKID_MPLL2 13
#define CLKID_MPLL3 14
#define CLKID_DDR 15
#define CLKID_DOS 16
#define CLKID_AUDIO_LOCKER 17
#define CLKID_MIPI_DSI_HOST 18
#define CLKID_ETH_PHY 19
#define CLKID_ISA 20
#define CLKID_PL301 21
#define CLKID_PERIPHS 22
#define CLKID_SPICC0 23
#define CLKID_I2C 24
#define CLKID_SANA 25
#define CLKID_SD 26
#define CLKID_RNG0 27
#define CLKID_UART0 28
#define CLKID_SPICC1 29
#define CLKID_HIU_IFACE 30
#define CLKID_MIPI_DSI_PHY 31
#define CLKID_ASSIST_MISC 32
#define CLKID_SD_EMMC_A 33
#define CLKID_SD_EMMC_B 34
#define CLKID_SD_EMMC_C 35
#define CLKID_AUDIO_CODEC 36
#define CLKID_AUDIO 37
#define CLKID_ETH 38
#define CLKID_DEMUX 39
#define CLKID_AUDIO_IFIFO 40
#define CLKID_ADC 41
#define CLKID_UART1 42
#define CLKID_G2D 43
#define CLKID_RESET 44
#define CLKID_PCIE_COMB 45
#define CLKID_PARSER 46
#define CLKID_USB 47
#define CLKID_PCIE_PHY 48
#define CLKID_AHB_ARB0 49
#define CLKID_AHB_DATA_BUS 50
#define CLKID_AHB_CTRL_BUS 51
#define CLKID_HTX_HDCP22 52
#define CLKID_HTX_PCLK 53
#define CLKID_BT656 54
#define CLKID_USB1_DDR_BRIDGE 55
#define CLKID_MMC_PCLK 56
#define CLKID_UART2 57
#define CLKID_VPU_INTR 58
#define CLKID_GIC 59
#define CLKID_SD_EMMC_A_CLK0 60
#define CLKID_SD_EMMC_B_CLK0 61
#define CLKID_SD_EMMC_C_CLK0 62
#define CLKID_HIFI_PLL 74
#define CLKID_VCLK2_VENCI0 80
#define CLKID_VCLK2_VENCI1 81
#define CLKID_VCLK2_VENCP0 82
#define CLKID_VCLK2_VENCP1 83
#define CLKID_VCLK2_VENCT0 84
#define CLKID_VCLK2_VENCT1 85
#define CLKID_VCLK2_OTHER 86
#define CLKID_VCLK2_ENCI 87
#define CLKID_VCLK2_ENCP 88
#define CLKID_DAC_CLK 89
#define CLKID_AOCLK 90
#define CLKID_IEC958 91
#define CLKID_ENC480P 92
#define CLKID_RNG1 93
#define CLKID_VCLK2_ENCT 94
#define CLKID_VCLK2_ENCL 95
#define CLKID_VCLK2_VENCLMMC 96
#define CLKID_VCLK2_VENCL 97
#define CLKID_VCLK2_OTHER1 98
#define CLKID_FCLK_DIV2P5 99
#define CLKID_DMA 105
#define CLKID_EFUSE 106
#define CLKID_ROM_BOOT 107
#define CLKID_RESET_SEC 108
#define CLKID_SEC_AHB_APB3 109
#define CLKID_VPU_0_SEL 110
#define CLKID_VPU_0 112
#define CLKID_VPU_1_SEL 113
#define CLKID_VPU_1 115
#define CLKID_VPU 116
#define CLKID_VAPB_0_SEL 117
#define CLKID_VAPB_0 119
#define CLKID_VAPB_1_SEL 120
#define CLKID_VAPB_1 122
#define CLKID_VAPB_SEL 123
#define CLKID_VAPB 124
#define CLKID_HDMI_PLL 128
#define CLKID_VID_PLL 129
#define CLKID_VCLK 138
#define CLKID_VCLK2 139
#define CLKID_VCLK_DIV1 148
#define CLKID_VCLK_DIV2 149
#define CLKID_VCLK_DIV4 150
#define CLKID_VCLK_DIV6 151
#define CLKID_VCLK_DIV12 152
#define CLKID_VCLK2_DIV1 153
#define CLKID_VCLK2_DIV2 154
#define CLKID_VCLK2_DIV4 155
#define CLKID_VCLK2_DIV6 156
#define CLKID_VCLK2_DIV12 157
#define CLKID_CTS_ENCI 162
#define CLKID_CTS_ENCP 163
#define CLKID_CTS_VDAC 164
#define CLKID_HDMI_TX 165
#define CLKID_HDMI 168
#define CLKID_MALI_0_SEL 169
#define CLKID_MALI_0 171
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#endif /* __G12A_CLKC_H */

114
include/dt-bindings/gpio/meson-g12a-gpio.h Normal file
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@ -0,0 +1,114 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*/
#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
#define _DT_BINDINGS_MESON_G12A_GPIO_H
/* First GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOE_0 12
#define GPIOE_1 13
#define GPIOE_2 14
/* Second GPIO chip */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOZ_11 11
#define GPIOZ_12 12
#define GPIOZ_13 13
#define GPIOZ_14 14
#define GPIOZ_15 15
#define GPIOH_0 16
#define GPIOH_1 17
#define GPIOH_2 18
#define GPIOH_3 19
#define GPIOH_4 20
#define GPIOH_5 21
#define GPIOH_6 22
#define GPIOH_7 23
#define GPIOH_8 24
#define BOOT_0 25
#define BOOT_1 26
#define BOOT_2 27
#define BOOT_3 28
#define BOOT_4 29
#define BOOT_5 30
#define BOOT_6 31
#define BOOT_7 32
#define BOOT_8 33
#define BOOT_9 34
#define BOOT_10 35
#define BOOT_11 36
#define BOOT_12 37
#define BOOT_13 38
#define BOOT_14 39
#define BOOT_15 40
#define GPIOC_0 41
#define GPIOC_1 42
#define GPIOC_2 43
#define GPIOC_3 44
#define GPIOC_4 45
#define GPIOC_5 46
#define GPIOC_6 47
#define GPIOC_7 48
#define GPIOA_0 49
#define GPIOA_1 50
#define GPIOA_2 51
#define GPIOA_3 52
#define GPIOA_4 53
#define GPIOA_5 54
#define GPIOA_6 55
#define GPIOA_7 56
#define GPIOA_8 57
#define GPIOA_9 58
#define GPIOA_10 59
#define GPIOA_11 60
#define GPIOA_12 61
#define GPIOA_13 62
#define GPIOA_14 63
#define GPIOA_15 64
#define GPIOX_0 65
#define GPIOX_1 66
#define GPIOX_2 67
#define GPIOX_3 68
#define GPIOX_4 69
#define GPIOX_5 70
#define GPIOX_6 71
#define GPIOX_7 72
#define GPIOX_8 73
#define GPIOX_9 74
#define GPIOX_10 75
#define GPIOX_11 76
#define GPIOX_12 77
#define GPIOX_13 78
#define GPIOX_14 79
#define GPIOX_15 80
#define GPIOX_16 81
#define GPIOX_17 82
#define GPIOX_18 83
#define GPIOX_19 84
#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */

134
include/dt-bindings/reset/amlogic,meson-g12a-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
/* RESET0 */
#define RESET_HIU 0
/* 1 */
#define RESET_DOS 2
/* 3-4 */
#define RESET_VIU 5
#define RESET_AFIFO 6
#define RESET_VID_PLL_DIV 7
/* 8-9 */
#define RESET_VENC 10
#define RESET_ASSIST 11
#define RESET_PCIE_CTRL_A 12
#define RESET_VCBUS 13
#define RESET_PCIE_PHY 14
#define RESET_PCIE_APB 15
#define RESET_GIC 16
#define RESET_CAPB3_DECODE 17
/* 18 */
#define RESET_HDMITX_CAPB3 19
#define RESET_DVALIN_CAPB3 20
#define RESET_DOS_CAPB3 21
/* 22 */
#define RESET_CBUS_CAPB3 23
#define RESET_AHB_CNTL 24
#define RESET_AHB_DATA 25
#define RESET_VCBUS_CLK81 26
/* 27-31 */
/* RESET1 */
/* 32 */
#define RESET_DEMUX 33
#define RESET_USB 34
#define RESET_DDR 35
/* 36 */
#define RESET_BT656 37
#define RESET_AHB_SRAM 38
/* 39 */
#define RESET_PARSER 40
/* 41 */
#define RESET_ISA 42
#define RESET_ETHERNET 43
#define RESET_SD_EMMC_A 44
#define RESET_SD_EMMC_B 45
#define RESET_SD_EMMC_C 46
/* 47-60 */
#define RESET_AUDIO_CODEC 61
/* 62-63 */
/* RESET2 */
/* 64 */
#define RESET_AUDIO 65
#define RESET_HDMITX_PHY 66
/* 67 */
#define RESET_MIPI_DSI_HOST 68
#define RESET_ALOCKER 69
#define RESET_GE2D 70
#define RESET_PARSER_REG 71
#define RESET_PARSER_FETCH 72
#define RESET_CTL 73
#define RESET_PARSER_TOP 74
/* 75-77 */
#define RESET_DVALIN 78
#define RESET_HDMITX 79
/* 80-95 */
/* RESET3 */
/* 96-95 */
#define RESET_DEMUX_TOP 105
#define RESET_DEMUX_DES_PL 106
#define RESET_DEMUX_S2P_0 107
#define RESET_DEMUX_S2P_1 108
#define RESET_DEMUX_0 109
#define RESET_DEMUX_1 110
#define RESET_DEMUX_2 111
/* 112-127 */
/* RESET4 */
/* 128-129 */
#define RESET_MIPI_DSI_PHY 130
/* 131-132 */
#define RESET_RDMA 133
#define RESET_VENCI 134
#define RESET_VENCP 135
/* 136 */
#define RESET_VDAC 137
/* 138-139 */
#define RESET_VDI6 140
#define RESET_VENCL 141
#define RESET_I2C_M1 142
#define RESET_I2C_M2 143
/* 144-159 */
/* RESET5 */
/* 160-191 */
/* RESET6 */
#define RESET_GEN 192
#define RESET_SPICC0 193
#define RESET_SC 194
#define RESET_SANA_3 195
#define RESET_I2C_M0 196
#define RESET_TS_PLL 197
#define RESET_SPICC1 198
#define RESET_STREAM 199
#define RESET_TS_CPU 200
#define RESET_UART0 201
#define RESET_UART1_2 202
#define RESET_ASYNC0 203
#define RESET_ASYNC1 204
#define RESET_SPIFC0 205
#define RESET_I2C_M3 206
/* 207-223 */
/* RESET7 */
#define RESET_USB_DDR_0 224
#define RESET_USB_DDR_1 225
#define RESET_USB_DDR_2 226
#define RESET_USB_DDR_3 227
#define RESET_TS_GPU 228
#define RESET_DEVICE_MMC_ARB 229
#define RESET_DVALIN_DMC_PIPL 230
#define RESET_VID_LOCK 231
#define RESET_NIC_DMC_PIPL 232
#define RESET_DMC_VPU_PIPL 233
#define RESET_GE2D_DMC_PIPL 234
#define RESET_HCODEC_DMC_PIPL 235
#define RESET_WAVE420_DMC_PIPL 236
#define RESET_HEVCF_DMC_PIPL 237
/* 238-255 */
#endif

18
include/dt-bindings/reset/g12a-aoclkc.h Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
#define RESET_AO_IR_IN 0
#define RESET_AO_UART 1
#define RESET_AO_I2C_M 2
#define RESET_AO_I2C_S 3
#define RESET_AO_SAR_ADC 4
#define RESET_AO_UART2 5
#define RESET_AO_IR_OUT 6
#endif

2
include/regmap.h
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@ -274,7 +274,7 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset,
if (cond) \
break; \
if (IS_ENABLED(CONFIG_SANDBOX) && test_add_time) \
sandbox_timer_add_offset(test_add_time); \
timer_test_add_offset(test_add_time); \
if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \
__ret = regmap_read((map), (addr), &(val)); \
break; \

8
include/time.h
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@ -13,6 +13,14 @@ unsigned long get_timer(unsigned long base);
*/
unsigned long timer_get_us(void);
/*
* timer_test_add_offset()
*
* Allow tests to add to the time reported through lib/time.c functions
* offset: number of milliseconds to advance the system time
*/
void timer_test_add_offset(unsigned long offset);
/*
* These inlines deal with timer wrapping correctly. You are
* strongly encouraged to use them