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STM32 MCUs update:

Browse source 
_ DT rework and alignment with DT kernel v4.20
 _ mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
 _ mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
 _ configs: update for F746/769 boards
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Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-boot

STM32 MCUs update:
- DT rework and alignment with DT kernel v4.20
- mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
- mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
- configs: update for F746/769 boards
This commit is contained in:
Tom Rini 2019-04-24 12:26:39 -04:00
commit c2bb9c5b9e
38 changed files with 2838 additions and 4214 deletions
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188
arch/arm/dts/stm32746g-eval-u-boot.dtsi Normal file
View file

@ -0,0 +1,188 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32f7-u-boot.dtsi>
/{
chosen {
bootargs = "root=/dev/mmcblk0p1 rw rootwait";
};
aliases {
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdio1;
spi0 = &qspi;
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioc 13 0>;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpiof 10 0>;
};
};
&fmc {
/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI
*/
bank1: bank@0 {
u-boot,dm-pre-reloc;
st,sdram-control = /bits/ 8 <NO_COL_9
NO_ROW_12
MWIDTH_32
BANKS_4
CAS_2
SDCLK_3
RD_BURST_EN
RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1
TXSR_1
TRAS_1
TRC_6
TRP_2
TWR_1
TRCD_1>;
st,sdram-refcount = <1539>;
};
};
&mac {
phy-mode = "mii";
};
&pinctrl {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32_PINMUX('A', 0, AF11)>, /*ETH_MII_CRS */
<STM32_PINMUX('A', 1, AF11)>, /*ETH_MII_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>, /*ETH_MII_RX_DV */
<STM32_PINMUX('A', 8, AF0)>, /*ETH_MII_MCO1 */
<STM32_PINMUX('G',13, AF11)>, /*ETH_MII_TXD0 */
<STM32_PINMUX('G',14, AF11)>, /*ETH_MII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /*ETH_MII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /*ETH_MII_TXD3 */
<STM32_PINMUX('C', 3, AF11)>, /*ETH_MII_TX_CLK */
<STM32_PINMUX('C', 4, AF11)>, /*ETH_MII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /*ETH_MII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /*ETH_MII_RXD2 */
<STM32_PINMUX('H', 7, AF11)>, /*ETH_MII_RXD3 */
<STM32_PINMUX('G',11, AF11)>, /*ETH_MII_TX_EN */
<STM32_PINMUX('C', 1, AF11)>, /*ETH_MII_MDC */
<STM32_PINMUX('A', 2, AF11)>; /*ETH_MII_MDIO */
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
<STM32_PINMUX('I', 9, AF12)>, /* D30 */
<STM32_PINMUX('I', 7, AF12)>, /* D29 */
<STM32_PINMUX('I', 6, AF12)>, /* D28 */
<STM32_PINMUX('I', 3, AF12)>, /* D27 */
<STM32_PINMUX('I', 2, AF12)>, /* D26 */
<STM32_PINMUX('I', 1, AF12)>, /* D25 */
<STM32_PINMUX('I', 0, AF12)>, /* D24 */
<STM32_PINMUX('H',15, AF12)>, /* D23 */
<STM32_PINMUX('H',14, AF12)>, /* D22 */
<STM32_PINMUX('H',13, AF12)>, /* D21 */
<STM32_PINMUX('H',12, AF12)>, /* D20 */
<STM32_PINMUX('H',11, AF12)>, /* D19 */
<STM32_PINMUX('H',10, AF12)>, /* D18 */
<STM32_PINMUX('H', 9, AF12)>, /* D17 */
<STM32_PINMUX('H', 8, AF12)>, /* D16 */
<STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
<STM32_PINMUX('E',15, AF12)>, /* D12 */
<STM32_PINMUX('E',14, AF12)>, /* D11 */
<STM32_PINMUX('E',13, AF12)>, /* D10 */
<STM32_PINMUX('E',12, AF12)>, /* D9 */
<STM32_PINMUX('E',11, AF12)>, /* D8 */
<STM32_PINMUX('E',10, AF12)>, /* D7 */
<STM32_PINMUX('E', 9, AF12)>, /* D6 */
<STM32_PINMUX('E', 8, AF12)>, /* D5 */
<STM32_PINMUX('E', 7, AF12)>, /* D4 */
<STM32_PINMUX('D', 1, AF12)>, /* D3 */
<STM32_PINMUX('D', 0, AF12)>, /* D2 */
<STM32_PINMUX('D',15, AF12)>, /* D1 */
<STM32_PINMUX('D',14, AF12)>, /* D0 */
<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
<STM32_PINMUX('F',15, AF12)>, /* A9 */
<STM32_PINMUX('F',14, AF12)>, /* A8 */
<STM32_PINMUX('F',13, AF12)>, /* A7 */
<STM32_PINMUX('F',12, AF12)>, /* A6 */
<STM32_PINMUX('F', 5, AF12)>, /* A5 */
<STM32_PINMUX('F', 4, AF12)>, /* A4 */
<STM32_PINMUX('F', 3, AF12)>, /* A3 */
<STM32_PINMUX('F', 2, AF12)>, /* A2 */
<STM32_PINMUX('F', 1, AF12)>, /* A1 */
<STM32_PINMUX('F', 0, AF12)>, /* A0 */
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
<STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* _FUNC_QUADSPI_CLK */
<STM32_PINMUX('B', 6, AF10)>, /*_FUNC_QUADSPI_BK1_NCS */
<STM32_PINMUX('F', 8, AF10)>, /* _FUNC_QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* _FUNC_QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 6, AF9)>, /* AF_FUNC_QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 7, AF9)>; /* _FUNC_QUADSPI_BK1_IO2 */
slew-rate = <2>;
};
};
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
};
&qspi {
qflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <108000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
};
};

226
arch/arm/dts/stm32746g-eval.dts
View file

@ -1,9 +1,5 @@
/*
* Copyright 2018 - Christophe Priouzeau <christophe.priouzeau@st.com>
*
* Based on:
* stm32f746-disco.dts from U-boot 2018.01
* Copyright 2016 - Lee Jones <lee.jones@linaro.org>
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -46,47 +42,61 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32F746G-EVAL board";
compatible = "st,stm32f746g-eval", "st,stm32f746";
model = "STMicroelectronics STM32746g-EVAL board";
compatible = "st,stm32746g-eval", "st,stm32f746";
chosen {
bootargs = "root=/dev/mmcblk0p1 rw rootwait";
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0xC0000000 0x2000000>;
reg = <0xc0000000 0x2000000>;
};
aliases {
serial0 = &usart1;
spi0 = &qspi;
mmc0 = &sdio;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpiof 10 0>;
leds {
compatible = "gpio-leds";
green {
gpios = <&gpiof 10 1>;
linux,default-trigger = "heartbeat";
};
red {
gpios = <&gpiob 7 1>;
};
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioc 13 0>;
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>;
};
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
mmc_vcard: mmc_vcard {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
@ -94,101 +104,30 @@
clock-frequency = <25000000>;
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
&crc {
status = "okay";
};
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F746_PA2_FUNC_ETH_MDIO>,
<STM32F746_PC1_FUNC_ETH_MDC>,
<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
slew-rate = <2>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
<STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
<STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
<STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
<STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
<STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
<STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
<STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
<STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
<STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
<STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
<STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
<STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
<STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
<STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
<STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
&rtc {
status = "okay";
};
<STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
<STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
<STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
<STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
<STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
<STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
<STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
<STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
<STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
<STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
<STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
<STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
<STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
<STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
<STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
<STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
<STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
<STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
<STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
<STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
<STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
<STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
<STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
<STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
<STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
<STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
<STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
<STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
<STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
<STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
<STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
<STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
<STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
<STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
<STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
<STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
<STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
<STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
slew-rate = <2>;
};
};
&sdio1 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
broken-cd;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_a>;
pinctrl-1 = <&sdio_pins_od_a>;
bus-width = <4>;
};
&usart1 {
@ -197,44 +136,11 @@
status = "okay";
};
&mac {
status = "okay";
pinctrl-0 = <&ethernet_mii>;
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&fmc {
pinctrl-0 = <&fmc_pins>;
&usbotg_hs {
dr_mode = "otg";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
status = "okay";
/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI
*/
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
TWR_1 TRCD_1>;
st,sdram-refcount = <1539>;
};
};
&sdio {
status = "okay";
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
bus-width = <4>;
max-frequency = <25000000>;
};

27
arch/arm/dts/stm32f4-pinctrl.dtsi
View file

@ -1,6 +1,5 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -342,12 +341,12 @@
sdio_pins: sdio_pins@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>,
<STM32_PINMUX('C', 9, AF12)>,
<STM32_PINMUX('C', 10, AF12)>,
<STM32_PINMUX('c', 11, AF12)>,
<STM32_PINMUX('C', 12, AF12)>,
<STM32_PINMUX('D', 2, AF12)>;
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
<STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
<STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
drive-push-pull;
slew-rate = <2>;
};
@ -355,17 +354,17 @@
sdio_pins_od: sdio_pins_od@0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>,
<STM32_PINMUX('C', 9, AF12)>,
<STM32_PINMUX('C', 10, AF12)>,
<STM32_PINMUX('C', 11, AF12)>,
<STM32_PINMUX('C', 12, AF12)>;
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
<STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>;
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
drive-open-drain;
slew-rate = <2>;
};

18
arch/arm/dts/stm32f429-disco-u-boot.dtsi
View file

@ -70,19 +70,11 @@
u-boot,dm-pre-reloc;
};
&clk_lse {
u-boot,dm-pre-reloc;
};
&clk_i2s_ckin {
u-boot,dm-pre-reloc;
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
&rcc {
&clk_lse {
u-boot,dm-pre-reloc;
};
@ -203,3 +195,11 @@
};
};
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
};

4
arch/arm/dts/stm32f429-disco.dts
View file

@ -1,6 +1,5 @@
/*
* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
* Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -76,6 +75,7 @@
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {

3
arch/arm/dts/stm32f429-pinctrl.dtsi
View file

@ -1,6 +1,5 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

33
arch/arm/dts/stm32f429.dtsi
View file

@ -1,6 +1,5 @@
/*
* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
* Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -259,6 +258,7 @@
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
@ -273,6 +273,7 @@
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
@ -296,7 +297,7 @@
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg>;
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@ -304,6 +305,7 @@
compatible = "st,stm32-iwdg";
reg = <0x40003000 0x400>;
clocks = <&clk_lsi>;
clock-names = "lsi";
status = "disabled";
};
@ -505,6 +507,17 @@
};
};
sdio: sdio@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
clock-names = "apb_pclk";
interrupts = <49>;
max-frequency = <48000000>;
status = "disabled";
};
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
@ -540,6 +553,7 @@
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
@ -554,6 +568,7 @@
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
@ -572,18 +587,6 @@
reg = <0x40007000 0x400>;
};
sdio: sdio@40012c00 {
compatible = "st,stm32f4xx-sdio";
reg = <0x40012c00 0x400>;
clocks = <&rcc 0 171>;
interrupts = <49>;
status = "disabled";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
};
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;

46
arch/arm/dts/stm32f469-disco-u-boot.dtsi
View file

@ -71,23 +71,11 @@
u-boot,dm-pre-reloc;
};
&clk_lse {
u-boot,dm-pre-reloc;
};
&clk_i2s_ckin {
u-boot,dm-pre-reloc;
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
&syscfg {
u-boot,dm-pre-reloc;
};
&rcc {
&clk_lse {
u-boot,dm-pre-reloc;
};
@ -147,16 +135,6 @@
};
&pinctrl {
usart3_pins_a: usart3@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
fmc_pins_d32: fmc_d32@0 {
u-boot,dm-pre-reloc;
pins
@ -226,4 +204,26 @@
u-boot,dm-pre-reloc;
};
};
usart3_pins_a: usart3@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
};
&syscfg {
u-boot,dm-pre-reloc;
};

86
arch/arm/dts/stm32f469-disco.dts
View file

@ -41,8 +41,10 @@
*/
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f469.dtsi"
#include "stm32f469-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32F469i-DISCO board";
@ -72,11 +74,40 @@
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
leds {
compatible = "gpio-leds";
green {
gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
orange {
gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
};
red {
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
};
blue {
gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
label = "User";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
};
};
/* This turns on vbus for otg for host mode (dwc2) */
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpiob 2 0>;
gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc5_host1";
regulator-always-on;
};
@ -90,6 +121,55 @@
clock-frequency = <8000000>;
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_out_dsi>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
panel-dsi@0 {
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
status = "okay";
port {
dsi_panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&ltdc {
dma-ranges;
status = "okay";
port {
ltdc_out_dsi: endpoint@0 {
remote-endpoint = <&dsi_in>;
};
};
};
&rtc {
status = "okay";
};
@ -125,6 +205,8 @@
&sdio {
status = "okay";
vmmc-supply = <&mmc_vcard>;
cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;

3
arch/arm/dts/stm32f469-pinctrl.dtsi
View file

@ -1,6 +1,5 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual

19
arch/arm/dts/stm32f469.dtsi Normal file
View file

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
#include "stm32f429.dtsi"
/ {
soc {
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
interrupts = <92>;
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
clock-names = "pclk", "ref";
status = "disabled";
};
};
};

289
arch/arm/dts/stm32f7-pinctrl.dtsi Normal file
View file

@ -0,0 +1,289 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
soc {
pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
cec_pins_a: cec@0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
slew-rate = <0>;
drive-open-drain;
bias-disable;
};
};
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_pins_b: usart1@1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
bias-disable;
};
};
i2c1_pins_b: i2c1@0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
usbotg_hs_pins_a: usbotg-hs@0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_hs_pins_b: usbotg-hs@1 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_fs_pins_a: usbotg-fs@0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_a: sdio_pins_a@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od_a: sdio_pins_od_a@0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
drive-open-drain;
slew-rate = <2>;
};
};
sdio_pins_b: sdio_pins_b@0 {
pins {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
<STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
<STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od_b: sdio_pins_od_b@0 {
pins1 {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
<STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
drive-open-drain;
slew-rate = <2>;
};
};
};
};
};

141
arch/arm/dts/stm32f7-u-boot.dtsi
View file

@ -1,21 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/memory/stm32-sdram.h>
/{
soc {
timer5: timer@40000c00 {
u-boot,dm-pre-reloc;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
u-boot,dm-pre-reloc;
};
mac: ethernet@40028000 {
compatible = "st,stm32-dwmac";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
snps,pbl = <8>;
snps,mixed-burst;
dma-ranges;
pinctrl-0 = <&ethernet_mii>;
phy-mode = "rmii";
phy-handle = <&phy0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
qspi: quadspi@A0001000 {
compatible = "st,stm32-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <92>;
spi-max-frequency = <108000000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
pinctrl-0 = <&qspi_pins>;
status = "okay";
};
};
};
&clk_hse {
u-boot,dm-pre-reloc;
};
&gpioa {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
compatible = "st,stm32-gpio";
};
&gpiok {
compatible = "st,stm32-gpio";
};
&pinctrl {
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
u-boot,dm-pre-reloc;
fmc_pins: fmc@0 {
u-boot,dm-pre-reloc;
pins
@ -25,16 +129,19 @@
};
};
&fmc {
bank1: bank@0 {
u-boot,dm-pre-reloc;
};
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
&clk_hse {
&rcc {
u-boot,dm-pre-reloc;
};
&timer5 {
u-boot,dm-pre-reloc;
};
&usart1 {
u-boot,dm-pre-reloc;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
};

251
arch/arm/dts/stm32f746-disco-u-boot.dtsi Normal file
View file

@ -0,0 +1,251 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32f7-u-boot.dtsi>
/{
chosen {
bootargs = "root=/dev/ram rdinit=/linuxrc";
};
aliases {
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdio1;
spi0 = &qspi;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpiok 3 0>;
status = "okay";
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpioi 1 0>;
};
panel-rgb@0 {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpioi 12 0>;
status = "okay";
display-timings {
timing@0 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <2>;
hback-porch = <2>;
hsync-len = <41>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
};
soc {
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;
resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
pinctrl-0 = <&ltdc_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
};
};
&clk_hse {
u-boot,dm-pre-reloc;
};
&fmc {
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
u-boot,dm-pre-reloc;
st,sdram-control = /bits/ 8 <NO_COL_8
NO_ROW_12
MWIDTH_16
BANKS_4
CAS_3
SDCLK_2
RD_BURST_EN
RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_2
TXSR_6
TRAS_4
TRC_6
TWR_2
TRP_2
TRCD_2>;
/* refcount = (64msec/total_row_sdram)*freq - 20 */
st,sdram-refcount = < 1542 >;
};
};
&pinctrl {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
<STM32_PINMUX('E',15, AF12)>, /* D12 */
<STM32_PINMUX('E',14, AF12)>, /* D11 */
<STM32_PINMUX('E',13, AF12)>, /* D10 */
<STM32_PINMUX('E',12, AF12)>, /* D9 */
<STM32_PINMUX('E',11, AF12)>, /* D8 */
<STM32_PINMUX('E',10, AF12)>, /* D7 */
<STM32_PINMUX('E', 9, AF12)>, /* D6 */
<STM32_PINMUX('E', 8, AF12)>, /* D5 */
<STM32_PINMUX('E', 7, AF12)>, /* D4 */
<STM32_PINMUX('D', 1, AF12)>, /* D3 */
<STM32_PINMUX('D', 0, AF12)>, /* D2 */
<STM32_PINMUX('D',15, AF12)>, /* D1 */
<STM32_PINMUX('D',14, AF12)>, /* D0 */
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
<STM32_PINMUX('F',15, AF12)>, /* A9 */
<STM32_PINMUX('F',14, AF12)>, /* A8 */
<STM32_PINMUX('F',13, AF12)>, /* A7 */
<STM32_PINMUX('F',12, AF12)>, /* A6 */
<STM32_PINMUX('F', 5, AF12)>, /* A5 */
<STM32_PINMUX('F', 4, AF12)>, /* A4 */
<STM32_PINMUX('F', 3, AF12)>, /* A3 */
<STM32_PINMUX('F', 2, AF12)>, /* A2 */
<STM32_PINMUX('F', 1, AF12)>, /* A1 */
<STM32_PINMUX('F', 0, AF12)>, /* A0 */
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
<STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
<STM32_PINMUX('G',12, AF14)>, /* B4 */
<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* CLK */
<STM32_PINMUX('I',15, AF14)>, /* R0 */
<STM32_PINMUX('J', 0, AF14)>, /* R1 */
<STM32_PINMUX('J', 1, AF14)>, /* R2 */
<STM32_PINMUX('J', 2, AF14)>, /* R3 */
<STM32_PINMUX('J', 3, AF14)>, /* R4 */
<STM32_PINMUX('J', 4, AF14)>, /* R5 */
<STM32_PINMUX('J', 5, AF14)>, /* R6 */
<STM32_PINMUX('J', 6, AF14)>, /* R7 */
<STM32_PINMUX('J', 7, AF14)>, /* G0 */
<STM32_PINMUX('J', 8, AF14)>, /* G1 */
<STM32_PINMUX('J', 9, AF14)>, /* G2 */
<STM32_PINMUX('J',10, AF14)>, /* G3 */
<STM32_PINMUX('J',11, AF14)>, /* G4 */
<STM32_PINMUX('J',13, AF14)>, /* B1 */
<STM32_PINMUX('J',14, AF14)>, /* B2 */
<STM32_PINMUX('J',15, AF14)>, /* B3 */
<STM32_PINMUX('K', 0, AF14)>, /* G5 */
<STM32_PINMUX('K', 1, AF14)>, /* G6 */
<STM32_PINMUX('K', 2, AF14)>, /* G7 */
<STM32_PINMUX('K', 4, AF14)>, /* B5 */
<STM32_PINMUX('K', 5, AF14)>, /* B6 */
<STM32_PINMUX('K', 6, AF14)>, /* B7 */
<STM32_PINMUX('K', 7, AF14)>; /* DE */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
<STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
<STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
<STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
<STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
slew-rate = <2>;
};
};
usart1_pins_b: usart1@1 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
&qspi {
qflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a13", "jedec,spi-nor";
spi-max-frequency = <108000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
memory-map = <0x90000000 0x1000000>;
reg = <0>;
};
};
&timer5 {
u-boot,dm-pre-reloc;
};

281
arch/arm/dts/stm32f746-disco.dts
View file

@ -1,10 +1,5 @@
/*
* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
*
* Based on:
* stm32f469-disco.dts from Linux
* Copyright 2016 - Lee Jones <lee.jones@linaro.org>
* Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -47,7 +42,8 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@ -55,7 +51,7 @@
compatible = "st,stm32f746-disco", "st,stm32f746";
chosen {
bootargs = "root=/dev/ram rdinit=/linuxrc";
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
@ -65,61 +61,28 @@
aliases {
serial0 = &usart1;
spi0 = &qspi;
mmc0 = &sdio;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpioi 1 0>;
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
/* This turns on vbus for otg fs for host mode (dwc2) */
vcc5v_otg_fs: vcc5v-otg-fs-regulator {
compatible = "regulator-fixed";
gpio = <&gpiod 5 0>;
regulator-name = "vcc5_host1";
regulator-always-on;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpiok 3 0>;
status = "okay";
};
panel-rgb@0 {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpioi 12 0>;
status = "okay";
display-timings {
timing@0 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <2>;
hback-porch = <2>;
hsync-len = <41>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
mmc_vcard: mmc_vcard {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
@ -127,196 +90,42 @@
clock-frequency = <25000000>;
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
bias-disable;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F746_PA2_FUNC_ETH_MDIO>,
<STM32F746_PC1_FUNC_ETH_MDC>,
<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
<STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
<STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
<STM32F746_PD9_FUNC_FMC_D14>,
<STM32F746_PD8_FUNC_FMC_D13>,
<STM32F746_PE15_FUNC_FMC_D12>,
<STM32F746_PE14_FUNC_FMC_D11>,
<STM32F746_PE13_FUNC_FMC_D10>,
<STM32F746_PE12_FUNC_FMC_D9>,
<STM32F746_PE11_FUNC_FMC_D8>,
<STM32F746_PE10_FUNC_FMC_D7>,
<STM32F746_PE9_FUNC_FMC_D6>,
<STM32F746_PE8_FUNC_FMC_D5>,
<STM32F746_PE7_FUNC_FMC_D4>,
<STM32F746_PD1_FUNC_FMC_D3>,
<STM32F746_PD0_FUNC_FMC_D2>,
<STM32F746_PD15_FUNC_FMC_D1>,
<STM32F746_PD14_FUNC_FMC_D0>,
<STM32F746_PE1_FUNC_FMC_NBL1>,
<STM32F746_PE0_FUNC_FMC_NBL0>,
<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
<STM32F746_PG1_FUNC_FMC_A11>,
<STM32F746_PG0_FUNC_FMC_A10>,
<STM32F746_PF15_FUNC_FMC_A9>,
<STM32F746_PF14_FUNC_FMC_A8>,
<STM32F746_PF13_FUNC_FMC_A7>,
<STM32F746_PF12_FUNC_FMC_A6>,
<STM32F746_PF5_FUNC_FMC_A5>,
<STM32F746_PF4_FUNC_FMC_A4>,
<STM32F746_PF3_FUNC_FMC_A3>,
<STM32F746_PF2_FUNC_FMC_A2>,
<STM32F746_PF1_FUNC_FMC_A1>,
<STM32F746_PF0_FUNC_FMC_A0>,
<STM32F746_PH3_FUNC_FMC_SDNE0>,
<STM32F746_PH5_FUNC_FMC_SDNWE>,
<STM32F746_PF11_FUNC_FMC_SDNRAS>,
<STM32F746_PG15_FUNC_FMC_SDNCAS>,
<STM32F746_PC3_FUNC_FMC_SDCKE0>,
<STM32F746_PG8_FUNC_FMC_SDCLK>;
slew-rate = <2>;
};
};
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
<STM32F746_PG12_FUNC_LCD_B4>,
<STM32F746_PI9_FUNC_LCD_VSYNC>,
<STM32F746_PI10_FUNC_LCD_HSYNC>,
<STM32F746_PI14_FUNC_LCD_CLK>,
<STM32F746_PI15_FUNC_LCD_R0>,
<STM32F746_PJ0_FUNC_LCD_R1>,
<STM32F746_PJ1_FUNC_LCD_R2>,
<STM32F746_PJ2_FUNC_LCD_R3>,
<STM32F746_PJ3_FUNC_LCD_R4>,
<STM32F746_PJ4_FUNC_LCD_R5>,
<STM32F746_PJ5_FUNC_LCD_R6>,
<STM32F746_PJ6_FUNC_LCD_R7>,
<STM32F746_PJ7_FUNC_LCD_G0>,
<STM32F746_PJ8_FUNC_LCD_G1>,
<STM32F746_PJ9_FUNC_LCD_G2>,
<STM32F746_PJ10_FUNC_LCD_G3>,
<STM32F746_PJ11_FUNC_LCD_G4>,
<STM32F746_PJ13_FUNC_LCD_B1>,
<STM32F746_PJ14_FUNC_LCD_B2>,
<STM32F746_PJ15_FUNC_LCD_B3>,
<STM32F746_PK0_FUNC_LCD_G5>,
<STM32F746_PK1_FUNC_LCD_G6>,
<STM32F746_PK2_FUNC_LCD_G7>,
<STM32F746_PK4_FUNC_LCD_B5>,
<STM32F746_PK5_FUNC_LCD_B6>,
<STM32F746_PK6_FUNC_LCD_B7>,
<STM32F746_PK7_FUNC_LCD_DE>;
slew-rate = <2>;
};
};
&sdio1 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_a>;
pinctrl-1 = <&sdio_pins_od_a>;
bus-width = <4>;
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-0 = <&usart1_pins_b>;
pinctrl-names = "default";
status = "okay";
};
&fmc {
pinctrl-0 = <&fmc_pins>;
&usbotg_fs {
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_a>;
pinctrl-names = "default";
status = "okay";
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
CAS_3 SDCLK_2 RD_BURST_EN
RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
TRP_2 TRCD_2>;
/* refcount = (64msec/total_row_sdram)*freq - 20 */
st,sdram-refcount = < 1542 >;
};
};
&mac {
&usbotg_hs {
dr_mode = "host";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_b>;
pinctrl-names = "default";
status = "okay";
pinctrl-0 = <&ethernet_mii>;
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&qspi {
pinctrl-0 = <&qspi_pins>;
status = "okay";
qflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a13", "jedec,spi-nor";
spi-max-frequency = <108000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
memory-map = <0x90000000 0x1000000>;
reg = <0>;
};
};
&sdio {
status = "okay";
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
bus-width = <4>;
max-frequency = <25000000>;
};
&ltdc {
status = "okay";
pinctrl-0 = <&ltdc_pins>;
};

11
arch/arm/dts/stm32f746-pinctrl.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include "stm32f7-pinctrl.dtsi"
&pinctrl{
compatible = "st,stm32f746-pinctrl";
};

813
arch/arm/dts/stm32f746.dtsi
View file

@ -1,9 +1,4 @@
/*
* Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
* Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
*
* Based on:
* stm32f429.dtsi from Linux
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
@ -45,8 +40,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@ -57,272 +52,112 @@
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_i2s_ckin: clk-i2s-ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
};
soc {
u-boot,dm-pre-reloc;
mac: ethernet@40028000 {
compatible = "st,stm32-dwmac";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
snps,pbl = <8>;
snps,mixed-burst;
dma-ranges;
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
u-boot,dm-pre-reloc;
};
qspi: quadspi@A0001000 {
compatible = "st,stm32-qspi";
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <92>;
spi-max-frequency = <108000000>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@1 {
compatible = "st,stm32-timer-trigger";
reg = <1>;
status = "disabled";
};
};
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
status = "disabled";
u-boot,dm-pre-reloc;
};
pwrcfg: power-config@58024800 {
compatible = "syscon";
reg = <0x40007000 0x400>;
};
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
st,syscfg = <&pwrcfg>;
u-boot,dm-pre-reloc;
};
pinctrl: pin-controller {
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f746-pinctrl";
ranges = <0 0x40020000 0x3000>;
u-boot,dm-pre-reloc;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
u-boot,dm-pre-reloc;
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
u-boot,dm-pre-reloc;
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
u-boot,dm-pre-reloc;
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
u-boot,dm-pre-reloc;
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
u-boot,dm-pre-reloc;
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
u-boot,dm-pre-reloc;
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
u-boot,dm-pre-reloc;
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
u-boot,dm-pre-reloc;
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
u-boot,dm-pre-reloc;
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
u-boot,dm-pre-reloc;
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
u-boot,dm-pre-reloc;
};
sdio_pins: sdio_pins@0 {
pins {
pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
<STM32F746_PC9_FUNC_SDMMC1_D1>,
<STM32F746_PC10_FUNC_SDMMC1_D2>,
<STM32F746_PC11_FUNC_SDMMC1_D3>,
<STM32F746_PC12_FUNC_SDMMC1_CK>,
<STM32F746_PD2_FUNC_SDMMC1_CMD>;
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od: sdio_pins_od@0 {
pins1 {
pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
<STM32F746_PC9_FUNC_SDMMC1_D1>,
<STM32F746_PC10_FUNC_SDMMC1_D2>,
<STM32F746_PC11_FUNC_SDMMC1_D3>,
<STM32F746_PC12_FUNC_SDMMC1_CK>;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
drive-open-drain;
slew-rate = <2>;
};
};
sdio_pins_b: sdio_pins_b@0 {
pins {
pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
<STM32F769_PG10_FUNC_SDMMC2_D1>,
<STM32F769_PB3_FUNC_SDMMC2_D2>,
<STM32F769_PB4_FUNC_SDMMC2_D3>,
<STM32F769_PD6_FUNC_SDMMC2_CLK>,
<STM32F769_PD7_FUNC_SDMMC2_CMD>;
drive-push-pull;
slew-rate = <2>;
};
};
sdio_pins_od_b: sdio_pins_od_b@0 {
pins1 {
pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
<STM32F769_PG10_FUNC_SDMMC2_D1>,
<STM32F769_PB3_FUNC_SDMMC2_D2>,
<STM32F769_PB4_FUNC_SDMMC2_D3>,
<STM32F769_PD6_FUNC_SDMMC2_CLK>;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
drive-open-drain;
slew-rate = <2>;
};
};
};
sdio: sdio@40012c00 {
compatible = "st,stm32f4xx-sdio";
reg = <0x40012c00 0x400>;
clocks = <&rcc 0 171>;
interrupts = <49>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
clock-names = "int";
status = "disabled";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@2 {
compatible = "st,stm32-timer-trigger";
reg = <2>;
status = "disabled";
};
};
sdio2: sdio2@40011c00 {
compatible = "st,stm32f4xx-sdio";
reg = <0x40011c00 0x400>;
clocks = <&rcc 0 167>;
interrupts = <103>;
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
pinctrl-0 = <&sdio_pins_b>;
pinctrl-1 = <&sdio_pins_od_b>;
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@3 {
compatible = "st,stm32-timer-trigger";
reg = <3>;
status = "disabled";
};
};
timer5: timer@40000c00 {
@ -332,17 +167,469 @@
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;
resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
u-boot,dm-pre-reloc;
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@4 {
compatible = "st,stm32-timer-trigger";
reg = <4>;
status = "disabled";
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
clock-names = "int";
status = "disabled";
timer@5 {
compatible = "st,stm32-timer-trigger";
reg = <5>;
status = "disabled";
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
clock-names = "int";
status = "disabled";
timer@6 {
compatible = "st,stm32-timer-trigger";
reg = <6>;
status = "disabled";
};
};
timers12: timers@40001800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@11 {
compatible = "st,stm32-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
clocks = <&rcc 1 CLK_USART2>;
status = "disabled";
};
usart3: serial@40004800 {
compatible = "st,stm32f7-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
clocks = <&rcc 1 CLK_USART3>;
status = "disabled";
};
usart4: serial@40004c00 {
compatible = "st,stm32f7-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
clocks = <&rcc 1 CLK_UART4>;
status = "disabled";
};
usart5: serial@40005000 {
compatible = "st,stm32f7-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
clocks = <&rcc 1 CLK_UART5>;
status = "disabled";
};
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
reg = <0x40005400 0x400>;
interrupts = <31>,
<32>;
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@40005800 {
compatible = "st,stm32f7-i2c";
reg = <0x40005800 0x400>;
interrupts = <33>,
<34>;
resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
clocks = <&rcc 1 CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@40005C00 {
compatible = "st,stm32f7-i2c";
reg = <0x40005C00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
clocks = <&rcc 1 CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@40006000 {
compatible = "st,stm32f7-i2c";
reg = <0x40006000 0x400>;
interrupts = <95>,
<96>;
resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
clocks = <&rcc 1 CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cec: cec@40006c00 {
compatible = "st,stm32-cec";
reg = <0x40006C00 0x400>;
interrupts = <94>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
usart7: serial@40007800 {
compatible = "st,stm32f7-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
clocks = <&rcc 1 CLK_UART7>;
status = "disabled";
};
usart8: serial@40007c00 {
compatible = "st,stm32f7-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
clocks = <&rcc 1 CLK_UART8>;
status = "disabled";
};
timers1: timers@40010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@0 {
compatible = "st,stm32-timer-trigger";
reg = <0>;
status = "disabled";
};
};
timers8: timers@40010400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@7 {
compatible = "st,stm32-timer-trigger";
reg = <7>;
status = "disabled";
};
};
usart1: serial@40011000 {
compatible = "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 1 CLK_USART1>;
status = "disabled";
};
usart6: serial@40011400 {
compatible = "st,stm32f7-uart";
reg = <0x40011400 0x400>;
interrupts = <71>;
clocks = <&rcc 1 CLK_USART6>;
status = "disabled";
};
sdio2: sdio2@40011c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40011c00 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
clock-names = "apb_pclk";
interrupts = <103>;
max-frequency = <48000000>;
status = "disabled";
};
sdio1: sdio1@40012c00 {
compatible = "arm,pl180", "arm,primecell";
arm,primecell-periphid = <0x00880180>;
reg = <0x40012c00 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
clock-names = "apb_pclk";
interrupts = <49>;
max-frequency = <48000000>;
status = "disabled";
};
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
};
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40013C00 0x400>;
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
timers9: timers@40014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@8 {
compatible = "st,stm32-timer-trigger";
reg = <8>;
status = "disabled";
};
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
pwrcfg: power-config@40007000 {
compatible = "syscon";
reg = <0x40007000 0x400>;
};
crc: crc@40023000 {
compatible = "st,stm32f7-crc";
reg = <0x40023000 0x400>;
clocks = <&rcc 0 12>;
status = "disabled";
};
rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
assigned-clock-rates = <1000000>;
};
dma1: dma@40026000 {
compatible = "st,stm32-dma";
reg = <0x40026000 0x400>;
interrupts = <11>,
<12>,
<13>,
<14>,
<15>,
<16>,
<17>,
<47>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
#dma-cells = <4>;
status = "disabled";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma";
reg = <0x40026400 0x400>;
interrupts = <56>,
<57>,
<58>,
<59>,
<60>,
<68>,
<69>,
<70>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
#dma-cells = <4>;
st,mem2mem;
status = "disabled";
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32f7-hsotg";
reg = <0x40040000 0x40000>;
interrupts = <77>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
clock-names = "otg";
g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
status = "disabled";
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32f4x9-fsotg";
reg = <0x50000000 0x40000>;
interrupts = <67>;
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
clock-names = "otg";
status = "disabled";
};
};
};
&systick {
clocks = <&rcc 1 0>;
status = "okay";
};

165
arch/arm/dts/stm32f769-disco-u-boot.dtsi Normal file
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@ -0,0 +1,165 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32f7-u-boot.dtsi>
/{
chosen {
bootargs = "root=/dev/ram rdinit=/linuxrc";
};
aliases {
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdio2;
spi0 = &qspi;
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioa 0 0>;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpioj 5 0>;
};
};
&fmc {
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
u-boot,dm-pre-reloc;
st,sdram-control = /bits/ 8 <NO_COL_8
NO_ROW_12
MWIDTH_32
BANKS_4
CAS_3
SDCLK_2
RD_BURST_EN
RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_2
TXSR_6
TRAS_4
TRC_6
TWR_2
TRP_2
TRCD_2>;
/* refcount = (64msec/total_row_sdram)*freq - 20 */
st,sdram-refcount = < 1542 >;
};
};
&pinctrl {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
<STM32_PINMUX('I', 9, AF12)>, /* D30 */
<STM32_PINMUX('I', 7, AF12)>, /* D29 */
<STM32_PINMUX('I', 6, AF12)>, /* D28 */
<STM32_PINMUX('I', 3, AF12)>, /* D27 */
<STM32_PINMUX('I', 2, AF12)>, /* D26 */
<STM32_PINMUX('I', 1, AF12)>, /* D25 */
<STM32_PINMUX('I', 0, AF12)>, /* D24 */
<STM32_PINMUX('H',15, AF12)>, /* D23 */
<STM32_PINMUX('H',14, AF12)>, /* D22 */
<STM32_PINMUX('H',13, AF12)>, /* D21 */
<STM32_PINMUX('H',12, AF12)>, /* D20 */
<STM32_PINMUX('H',11, AF12)>, /* D19 */
<STM32_PINMUX('H',10, AF12)>, /* D18 */
<STM32_PINMUX('H', 9, AF12)>, /* D17 */
<STM32_PINMUX('H', 8, AF12)>, /* D16 */
<STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
<STM32_PINMUX('E',15, AF12)>, /* D12 */
<STM32_PINMUX('E',14, AF12)>, /* D11 */
<STM32_PINMUX('E',13, AF12)>, /* D10 */
<STM32_PINMUX('E',12, AF12)>, /* D9 */
<STM32_PINMUX('E',11, AF12)>, /* D8 */
<STM32_PINMUX('E',10, AF12)>, /* D7 */
<STM32_PINMUX('E', 9, AF12)>, /* D6 */
<STM32_PINMUX('E', 8, AF12)>, /* D5 */
<STM32_PINMUX('E', 7, AF12)>, /* D4 */
<STM32_PINMUX('D', 1, AF12)>, /* D3 */
<STM32_PINMUX('D', 0, AF12)>, /* D2 */
<STM32_PINMUX('D',15, AF12)>, /* D1 */
<STM32_PINMUX('D',14, AF12)>, /* D0 */
<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
<STM32_PINMUX('F',15, AF12)>, /* A9 */
<STM32_PINMUX('F',14, AF12)>, /* A8 */
<STM32_PINMUX('F',13, AF12)>, /* A7 */
<STM32_PINMUX('F',12, AF12)>, /* A6 */
<STM32_PINMUX('F', 5, AF12)>, /* A5 */
<STM32_PINMUX('F', 4, AF12)>, /* A4 */
<STM32_PINMUX('F', 3, AF12)>, /* A3 */
<STM32_PINMUX('F', 2, AF12)>, /* A2 */
<STM32_PINMUX('F', 1, AF12)>, /* A1 */
<STM32_PINMUX('F', 0, AF12)>, /* A0 */
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
<STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
<STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
<STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
<STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
slew-rate = <2>;
};
};
};
&qspi {
flash0: mx66l51235l {
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};

252
arch/arm/dts/stm32f769-disco.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright 2016 - Vikas Manocha <vikas.manocha@st.com>
* Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -42,15 +42,16 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
#include "stm32f769-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F769-DISCO board";
compatible = "st,stm32f769-disco", "st,stm32f7";
compatible = "st,stm32f769-disco", "st,stm32f769";
chosen {
bootargs = "root=/dev/ram rdinit=/linuxrc";
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
@ -60,144 +61,77 @@
aliases {
serial0 = &usart1;
spi0 = &qspi;
mmc0 = &sdio2;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
};
led1 {
compatible = "st,led1";
led-gpio = <&gpioj 5 0>;
leds {
compatible = "gpio-leds";
green {
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
red {
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
};
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioa 0 0>;
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
};
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
mmc_vcard: mmc_vcard {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cec {
pinctrl-0 = <&cec_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&clk_hse {
clock-frequency = <25000000>;
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F746_PA2_FUNC_ETH_MDIO>,
<STM32F746_PC1_FUNC_ETH_MDC>,
<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
slew-rate = <2>;
};
};
&rtc {
status = "okay";
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
<STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
<STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
slew-rate = <2>;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
<STM32F746_PI9_FUNC_FMC_D30>,
<STM32F746_PI7_FUNC_FMC_D29>,
<STM32F746_PI6_FUNC_FMC_D28>,
<STM32F746_PI3_FUNC_FMC_D27>,
<STM32F746_PI2_FUNC_FMC_D26>,
<STM32F746_PI1_FUNC_FMC_D25>,
<STM32F746_PI0_FUNC_FMC_D24>,
<STM32F746_PH15_FUNC_FMC_D23>,
<STM32F746_PH14_FUNC_FMC_D22>,
<STM32F746_PH13_FUNC_FMC_D21>,
<STM32F746_PH12_FUNC_FMC_D20>,
<STM32F746_PH11_FUNC_FMC_D19>,
<STM32F746_PH10_FUNC_FMC_D18>,
<STM32F746_PH9_FUNC_FMC_D17>,
<STM32F746_PH8_FUNC_FMC_D16>,
<STM32F746_PD10_FUNC_FMC_D15>,
<STM32F746_PD9_FUNC_FMC_D14>,
<STM32F746_PD8_FUNC_FMC_D13>,
<STM32F746_PE15_FUNC_FMC_D12>,
<STM32F746_PE14_FUNC_FMC_D11>,
<STM32F746_PE13_FUNC_FMC_D10>,
<STM32F746_PE12_FUNC_FMC_D9>,
<STM32F746_PE11_FUNC_FMC_D8>,
<STM32F746_PE10_FUNC_FMC_D7>,
<STM32F746_PE9_FUNC_FMC_D6>,
<STM32F746_PE8_FUNC_FMC_D5>,
<STM32F746_PE7_FUNC_FMC_D4>,
<STM32F746_PD1_FUNC_FMC_D3>,
<STM32F746_PD0_FUNC_FMC_D2>,
<STM32F746_PD15_FUNC_FMC_D1>,
<STM32F746_PD14_FUNC_FMC_D0>,
<STM32F746_PI5_FUNC_FMC_NBL3>,
<STM32F746_PI4_FUNC_FMC_NBL2>,
<STM32F746_PE1_FUNC_FMC_NBL1>,
<STM32F746_PE0_FUNC_FMC_NBL0>,
<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
<STM32F746_PG1_FUNC_FMC_A11>,
<STM32F746_PG0_FUNC_FMC_A10>,
<STM32F746_PF15_FUNC_FMC_A9>,
<STM32F746_PF14_FUNC_FMC_A8>,
<STM32F746_PF13_FUNC_FMC_A7>,
<STM32F746_PF12_FUNC_FMC_A6>,
<STM32F746_PF5_FUNC_FMC_A5>,
<STM32F746_PF4_FUNC_FMC_A4>,
<STM32F746_PF3_FUNC_FMC_A3>,
<STM32F746_PF2_FUNC_FMC_A2>,
<STM32F746_PF1_FUNC_FMC_A1>,
<STM32F746_PF0_FUNC_FMC_A0>,
<STM32F746_PH3_FUNC_FMC_SDNE0>,
<STM32F746_PH5_FUNC_FMC_SDNWE>,
<STM32F746_PF11_FUNC_FMC_SDNRAS>,
<STM32F746_PG15_FUNC_FMC_SDNCAS>,
<STM32F746_PH2_FUNC_FMC_SDCKE0>,
<STM32F746_PG8_FUNC_FMC_SDCLK>;
slew-rate = <2>;
};
};
&sdio2 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_b>;
pinctrl-1 = <&sdio_pins_od_b>;
bus-width = <4>;
};
&usart1 {
@ -206,61 +140,11 @@
status = "okay";
};
&fmc {
pinctrl-0 = <&fmc_pins>;
&usbotg_hs {
dr_mode = "otg";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
status = "okay";
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
CAS_3 SDCLK_2 RD_BURST_EN
RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
TRP_2 TRCD_2>;
/* refcount = (64msec/total_row_sdram)*freq - 20 */
st,sdram-refcount = < 1542 >;
};
};
&mac {
status = "okay";
pinctrl-0 = <&ethernet_mii>;
phy-mode = "rmii";
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&qspi {
pinctrl-0 = <&qspi_pins>;
status = "okay";
qflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a13", "jedec,spi-nor";
spi-max-frequency = <108000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
memory-map = <0x90000000 0x1000000>;
reg = <0>;
};
};
&sdio2 {
status = "okay";
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_b>;
pinctrl-1 = <&sdio_pins_od_b>;
bus-width = <4>;
max-frequency = <25000000>;
};

11
arch/arm/dts/stm32f769-pinctrl.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
#include "stm32f7-pinctrl.dtsi"
&pinctrl{
compatible = "st,stm32f769-pinctrl";
};

279
arch/arm/dts/stm32h7-u-boot.dtsi
View file

@ -1,13 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/memory/stm32-sdram.h>
/{
clocks {
u-boot,dm-pre-reloc;
};
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
mmc0 = &sdmmc1;
};
soc {
u-boot,dm-pre-reloc;
pin-controller {
u-boot,dm-pre-reloc;
};
fmc: fmc@52004000 {
compatible = "st,stm32h7-fmc";
reg = <0x52004000 0x1000>;
clocks = <&rcc FMC_CK>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI
* firsct bank is bank@0
* second bank is bank@1
*/
bank1: bank@1 {
st,sdram-control = /bits/ 8 <NO_COL_9
NO_ROW_12
MWIDTH_32
BANKS_4
CAS_2
SDCLK_3
RD_BURST_EN
RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1
TXSR_1
TRAS_1
TRC_6
TRP_2
TWR_1
TRCD_1>;
st,sdram-refcount = <1539>;
};
};
sdmmc1: sdmmc@52007000 {
compatible = "st,stm32-sdmmc2";
reg = <0x52007000 0x1000>;
interrupts = <49>;
clocks = <&rcc SDMMC1_CK>;
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
};
};
@ -15,14 +79,171 @@
u-boot,dm-pre-reloc;
};
&clk_i2s {
u-boot,dm-pre-reloc;
};
&clk_lse {
u-boot,dm-pre-reloc;
};
&clk_i2s {
&fmc {
u-boot,dm-pre-reloc;
};
&gpioa {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpiob {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpioc {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpiod {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpioe {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpiof {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpiog {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpioh {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpioi {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpioj {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&gpiok {
u-boot,dm-pre-reloc;
compatible = "st,stm32-gpio";
};
&pinctrl {
fmc_pins: fmc@0 {
pins {
pinmux = <STM32_PINMUX('D', 0, AF12)>,
<STM32_PINMUX('D', 1, AF12)>,
<STM32_PINMUX('D', 8, AF12)>,
<STM32_PINMUX('D', 9, AF12)>,
<STM32_PINMUX('D',10, AF12)>,
<STM32_PINMUX('D',14, AF12)>,
<STM32_PINMUX('D',15, AF12)>,
<STM32_PINMUX('E', 0, AF12)>,
<STM32_PINMUX('E', 1, AF12)>,
<STM32_PINMUX('E', 7, AF12)>,
<STM32_PINMUX('E', 8, AF12)>,
<STM32_PINMUX('E', 9, AF12)>,
<STM32_PINMUX('E',10, AF12)>,
<STM32_PINMUX('E',11, AF12)>,
<STM32_PINMUX('E',12, AF12)>,
<STM32_PINMUX('E',13, AF12)>,
<STM32_PINMUX('E',14, AF12)>,
<STM32_PINMUX('E',15, AF12)>,
<STM32_PINMUX('F', 0, AF12)>,
<STM32_PINMUX('F', 1, AF12)>,
<STM32_PINMUX('F', 2, AF12)>,
<STM32_PINMUX('F', 3, AF12)>,
<STM32_PINMUX('F', 4, AF12)>,
<STM32_PINMUX('F', 5, AF12)>,
<STM32_PINMUX('F',11, AF12)>,
<STM32_PINMUX('F',12, AF12)>,
<STM32_PINMUX('F',13, AF12)>,
<STM32_PINMUX('F',14, AF12)>,
<STM32_PINMUX('F',15, AF12)>,
<STM32_PINMUX('G', 0, AF12)>,
<STM32_PINMUX('G', 1, AF12)>,
<STM32_PINMUX('G', 2, AF12)>,
<STM32_PINMUX('G', 4, AF12)>,
<STM32_PINMUX('G', 5, AF12)>,
<STM32_PINMUX('G', 8, AF12)>,
<STM32_PINMUX('G',15, AF12)>,
<STM32_PINMUX('H', 5, AF12)>,
<STM32_PINMUX('H', 6, AF12)>,
<STM32_PINMUX('H', 7, AF12)>,
<STM32_PINMUX('H', 8, AF12)>,
<STM32_PINMUX('H', 9, AF12)>,
<STM32_PINMUX('H',10, AF12)>,
<STM32_PINMUX('H',11, AF12)>,
<STM32_PINMUX('H',12, AF12)>,
<STM32_PINMUX('H',13, AF12)>,
<STM32_PINMUX('H',14, AF12)>,
<STM32_PINMUX('H',15, AF12)>,
<STM32_PINMUX('I', 0, AF12)>,
<STM32_PINMUX('I', 1, AF12)>,
<STM32_PINMUX('I', 2, AF12)>,
<STM32_PINMUX('I', 3, AF12)>,
<STM32_PINMUX('I', 4, AF12)>,
<STM32_PINMUX('I', 5, AF12)>,
<STM32_PINMUX('I', 6, AF12)>,
<STM32_PINMUX('I', 7, AF12)>,
<STM32_PINMUX('I', 9, AF12)>,
<STM32_PINMUX('I',10, AF12)>;
slew-rate = <3>;
};
};
pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
pins {
pinmux = <STM32_PINMUX('B', 8, AF7)>,
<STM32_PINMUX('B', 9, AF7)>,
<STM32_PINMUX('C', 6, AF8)>,
<STM32_PINMUX('C', 7, AF8)>;
drive-push-pull;
slew-rate = <3>;
};
};
sdmmc1_pins: sdmmc@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>,
<STM32_PINMUX('C', 9, AF12)>,
<STM32_PINMUX('C',10, AF12)>,
<STM32_PINMUX('C',11, AF12)>,
<STM32_PINMUX('C',12, AF12)>,
<STM32_PINMUX('D', 2, AF12)>;
slew-rate = <3>;
drive-push-pull;
bias-disable;
};
};
};
&pwrcfg {
u-boot,dm-pre-reloc;
};
@ -30,59 +251,3 @@
&rcc {
u-boot,dm-pre-reloc;
};
&fmc {
u-boot,dm-pre-reloc;
};
&clk_hsi {
u-boot,dm-pre-reloc;
};
&clk_csi {
u-boot,dm-pre-reloc;
};
&gpioa {
u-boot,dm-pre-reloc;
};
&gpiob {
u-boot,dm-pre-reloc;
};
&gpioc {
u-boot,dm-pre-reloc;
};
&gpiod {
u-boot,dm-pre-reloc;
};
&gpioe {
u-boot,dm-pre-reloc;
};
&gpiof {
u-boot,dm-pre-reloc;
};
&gpiog {
u-boot,dm-pre-reloc;
};
&gpioh {
u-boot,dm-pre-reloc;
};
&gpioi {
u-boot,dm-pre-reloc;
};
&gpioj {
u-boot,dm-pre-reloc;
};
&gpiok {
u-boot,dm-pre-reloc;
};

160
arch/arm/dts/stm32h743-pinctrl.dtsi
View file

@ -40,234 +40,182 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ {
soc {
pin-controller {
pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
interrupt-controller;
#interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
interrupt-controller;
#interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
interrupt-controller;
#interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
interrupt-controller;
#interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
interrupt-controller;
#interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
interrupt-controller;
#interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
interrupt-controller;
#interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
interrupt-controller;
#interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
interrupt-controller;
#interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
interrupt-controller;
#interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
interrupt-controller;
#interrupt-cells = <2>;
};
i2c1_pins_a: i2c1@0 {
pins {
pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
usart1_pins: usart1@0 {
pins1 {
pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
bias-disable;
};
};
usart2_pins: usart2@0 {
pins1 {
pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
};
fmc_pins: fmc@0 {
pins {
pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
<STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
<STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
<STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
<STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
<STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
<STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
<STM32H7_PE0_FUNC_FMC_NBL0>,
<STM32H7_PE1_FUNC_FMC_NBL1>,
<STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
<STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
<STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
<STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
<STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
<STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
<STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
<STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
<STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
<STM32H7_PF0_FUNC_FMC_A0>,
<STM32H7_PF1_FUNC_FMC_A1>,
<STM32H7_PF2_FUNC_FMC_A2>,
<STM32H7_PF3_FUNC_FMC_A3>,
<STM32H7_PF4_FUNC_FMC_A4>,
<STM32H7_PF5_FUNC_FMC_A5>,
<STM32H7_PF11_FUNC_FMC_SDNRAS>,
<STM32H7_PF12_FUNC_FMC_A6>,
<STM32H7_PF13_FUNC_FMC_A7>,
<STM32H7_PF14_FUNC_FMC_A8>,
<STM32H7_PF15_FUNC_FMC_A9>,
<STM32H7_PG0_FUNC_FMC_A10>,
<STM32H7_PG1_FUNC_FMC_A11>,
<STM32H7_PG2_FUNC_FMC_A12>,
<STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
<STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
<STM32H7_PG8_FUNC_FMC_SDCLK>,
<STM32H7_PG15_FUNC_FMC_SDNCAS>,
<STM32H7_PH5_FUNC_FMC_SDNWE>,
<STM32H7_PH6_FUNC_FMC_SDNE1>,
<STM32H7_PH7_FUNC_FMC_SDCKE1>,
<STM32H7_PH8_FUNC_FMC_D16>,
<STM32H7_PH9_FUNC_FMC_D17>,
<STM32H7_PH10_FUNC_FMC_D18>,
<STM32H7_PH11_FUNC_FMC_D19>,
<STM32H7_PH12_FUNC_FMC_D20>,
<STM32H7_PH13_FUNC_FMC_D21>,
<STM32H7_PH14_FUNC_FMC_D22>,
<STM32H7_PH15_FUNC_FMC_D23>,
<STM32H7_PI0_FUNC_FMC_D24>,
<STM32H7_PI1_FUNC_FMC_D25>,
<STM32H7_PI2_FUNC_FMC_D26>,
<STM32H7_PI3_FUNC_FMC_D27>,
<STM32H7_PI4_FUNC_FMC_NBL2>,
<STM32H7_PI5_FUNC_FMC_NBL3>,
<STM32H7_PI6_FUNC_FMC_D28>,
<STM32H7_PI7_FUNC_FMC_D29>,
<STM32H7_PI9_FUNC_FMC_D30>,
<STM32H7_PI10_FUNC_FMC_D31>;
slew-rate = <3>;
};
};
sdmmc1_pins: sdmmc@0 {
usbotg_hs_pins_a: usbotg-hs@0 {
pins {
pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
<STM32H7_PC9_FUNC_SDMMC1_D1>,
<STM32H7_PC10_FUNC_SDMMC1_D2>,
<STM32H7_PC11_FUNC_SDMMC1_D3>,
<STM32H7_PC12_FUNC_SDMMC1_CK>,
<STM32H7_PD2_FUNC_SDMMC1_CMD>;
slew-rate = <3>;
drive-push-pull;
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
<STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
<STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
<STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
<STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
<STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
<STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
<STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
<STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
<STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
<STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
bias-disable;
};
};
pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
pins {
pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
<STM32H7_PB9_FUNC_SDMMC1_CDIR>,
<STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
<STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
drive-push-pull;
slew-rate = <3>;
slew-rate = <2>;
};
};
};

484
arch/arm/dts/stm32h743.dtsi
View file

@ -44,13 +44,14 @@
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
#include <dt-bindings/mfd/stm32h7-rcc.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-frequency = <0>;
};
clk_lse: clk-lse {
@ -67,31 +68,6 @@
};
soc {
rcc: rcc@58024400 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
reg = <0x58024400 0x400>;
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;
st,syscfg = <&pwrcfg>;
};
usart1: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
clocks = <&rcc USART1_CK>;
};
usart2: serial@40004400 {
compatible = "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
clocks = <&rcc USART2_CK>;
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
@ -99,39 +75,441 @@
clocks = <&rcc TIM5_CK>;
};
lptimer1: timer@40002400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40002400 0x400>;
clocks = <&rcc LPTIM1_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@0 {
compatible = "st,stm32-lptimer-trigger";
reg = <0>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
};
spi2: spi@40003800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x40003800 0x400>;
interrupts = <36>;
clocks = <&rcc SPI2_CK>;
status = "disabled";
};
spi3: spi@40003c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x40003c00 0x400>;
interrupts = <51>;
clocks = <&rcc SPI3_CK>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
clocks = <&rcc USART2_CK>;
};
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
interrupts = <31>,
<32>;
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
clocks = <&rcc I2C1_CK>;
status = "disabled";
};
i2c2: i2c@40005800 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
interrupts = <33>,
<34>;
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
clocks = <&rcc I2C2_CK>;
status = "disabled";
};
i2c3: i2c@40005C00 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005C00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
clocks = <&rcc I2C3_CK>;
status = "disabled";
};
dac: dac@40007400 {
compatible = "st,stm32h7-dac-core";
reg = <0x40007400 0x400>;
clocks = <&rcc DAC12_CK>;
clock-names = "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
dac1: dac@1 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
reg = <2>;
status = "disabled";
};
};
usart1: serial@40011000 {
compatible = "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
clocks = <&rcc USART1_CK>;
};
spi1: spi@40013000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x40013000 0x400>;
interrupts = <35>;
clocks = <&rcc SPI1_CK>;
status = "disabled";
};
spi4: spi@40013400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x40013400 0x400>;
interrupts = <84>;
clocks = <&rcc SPI4_CK>;
status = "disabled";
};
spi5: spi@40015000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x40015000 0x400>;
interrupts = <85>;
clocks = <&rcc SPI5_CK>;
status = "disabled";
};
dma1: dma@40020000 {
compatible = "st,stm32-dma";
reg = <0x40020000 0x400>;
interrupts = <11>,
<12>,
<13>,
<14>,
<15>,
<16>,
<17>,
<47>;
clocks = <&rcc DMA1_CK>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
status = "disabled";
};
dma2: dma@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
interrupts = <56>,
<57>,
<58>,
<59>,
<60>,
<68>,
<69>,
<70>;
clocks = <&rcc DMA2_CK>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
status = "disabled";
};
dmamux1: dma-router@40020800 {
compatible = "st,stm32h7-dmamux";
reg = <0x40020800 0x1c>;
#dma-cells = <3>;
dma-channels = <16>;
dma-requests = <128>;
dma-masters = <&dma1 &dma2>;
clocks = <&rcc DMA1_CK>;
};
adc_12: adc@40022000 {
compatible = "st,stm32h7-adc-core";
reg = <0x40022000 0x400>;
interrupts = <18>;
clocks = <&rcc ADC12_CK>;
clock-names = "bus";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
adc1: adc@0 {
compatible = "st,stm32h7-adc";
#io-channel-cells = <1>;
reg = <0x0>;
interrupt-parent = <&adc_12>;
interrupts = <0>;
status = "disabled";
};
adc2: adc@100 {
compatible = "st,stm32h7-adc";
#io-channel-cells = <1>;
reg = <0x100>;
interrupt-parent = <&adc_12>;
interrupts = <1>;
status = "disabled";
};
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32f7-hsotg";
reg = <0x40040000 0x40000>;
interrupts = <77>;
clocks = <&rcc USB1OTG_CK>;
clock-names = "otg";
g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
status = "disabled";
};
usbotg_fs: usb@40080000 {
compatible = "st,stm32f4x9-fsotg";
reg = <0x40080000 0x40000>;
interrupts = <101>;
clocks = <&rcc USB2OTG_CK>;
clock-names = "otg";
status = "disabled";
};
mdma1: dma@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
interrupts = <122>;
clocks = <&rcc MDMA_CK>;
#dma-cells = <5>;
dma-channels = <16>;
dma-requests = <32>;
};
exti: interrupt-controller@58000000 {
compatible = "st,stm32h7-exti";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x58000000 0x400>;
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
};
syscfg: system-config@58000400 {
compatible = "syscon";
reg = <0x58000400 0x400>;
};
spi6: spi@58001400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x58001400 0x400>;
interrupts = <86>;
clocks = <&rcc SPI6_CK>;
status = "disabled";
};
i2c4: i2c@58001C00 {
compatible = "st,stm32f7-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58001C00 0x400>;
interrupts = <95>,
<96>;
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
clocks = <&rcc I2C4_CK>;
status = "disabled";
};
lptimer2: timer@58002400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002400 0x400>;
clocks = <&rcc LPTIM2_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@1 {
compatible = "st,stm32-lptimer-trigger";
reg = <1>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
};
lptimer3: timer@58002800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002800 0x400>;
clocks = <&rcc LPTIM3_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@2 {
compatible = "st,stm32-lptimer-trigger";
reg = <2>;
status = "disabled";
};
};
lptimer4: timer@58002c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
};
lptimer5: timer@58003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
};
vrefbuf: regulator@58003c00 {
compatible = "st,stm32-vrefbuf";
reg = <0x58003C00 0x8>;
clocks = <&rcc VREF_CK>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2500000>;
status = "disabled";
};
rtc: rtc@58004000 {
compatible = "st,stm32h7-rtc";
reg = <0x58004000 0x400>;
clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
clock-names = "pclk", "rtc_ck";
assigned-clocks = <&rcc RTC_CK>;
assigned-clock-parents = <&rcc LSE_CK>;
interrupt-parent = <&exti>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
rcc: reset-clock-controller@58024400 {
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
reg = <0x58024400 0x400>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
st,syscfg = <&pwrcfg>;
};
pwrcfg: power-config@58024800 {
compatible = "syscon";
reg = <0x58024800 0x400>;
};
fmc: fmc@52004000 {
compatible = "st,stm32h7-fmc";
reg = <0x52004000 0x1000>;
clocks = <&rcc FMC_CK>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_csi: clk-csi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
sdmmc1: sdmmc@52007000 {
compatible = "st,stm32-sdmmc2";
reg = <0x52007000 0x1000>;
interrupts = <49>;
clocks = <&rcc SDMMC1_CK>;
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
adc_3: adc@58026000 {
compatible = "st,stm32h7-adc-core";
reg = <0x58026000 0x400>;
interrupts = <127>;
clocks = <&rcc ADC3_CK>;
clock-names = "bus";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
adc3: adc@0 {
compatible = "st,stm32h7-adc";
#io-channel-cells = <1>;
reg = <0x0>;
interrupt-parent = <&adc_3>;
interrupts = <0>;
status = "disabled";
};
};
};
};

11
arch/arm/dts/stm32h743i-disco-u-boot.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32h7-u-boot.dtsi>
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_pins>;
pinctrl-names = "default";
bus-width = <4>;
cd-gpios = <&gpioi 8 1>;
};

44
arch/arm/dts/stm32h743i-disco.dts
View file

@ -43,7 +43,6 @@
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h743-pinctrl.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
/ {
model = "STMicroelectronics STM32H743i-Discovery board";
@ -60,50 +59,15 @@
aliases {
serial0 = &usart2;
mmc0 = &sdmmc1;
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
};
};
&clk_hse {
clock-frequency = <25000000>;
};
&usart2 {
pinctrl-0 = <&usart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&fmc {
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI
* firsct bank is bank@0
* second bank is bank@1
*/
bank1: bank@1 {
st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
TWR_1 TRCD_1>;
st,sdram-refcount = <1539>;
};
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_pins>;
pinctrl-names = "default";
bus-width = <4>;
cd-gpios = <&gpioi 8 1>;
};

12
arch/arm/dts/stm32h743i-eval-u-boot.dtsi Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
#include <stm32h7-u-boot.dtsi>
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_pins>,
<&pinctrl_sdmmc1_level_shifter>;
pinctrl-names = "default";
bus-width = <4>;
st,sig-dir;
};

83
arch/arm/dts/stm32h743i-eval.dts
View file

@ -43,7 +43,6 @@
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h743-pinctrl.dtsi"
#include <dt-bindings/memory/stm32-sdram.h>
/ {
model = "STMicroelectronics STM32H743i-EVAL board";
@ -60,18 +59,49 @@
aliases {
serial0 = &usart1;
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
};
vdda: regulator-vdda {
compatible = "regulator-fixed";
regulator-name = "vdda";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc USB1ULPI_CK>;
clock-names = "main_clk";
};
};
&adc_12 {
vref-supply = <&vdda>;
status = "okay";
adc1: adc@0 {
/* potentiometer */
st,adc-channels = <0>;
status = "okay";
};
};
&clk_hse {
clock-frequency = <25000000>;
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&rtc {
status = "okay";
};
&usart1 {
@ -80,30 +110,11 @@
status = "okay";
};
&fmc {
pinctrl-0 = <&fmc_pins>;
&usbotg_hs {
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
dr_mode = "otg";
status = "okay";
/*
* Memory configuration from sdram datasheet IS42S32800G-6BLI
* firsct bank is bank@0
* second bank is bank@1
*/
bank2: bank@1 {
st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
TWR_1 TRCD_1>;
st,sdram-refcount = <1539>;
};
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_pins>,
<&pinctrl_sdmmc1_level_shifter>;
pinctrl-names = "default";
bus-width = <4>;
st,dirpol;
};

10
arch/arm/dts/stm32mp157c-ed1.dts
View file

@ -342,9 +342,9 @@
&sdmmc1 {
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
broken-cd;
st,dirpol;
st,negedge;
st,pin-ckin;
st,sig-dir;
st,neg-edge;
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
@ -361,8 +361,8 @@
non-removable;
no-sd;
no-sdio;
st,dirpol;
st,negedge;
st,sig-dir;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd>;

23
board/st/stm32f746-disco/stm32f746-disco.c
View file

@ -7,6 +7,8 @@
#include <common.h>
#include <dm.h>
#include <lcd.h>
#include <miiphy.h>
#include <phy_interface.h>
#include <ram.h>
#include <spl.h>
#include <splash.h>
@ -123,8 +125,25 @@ int board_init(void)
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
#ifdef CONFIG_ETH_DESIGNWARE
/* Set >RMII mode */
STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
const char *phy_mode;
int node;
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,stm32-dwmac");
if (node < 0)
return -1;
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
switch (phy_get_interface_by_name(phy_mode)) {
case PHY_INTERFACE_MODE_RMII:
STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
break;
case PHY_INTERFACE_MODE_MII:
STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL;
break;
default:
printf("PHY interface %s not supported !\n", phy_mode);
}
#endif
#if defined(CONFIG_CMD_BMP)

14
configs/stm32f746-disco_defconfig
View file

@ -4,39 +4,32 @@ CONFIG_SYS_TEXT_BASE=0x08008000
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
@ -49,6 +42,7 @@ CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y

14
drivers/mmc/arm_pl180_mmci.c
View file

@ -422,6 +422,7 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
struct mmc_config *cfg = &pdata->cfg;
struct clk clk;
u32 bus_width;
u32 periphid;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
@ -439,7 +440,15 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
SDI_CLKCR_HWFC_EN;
host->clock_in = clk_get_rate(&clk);
host->version2 = dev_get_driver_data(dev);
periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
switch (periphid) {
case STM32_MMCI_ID: /* stm32 variant */
host->version2 = false;
break;
default:
host->version2 = true;
}
cfg->name = dev->name;
cfg->voltages = VOLTAGE_WINDOW_SD;
@ -526,7 +535,8 @@ static int arm_pl180_mmc_ofdata_to_platdata(struct udevice *dev)
}
static const struct udevice_id arm_pl180_mmc_match[] = {
{ .compatible = "st,stm32f4xx-sdio", .data = VERSION1 },
{ .compatible = "arm,pl180" },
{ .compatible = "arm,primecell" },
{ /* sentinel */ }
};

3
drivers/mmc/arm_pl180_mmci.h
View file

@ -141,8 +141,7 @@
#define SDI_FIFO_BURST_SIZE 8
#define VERSION1 false
#define VERSION2 true
#define STM32_MMCI_ID 0x00880180
struct sdi_registers {
u32 power; /* 0x00*/

67
drivers/mmc/stm32_sdmmc2.c
View file

@ -190,6 +190,7 @@ struct stm32_sdmmc2_ctx {
#define SDMMC_IDMACTRL_IDMAEN BIT(0)
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
#define SDMMC_BUSYD0END_TIMEOUT_US 1000000
static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
struct mmc_data *data,
@ -209,9 +210,6 @@ static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
idmabase0 = (u32)data->src;
}
/* Set the SDMMC Data TimeOut value */
writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER);
/* Set the SDMMC DataLength value */
writel(ctx->data_length, priv->base + SDMMC_DLEN);
@ -236,8 +234,11 @@ static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
}
static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
struct mmc_cmd *cmd, u32 cmd_param)
struct mmc_cmd *cmd, u32 cmd_param,
struct stm32_sdmmc2_ctx *ctx)
{
u32 timeout = 0;
if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
writel(0, priv->base + SDMMC_CMD);
@ -251,6 +252,26 @@ static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
cmd_param |= SDMMC_CMD_WAITRESP_1;
}
/*
* SDMMC_DTIME must be set in two case:
* - on data transfert.
* - on busy request.
* If not done or too short, the dtimeout flag occurs and DPSM stays
* enabled/busy and waits for abort (stop transmission cmd).
* Next data command is not possible whereas DPSM is activated.
*/
if (ctx->data_length) {
timeout = SDMMC_CMD_TIMEOUT;
} else {
writel(0, priv->base + SDMMC_DCTRL);
if (cmd->resp_type & MMC_RSP_BUSY)
timeout = SDMMC_CMD_TIMEOUT;
}
/* Set the SDMMC Data TimeOut value */
writel(timeout, priv->base + SDMMC_DTIMER);
/* Clear flags */
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
@ -309,6 +330,31 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
cmd->response[2] = readl(priv->base + SDMMC_RESP3);
cmd->response[3] = readl(priv->base + SDMMC_RESP4);
}
/* Wait for BUSYD0END flag if busy status is detected */
if (cmd->resp_type & MMC_RSP_BUSY &&
status & SDMMC_STA_BUSYD0) {
mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
/* Polling status register */
ret = readl_poll_timeout(priv->base + SDMMC_STA,
status, status & mask,
SDMMC_BUSYD0END_TIMEOUT_US);
if (ret < 0) {
debug("%s: timeout reading SDMMC_STA\n",
__func__);
ctx->dpsm_abort = true;
return ret;
}
if (status & SDMMC_STA_DTIMEOUT) {
debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
__func__, status);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
}
}
return 0;
@ -395,7 +441,7 @@ retry_cmd:
stm32_sdmmc2_start_data(priv, data, &ctx);
}
stm32_sdmmc2_start_cmd(priv, cmd, cmdat);
stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
__func__, cmd->cmdidx,
@ -425,7 +471,10 @@ retry_cmd:
debug("%s: send STOP command to abort dpsm treatments\n",
__func__);
stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP);
ctx.data_length = 0;
stm32_sdmmc2_start_cmd(priv, &stop_cmd,
SDMMC_CMD_CMDSTOP, &ctx);
stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
@ -585,11 +634,11 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
if (dev_read_bool(dev, "st,negedge"))
if (dev_read_bool(dev, "st,neg-edge"))
priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
if (dev_read_bool(dev, "st,dirpol"))
if (dev_read_bool(dev, "st,sig-dir"))
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
if (dev_read_bool(dev, "st,pin-ckin"))
if (dev_read_bool(dev, "st,use-ckin"))
priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
ret = clk_get_by_index(dev, 0, &priv->clk);

1
drivers/pinctrl/pinctrl_stm32.c
View file

@ -421,6 +421,7 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
{ .compatible = "st,stm32f429-pinctrl" },
{ .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32f769-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
{ .compatible = "st,stm32mp157-pinctrl" },
{ .compatible = "st,stm32mp157-z-pinctrl" },

20
include/configs/stm32f746-disco.h
View file

@ -43,14 +43,20 @@
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_BOOTCOMMAND \
"run bootcmd_romfs"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
"bootm 0x08044000 - 0x08042000\0"
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xC0008000\0" \
"fdtfile=stm32f746-disco.dtb\0" \
"fdt_addr_r=0xC0500000\0" \
"scriptaddr=0xC0008000\0" \
"pxefile_addr_r=0xC0008000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"ramdisk_addr_r=0xD0900000\0" \
BOOTENV
/*
* Command line configuration.

7
include/dt-bindings/clock/stm32fx-clock.h
View file

@ -33,11 +33,12 @@
#define CLK_SAI2 11
#define CLK_I2SQ_PDIV 12
#define CLK_SAIQ_PDIV 13
#define END_PRIMARY_CLK 14
#define CLK_HSI 14
#define CLK_SYSCLK 15
#define CLK_F469_DSI 16
#define END_PRIMARY_CLK 17
#define CLK_HDMI_CEC 16
#define CLK_SPDIF 17
#define CLK_USART1 18

1341
include/dt-bindings/pinctrl/stm32f746-pinfunc.h
View file

File diff suppressed because it is too large Load diff

1612
include/dt-bindings/pinctrl/stm32h7-pinfunc.h
View file

File diff suppressed because it is too large Load diff