Remove unneeded headers, function prototype and stale comment, that
doesn't match the actual codebase anymore.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no need to init a USB controller before the upper layers indicate
that they are actually going to use it.
board_usb_init now only parses the device tree and sets up the common pll.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Just a dead parameter, never actually used.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no need to pass around all those parameters. The init functions
are able to easily extract all the needed setup info on their own.
This allows to move out the controller init into ehci_hcd_init later
on, without having to save away global state for later use and thus
bloating the file global state.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Both Tegra20 and Tegra30 have a max of 3 USB controllers.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.
This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.
Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.
Conflicts:
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/vpac270/u-boot-spl.lds
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Turn __bss_start and __bss_end__ from linker-generated
to compiler-generated symbols, causing relocations for
these symbols to change type, from R_ARM_ABS32 to
R_ARM_RELATIVE.
This should have no functional impact, as it affects
references to __bss_start and __bss_end__ only before
relocation, and no such references are done.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.
This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.
Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.
This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
As the CPU name is not configurable, using CPU string directly
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This adds hardware tripping at 110 degrees celsius which must enable
forced system shutdown in case TMU fails to power off.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
Adding CPU detection support for the DRA752 ES1.0 soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.
While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x
Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.
This avoids unnessecary code addition for future socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.
This helps in addition of a new Soc with minimal
changes.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.
Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence. In our current (incorrect)
sequence some edge cases may fail to initalize correctly.
Signed-off-by: Tom Rini <trini@ti.com>
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.
Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.
Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to
enable the 'Fast Auto Pre-Charge' found in the memory chip. The
setting is applied after memory initialization and it is worth
document it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.
First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.
Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.
Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.
Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The real reason for memory instability was the fact that the EMI block
was gated and not reset throughout the boards' operation. This patch
resets the EMI block properly while also reverts the memory voltage bump.
The memory stability issues were caused by the EMI not being reset properly
and thus there is no longer need to run the memory at higher voltage than
it ought to run at.
This partly reverts 8303ed128a .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This pulls the three following ZYNQ commits into ARM master:
7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f4: arm: zynq: Add SLCR support with system reset
00ed3458: arm: zynq: Add lowlevel initialization to C
The issue got introduced in a cleanup by Manjunath Hadli in commit
826e99136e. The eth_getenv_enetaddr_by_index
method will validate the MAC addr and if none is set in the environment
0 will be returned. Set the MAC from the eeprom if no valid address
is found in environment.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition goes away(e.g. power button).
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
When calling 'make u-boot.imx' the build were failing as it were
expecting the full path for the file; this regression has been
included by commit 71a988a (imximage.cfg: run files through C
preprocessor).
The direct references for u-boot.imx were replaced by $(obj) as
config.mk handles the proper setting of it making it set to $(OBJTREE)
when required.
The build has been test using:
- ./MAKEALL -s mx5 -s mx6
- make u-boot.imx
- make O=/tmp/build
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.
Comparing the watchdog behaviour on a revB versus revC board:
- On a mx6qsabresd revB:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...
- On a mx6qsabresd revC:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR
So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.
Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
SBC1 is SPI controller 1 on tegra30
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c
Some T30 tables needed whitespace fixes due to checkpatch complaints.
Signed-off-by: Tom Warren <twarren@nvidia.com>
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Using the __weak annotation can make the code cleaner.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
The memory power supply on MX23 didn't pump out enough juice into
the DRAM chip, thus caused occasional memory corruption. Fix this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.
The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile
.gitignore was updated to ignore .cfgtmp files.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The memory init is slightly different on MX23, thus split the memory
init for mx23 and mx28 into different functions.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The power block on MX23 must first be ungated before it can be operated.
Add function to MXS power init that ungates it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
For i.MX23 we need to pass imx23 as elftosb param.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This adds the boot mode support for i.MX23 processors.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add information to identify i.MX23 chips and its known revisions.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this
synonym and replace with UARTB to disambiguate.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch adds basic Tegra30 (T30) build support - no specific
board is targeted.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidai.com>
This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.
Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
When u-boot is compiled for PXA25x processor, pxa/start.S is calling
cpu_init_crit by BL instruction. BL is overwriting lr register so
relocate_code is going into infinite loop. This patch preservs lr
register in r12 before calling cpu_init_crit and after function returns
restores it.
Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Mobile storage is used the CLK_DIV_FSYS3 value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
To get exactly clock value for mmc, support the get_mmc_clk() like
set_mmc_clk().
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add workaround for the following ARM errata: 743622 and 751472.
The motivation for this change is the following kernel commit 62e4d357a
(ARM: 7609/1: disable errata work-arounds which access
secure registers), which removes the errata from multiplatform kernel.
Since imx has been converted to multiplatform in the kernel, we need to apply
such workarounds into the bootloader.
Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel.
Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad"
document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Move all the C runtime setup code from every start.S
in arch/arm into arch/arm/lib/crt0.S. This covers
the code sequence from setting up the initial stack
to calling into board_init_r().
Also, rewrite the C runtime setup and make functions
board_init_*() and relocate_code() behave according to
normal C semantics (no jumping across the C stack any
more, etc).
Some SPL targets had to be touched because they use
start.S explicitly or for some reason; the relevant
maintainers and custodians are cc:ed.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Api is added to decode peripheral id based on the interrupt number
of the peripheral.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch add pinmux settings for Exynos4 for mmc0 and mmc2
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adds functions to extract clock frequency of Exynos4x12 IPs.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes.
This patch add pinmux for I2C for Exynos4
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
This patch adds i2c clock for Exynos4
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.
The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
The reset procedure works on watchdog timer while before it was modifying
TIMER_1 registers.
Tested on DM365.
Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
DMM_LISA_MAP registers program whether memory is mapped
on particular EMIF or not. Irrespective of these registers
EMIF is getting configured. Correcting the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Git commit d417d1db5f replaced the
omap-common file reset.S with reset.c, but the Makefile was not
adjusted for that.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
No functional changes, just more comments for readability when a
preprocessor check spans more than a few lines, and for consistency.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings. This saves about
90 bytes of space in SPL.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.
Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Include asm/arch/sys_proto.h for gpmc_init prototype.
Without this we get a warning while building for AM335x.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
These GPMC_CS defines are a leftover from prior gpmc_init(). Commit 187af954
removed the need for these definitions but missed to remove them.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Conflicts:
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/woodburn_common.h
board/woodburn/woodburn.c
These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.
Fix all conflicts and update woodburn to use Power Framework.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Use a generic 'dram_vals[]' array that has the full initialization
sequence and rename the initialization method so it doesn't has a
frequency on its name.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The MXS SPL didn't mark local functions "static". Fix it. This also makes the
SPL smaller by roughly 300 bytes.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
The memory setup code adjusted the VDDD voltage. Remove this adjustment
and configure the VDDD voltage correctly in the power supply setup code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Implement common function to setup the VDDIO, VDDD and VDDA voltage.
Right now, there are two almost identical functions to setup VDDIO
and VDDD, which is prone to breakage. Pull out the differences into
constant structure and pass them as an argument to the common function.
Moreover, the function has almost identical loops for setting higher
and lower VDDx voltage. Merge these two loops.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Add support for adjusting the L1 cache behavior by updating the MMU
configuration. The mmu_set_region_dcache_behaviour() function allows
drivers to make these changes after the MMU is set up.
It is implemented only for ARMv7 at present.
This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Mayuresh Kulkarni:
- changes to remove bitfields and clean up for submission
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass:
- simplify code, move clock control into here, clean-up
Signed-off-by: Tom Warren <twarren@nvidia.com>
The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These two functions don't actually modify their arguments so add a const
keyword.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.
Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Add api to calculate and set the clock for SPI channels
Signed-off-by: James Miller <jamesmiller@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds pinmux support for SPI channels
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds clock support for I2S
Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds pinmux support for I2S1
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch_cpu_init() is removed from cpu level to SOC level for arm1176
in commit 4ea6d6b,the same is done for s3c64xx
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Moved the common code to calculate pll clock rate to new function
exynos_get_pll_clk().
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
This patch add pinmux settings for Exynos4 for mmc0 and mmc2
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
enable_caches() did not enable icache if CONFIG_SYS_ICACHE_OFF was not defined
but CONFIG_SYS_DCACHE_OFF was.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Previously, the same value was returned for both mx6dl and mx6solo.
Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev
stored at 0x280 instead of 0x260.
I don't have a sololite to verify.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
Timer is initialized already in board_init_r function in
(common/spl/spl.c) No need to initialize it again
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings
currently. Re-order functions so that we don't have that anymore.
Signed-off-by: Tom Rini <trini@ti.com>
Add back common.h header that was removed in previous patch so that
CONFIG_TEGRA can be evaluated correctly.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Initialize this variable to avoid a compiler warning about possible
use of uninitialized variable with gcc 4.4.6.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change tegra SPL to use common SPL framework. Any tegra specific
initialization is now done in spl_board_init() instead of
board_init_f()/board_init_r(). Only one SPL boot target is supported
on tegra, which is boot to RAM image. jump_to_image_no_args() must be
overridden on tegra so the host CPU can be initialized.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add an ASSERT() to u-boot.lds to detect an SPL that doesn't fit within
SPL_TEXT_BASE..SPL_MAX_SIZE.
Different .lds files implement this check in two possible ways:
1) An ASSERT() like this
2) Defining a MEMORY region of size SPL_MAX_SIZE, and re-directing all
linker output into that region. Since u-boot.lds is used for both
SPL and main U-Boot, this would entail only sometimes defining a
MEMORY region, and only sometimes performing that redirection, and
hence option (1) was deemed much simpler, and hence implemented.
Note that this causes build failures at least for NVIDIA Tegra Seaboard
and Ventana. However, these are legitimate; the SPL doesn't fit within
the required space, and this does cause runtime issues.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When -ffunction-sections or -fdata-section are used, symbols are placed
into sections such as .data.eserial1_device and .bss.serial_current.
Update the linker script to explicitly include these. Without this
change (at least with my gcc-4.5.3 built using crosstool-ng), I see that
the sections do end up being included, but __bss_end__ gets set to the
same value as __bss_start.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The woodburn board is based on the MX35 SOC.
Support for both external (NOR) and internal
(SD Card) boot mode are added. It uses the
generic SPL framework to implement the internal boot
mode.
The following peripherals are supported:
- Ethernet (FEC)
- SD Card
- NAND (512 MB)
- NOR Flash
In the internal boot mode, a simple imximage header
is generated to set the address in internal RAM
where the SOC must copy the SPL code. The initial setup
is then demanded to the SPL itself.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The patch adds SPL for the arm1136 architecture and
inserts SPL (the produced binary) to clobber target
in the main Makefile.
Signed-off-by: Stefano Babic <sbabic@denx.de>
This patch modifies start.S for the arm1136 to make it
conform to start.S in armv7 architecture, to make it
usable if the SPL framework is used.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Patch fix warnings compiling with ELDK-4.2:
clock.c: In function 'get_standard_pll_sel_clk':
clock.c:341: warning: 'freq' may be used uninitialized in this function
Reported-by : Marek Vasut <marex@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232
cape or the am335x_evm daughterboard, enable the required clocks for
the UART in use.
Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make re-apply with rtc32k_enable() applied]
Signed-off-by: Tom Rini <trini@ti.com>
Add the required config.mk logic for this SoC as well as the BOOT_DEVICE
define. Finally, enable the options on the am335x_evm.
Signed-off-by: Tom Rini <trini@ti.com>
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume. In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain. Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.
So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
DDR3 support is tested and working with beaglebone hardware. Include a check
for this board type and configure DDR3. The timings and other configuration
match EVM SK.
Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Acked-by: Jason Kridner <jdk@ti.com>
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Oliver Brown <obrown@adventnetworks.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Add the software workaround for ARM erratum ID 468414.
According to mx53/mx51 errata document:
"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a
subsequent request
Description:
Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded
to a subsequent, unrelated memory request.
The conditions are as follows:
• Neon loads and stores must be in use
• Neon L1 caching must be disabled
• Trustzone must be configured and in use
• The secure memory address space and the non-secure memory address space both use the same
physical addresses, either as an alias or the same memory location or for separate memory
locations
The issue is reported by ARM, erratum ID 468414, Category 2"
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.
Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.
Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.
Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
init_clock is currently shared between mx51 and mx53 and it contains lots of
ifdef's which makes it really hard to follow the code.
Split the init_clock between mx51 and mx53 to allow easier readability.
No functional changes are made.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Since commit 957731ed (ARM: remove broken "lpd7a40x" boards),
lh7a40x cpu and serial driver have become unused. Remove them.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Each eSDHC instance has a dedicated clock.
gd->sdhc_clk must also be set accordingly. This is good for the case only a
single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A
future patch will fix the multi-instance use case (initialization made directly
with fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Optimize mx5 lowlevel_init.S code size:
- Compute values at compile time rather than at runtime where possible.
- Assign r4 to hold the zero value rather than setting registers to 0 again and
again.
- Associate a function to setup_pll rather than expanding its large macro code
multiple times.
- Allocate constant values in section only if used.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do
with mxcmmc.
Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set
accordingly. This is good for the case only a single SDHC instance is used
(initialization made with fsl_esdhc_mmc_init()). A future patch will fix the
multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
The FEC is the only SoC Ethernet support available on i.MX25, so define
cpu_eth_init() only for it instead of returning a misleading success code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Use the standard mxc_get_clock() instead of exporting internal functions and
using literal constant values.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock.
Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG
clock, so remove the duplicated code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Avoid possible overflow in clock calculations, and do not waste calls to lldiv()
to divide simple ulongs.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.
Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
There are only 2 I²C instances on i.MX51, but 3 on i.MX53.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The FEC clock does not come from PLL1, but from the IPG clock. The previous code
was even inconsistent with itself, returning the IPG clock as expected for
imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The code handling the dividers was duplicated for each possible input clock, and
this function can benefit from the newly introduced get_standard_pll_sel_clk()
function instead of duplicating this mux handling code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This function returned 66500000 instead of the correct lp_apm clock frequency if
the CCM.CSCMR1.uart_clk_sel mux is set to 3.
This patch fixes this issue by introducing the get_standard_pll_sel_clk()
function that will be used by future patches to handle identical muxes used by
many other clocks.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue
was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case
CCM.CBCMR.perclk_lp_apm_sel is set.
It also fixes I²C support.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
- on i.MX51, this clock comes from the output of the FPM,
- on i.MX53, this clock comes from the output of PLL4.
This patch fixes the code accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.
The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Clean up the i.MX5 clock driver:
- Use readl() and writel() instead of their __raw_ counterparts.
- Use the clr/setbits_le32() family of macros rather than expanding code.
- Use accessor macros for bit-fields instead of _MASK and _OFFSET.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Stefano Babic <sbabic@denx.de>
tested on a MCIMX257CJM4A which now reports :
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.
Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:
http://patchwork.ozlabs.org/patch/185129/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The prototypes used in board files were all scattered out, which lead to
code duplication between SPL and normal U-Boot and some prototypes not actually
being used. Consolidate this in a common board header.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Secondary config for the Flash attachment.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Rename board provided gpio_config_uart() to
gpio_early_init_uart() as it does the same thing as the equally
called function provided by the uart-switch code. This allows
to simply call this function in early board init whether or not
we are building with CONFIG_UART_SWITCH defined.
Also provide a weak symbol for this function, to avoid the
need to provide this function for boards that don't need any
fixup.
This patch supersedes the earlier posted
"tegra: convert gpio_config_uart to weak symbol".
Build tested with MAKEALL -s tegra20
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.
This function adds a clean way to do so.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Most Tegra boards output the ULPI reference clock on pad DEV2.
Complete the periph_id enum so that we are able to enable this
clock output circuit.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.
All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any
files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs
and modified for that SoC. The 'common' files should need only minor changes.
Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a
follow-on patch.
Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean.
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along the way of
debugging this.
To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Carry an index in the lowlevel usb functions to make specify the
respective usb controller.
Also pass through an controller struct from lowlevel_init to the
creation of the root usb device of this controller.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Remove the empty bodies from serial_* functions from MXS SPL code.
These empty implementations are now in common/serial.c instead so
declaring them also in the SPL code would cause a colision once
serial multi is enabled unconditionally.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefano Babic <sbabic@denx.de>
Under option -munaligned-access, gcc can perform local char
or 16-bit array initializations using misaligned native
accesses which will throw a data abort exception. Fix files
where these array initializations were unneeded, and for
files known to contain such initializations, enforce gcc
option -mno-unaligned-access.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Switch to usign call cc-option for -mno-unaligned-access as
Albert had done previously as that's really correct]
Signed-off-by: Tom Rini <trini@ti.com>
The restore sequence in lowlevel_init was in the wrong order,
causing lr to lose its original value and be set equal to ip
instead. Also, its use of the stack clashes with that of
s_init, so move the s_init call after the restore and turn
it into a tail-optimized branch.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
lowlevel_init() of rmobile badly assumed that ip register holds return address.
The commit "63ee53a7 armv7 cpu_init_crit: Simplify code" breaks this assumption.
This patch removes this bad assumption and simplify code.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
This patch aims at ensuring that the 2012.10 release works
out-of-the-box on as many targets as possible, by reinstating
commit 5347560f5427bcdd48a563b62180481606ac8044, which adds
option -mno-unaligned-access to armv7 builds.
This patch will be overriden immediately after release of 2012.10.
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Tom Trini <trini@ti.com>
Cc: Wolfgang Denx <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
----
v8: Remove no_return attribute for reset_cpu
Based on v2012.10-rc2
Add timer driver.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
When the u-boot address of destination equal to __start,
no relocation. relocation offset(r9) = 0.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Tested-by: Stefano Babic <sbabic@denx.de>
We don't need to return to cpu_init_crit after calling lowlevel_init, so
lowlevel_init can directly return to the caller of cpu_init_crit.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Size of the SDRAM chips might differ between any two (otherwise
identical) instances of the same board.
So add a function kw_sdram_size_adjust() which reads out the current
ram size for a given bank, and adjusts the Kirkwood's SDRAM window size
register accordingly.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Some boards might be equipped with different SDRAM configurations.
When that is the case, CPU CS Window Size Register (CS[0]n Size)
should be set to the biggest value through board.cfg file; then its
value can be fixed at runtime according to the detected SDRAM size.
Therefore, implement kw_sdram_bs_set().
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Marek Vasut <marex@denx.de>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Remove the defines and do this with a C-struct.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Marek Vasut <marex@denx.de>
Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
Rmobile common timer driver diverts the same driver as SH architecture.
When it builds at the same place with source, it is no problem, but when
it builds out of source, it cannot build.
This patch revises this problem.
Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Renesas R8A7740 has GPIO based PFC. This privode framework of PFC.
The code included in this base from linux kernel.
Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Renesas R8A7740 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Some rmobile SoC has TMU base timer function. This supports TMU.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
There is rmobile without ICCICR.
ICCICR is initialized only when ICCICR is defined.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
According to SoC document, revision info is separated to integer part and
fracton part.
So I separete rmobile_get_cpu_rev() to rmobile_get_cpu_rev_integer() and
rmobile_get_cpu_rev_fraction().
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CPU info register was read wrongly by mistake. And function rmobile_get_cpu_rev() was not called properly.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Latest rmobile code was tested by using old gcc (gcc-4.4).
When we use gcc-4.6 (or later), the build is made, but does not work.
This solves a problem not to work by add -march=armv5 to compiple option
when we built in gcc-4.6 (or later).
I tested by linaro's compiler version 2012.04-20120426.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Renesas SH73A0 has GPIO based PFC. This privode framework of PFC.
The code included in this base from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds minimum support for R-Mobile. Only minimal support with timer.
This CPU can uses the peripheral of Renesas SuperH.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
U-boot should not ignore getting the bootmode passed on from the bootrom.
With this, U-boot SPL knows it was loaded from MMC1 and use this info to
read full U-boot from MMC1 as well.
Cc: pprakash@ti.com
Cc: trini@ti.com
Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
- Convert the non-relocation part of board_init_f to spl_board_init, turn on CONFIG_SPL_BOARD_INIT in the configs.
- Remove duplicated code.
- Add spl_boot_device() that returns the statically chosen boot device.
Signed-off-by: Tom Rini <trini@ti.com>
We move the spl_nand_load_image function to common/spl. This will allow
for easier integration of SPL-boots-Linux code on other arches.
Signed-off-by: Tom Rini <trini@ti.com>
In SPL (CONFIG_SPL_FRAMEWORK) board_init_f must setup the stack pointer,
clear the BSS and call board_init_r. We mark this as weak as some
platforms may need to perform additional initalization at this point.
We provide a gd that we know will be in a usable location, once the BSS
has been cleared to help with this as well. Finally, we no longer call
relocate_code so remove that from the armv7 version.
Next, both board_init_f and jump_to_image_linux are going to be
inherently arch-specific, so move these versions to arch/arm/lib/spl.c
Signed-off-by: Tom Rini <trini@ti.com>
Add a new flag, CONFIG_SPL_FRAMEWORK to opt into the common/spl SPL
framework, enable on all of the previously using boards. We move the
spl_ymodem.c portion to common/ and spl_mmc.c to drivers/mmc/. We leave
the NAND one in-place as we plan to replace it later in this series.
We use common/spl to avoid linker problems with respect to merging
constant strings in objects. Otherwise all strings in common/ will be
linked in and kept which grows SPL in size too much.
Signed-off-by: Tom Rini <trini@ti.com>
This is an OMAP/related-specific function, move calling it to
spl_board_init() and turn on CONFIG_SPL_BOARD_INIT on the boards that
enabled NAND and didn't enable this already.
Signed-off-by: Tom Rini <trini@ti.com>
- Remove includes we don't need
- Switch some printf statements to puts
- Convert some printf statements to debug, introduce new puts statements
- In most cases saying just "No mkimage signature, assuming
u-boot.bin" or similar is sufficient. This also means the non-DEBUG
case doesn't need printf, in the core of SPL.
- The other case here is that PLAIN_VERSION provided what we wanted
already, so just use it.
Signed-off-by: Tom Rini <trini@ti.com>
Move the default omap/related-centric board_mmc_init to
arch/arm/cpu/armv7/omap-common/boot-common.c and move the type defines
to <asm/spl.h>. Also use mmc->read_bl_len rather than MMCSD_SECTOR_SIZE
Signed-off-by: Tom Rini <trini@ti.com>
Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and
add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK.
Signed-off-by: Tom Rini <trini@ti.com>
We can only attempt to setup a malloc pool if
CONFIG_SYS_SPL_MALLOC_START is defined, and not all boards require it.
Make the call depend on the define.
Signed-off-by: Tom Rini <trini@ti.com>
Only omap4/5 currently have a meaningful set of display text and overo
had been adding a function to display nothing. Change how this works to
be opt-in and only turned on for omap4/5 now.
Signed-off-by: Tom Rini <trini@ti.com>
Commit 86c6326 "ARM: arm1176: enable instruction cache in
arch_cpu_init()" defined arch_cpu_init() in a file that is shared across
all arm1176 SoCs. tnetv107x already implemented this function, which
caused linking to break. Move the new conflicting arch_cpu_init() into
arm1176/bcm2835/init.c so that it doesn't conflict; grep indicates this
function is usually defined at the SoC-level, not the CPU-level, at least
for ARM.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.
Upcoming Tegra30 port will use common code/defines/names where possible.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This allows for two things:
- VBus GPIO may be used on other ports than the OTG one
- VBus GPIO may be low active if specified by DT
Signed-off-by: Lucas Stach <dev@lynxeye.de>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <TWarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Up now only MX5 and MX6 can share code, because they have
a common source directory in cpu/armv7. Other not armv7
i.MX can profit of the same shared code. Move these files
into a directory accessible for all, similar to plat-mxc
in linux.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Add selection of NAND flash pins to the funcmux.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Define default SoC input clock frequencies for i.MX31 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Helmut Raiger <helmut.raiger@hale.at>
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Define default SoC input clock frequencies for i.MX35 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that
has been configuring and enabling the timer, so remove our code that
does the same thing by different methods.
Tested on EVM GP, SK-EVM and Beaglebone.
Signed-off-by: Tom Rini <trini@ti.com>
Use proper struct-based access for this register in the SPL code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Orion5x did not actually write GPIO output values
or input polarities, and ED Mini V2 had bad or
missing values for GPIO settings.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
For representing a timeout value, it makes more sense to pass it as
'unsigned int'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The DRAM initialization, after SPL has complete, is exactly the same
for all mxs SoCs so we should name it accordinly.
The following boards has been changed:
* apx4devkit
* m28evk
* mx28evk
* sc_sps_1
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
The internal Ethernet controller is only available on i.MX28
processors so it needs to use CONFIG_MX28 guardian to avoid having
this code called in others.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
The elftosb call needs to use a target param specific for i.MX28. This
patch allow for later addition of i.MX233.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Do not pretend to have initialized mmc successfully if CONFIG_FSL_ESDHC is not
defined. Instead, only implement a custom cpu_mmc_init() when it does something.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.
Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Note: MX53 support untested.
Acked-by: Stefano Babic <sbabic@denx.de>
Round up tick_to_time() value instead of truncating it. This avoids stopping
waits instantly for low usec values, and this generally guarantees that the code
always waits for at least the requested duration.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Now that the main i.MX features work fine with dcache enabled, enabled it by
default if CONFIG_SYS_DCACHE_OFF is not defined.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Now that the main i.MX features work fine with dcache enabled, enabled it by
default if CONFIG_SYS_DCACHE_OFF is not defined.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Move some function calls to a more appropriate place, so they're
called only when needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The SPL doesn't need the CP15 reconfiguration, as that's what the
BootROM does for us already. Moreover, when the CP15 is reconfigured
and the code returns control to BootROM, the USB boot works no more.
Remove the code and allow [1] to work properly as well.
[1] http://git.bfuser.eu/?p=marex/mxsldr.git;a=summary
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The iomux header is included on sys_proto.h so to avoid SoC specific
header inclusion.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
This patch enables the L1 data cache for systems based on Samsung
Exynos processor.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch support display port phy control function.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch supports display block system regisger control.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch support exynos5 lcd clock control.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Removed [-Wuninitialized] warning message.
The fout_sel is assigned to "-1" by default.
And start, gpio_func is initialized to 0.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In general, The get_timer_masked function get the system time,
no the number of ticks. Such as the nand_wait_ready will use
get_timer_masked to delay the operations. And change the system
time to adopt to the CONFIG_SYS_HZ.
Signed-off-by: Hongbo Zhong <bocui107@gmail.com>
Tested-by: Jaehoon Chung<jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for BPLL clock.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
This patch removes save_boot_params_default() and put the equivalent in start.S
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move warmboot_save_sdram_params() to later in the boot sequence. This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it. In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This SoC is used in the Raspberry Pi, for example.
For more details, see:
http://www.broadcom.com/products/BCM2835http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.
Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.
GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.
Cc: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Register mapping has changed on power control chip between
the first and second revision.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Enabling timers and clocks in PRCMU and cleaning up mailbox.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
This is to allow the prcmu functions to be used by multiple
u8500-based processors.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
We can safely use the same reset code written in C for both Davinci and
C6X platforms. In addition the C version of the code is marginally
smaller on Davinci.
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.
During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.
Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.
Move the usb header for da8xx platforms under arch-davinci.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms. As part of this we change some of the macros that are used
to be more clear. Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we
should have been doing this initially and do now.
Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value
Signed-off-by: Tom Rini <trini@ti.com>
This gets us rid of duplication of the same file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable
but this wasn't clear on code so a comment has been added to clarify
it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
In case an unidentified CPU type is detected it now returns
i.MX??, in a const char.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Hadli, Manjunath <manjunath.hadli@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
- Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.
Signed-off-by: Tom Rini <trini@ti.com>
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
config_ddr with.
- Both of the above require filling in the header structure early, move
it into the data section.
Signed-off-by: Tom Rini <trini@ti.com>
The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards. As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.
Signed-off-by: Tom Rini <trini@ti.com>
In order to support DDR3 as well as DDR2, we need to perform the same
init sequence, but with different values. So change config_ddr() to
toggle setting pointers/etc for what DDR2 wants, and then calling.
Signed-off-by: Tom Rini <trini@ti.com>
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini <trini@ti.com>
The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.
Signed-off-by: Tom Rini <trini@ti.com>
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.
Signed-off-by: Tom Rini <trini@ti.com>
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.
Signed-off-by: Tom Rini <trini@ti.com>
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini <trini@ti.com>
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.
Signed-off-by: Tom Rini <trini@ti.com>
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Signed-off-by: Tom Rini <trini@ti.com>
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()). For now, pass in
the value of DDR2.
Signed-off-by: Tom Rini <trini@ti.com>
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const. This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.
Signed-off-by: Tom Rini <trini@ti.com>
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.
Signed-off-by: Tom Rini <trini@ti.com>
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.
Signed-off-by: Tom Rini <trini@ti.com>
We do not need to check for EMIF_GCLK and L3_GCLK being active. This
was a hold-over from bringup and no longer required.
Signed-off-by: Tom Rini <trini@ti.com>
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
This reverts commit 5347560f5427bcdd48a563b62180481606ac8044,
which was applied only to get release 2012.07 functional on as
many ARM targets as possible despite mis-aligned accesses.
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
initialize baudrate, flags, data and serial initialization,
only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
This patch adds support for MMC/SD on DA850/OMAP-L138.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.
It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP
Signed-off-by: Steve Sakoman <steve@sakoman.com>
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
