Commit graph

1255 commits

Author SHA1 Message Date
Bin Meng
8a8c035255 x86: acpi: Various changes to acpi_table.h
- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID.
- Do not typedef acpi_header_t, instead use struct acpi_table_hader.
- Use a shorter name aslc_id and aslc-revision.
- Change MCFG base address to use 32-bit value pairs (_l and _h).
- Apply ACPI_APIC_ prefix to MADT APIC type macros and make
  their names to be more readable.
- Apply __packed to struct acpi_madt_irqoverride and struct
  acpi_madt_lapic_nmi tables, as they are not naturally aligned
  by the compiler which leads to wrong sizeof(struct).
- Rename model to res1 as it is reserved after ACPI spec 1.0.
- Apply ACPI_ prefix to the PM profile macros and change them
  to enum.
- Add ospm_flags to FACS structure which is defined since ACPI 4.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
f4446629c9 x86: acpi: Remove unused codes
- Remove #include <> header files.
- Remove APM_CNT register defines, which should not be here as
  they are SMI related.
- Remove MP_IRQ_ defines as they are duplicates of the same ones
  in asm/mpspec.h.
- Remove ACTL register defines, which should not be here as they
  are chipset specific.
- Remove functional fixed hardware defines, which are not used.
- Remove dev_scope related defines, which are not used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
ce8dd77d99 x86: dts: Update to include ACTL register details
This updates all x86 boards that currently have IRQ router in the
dts files to include ACTL register details.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
d4e61f505b x86: irq: Enable SCI on IRQ9
By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2016-05-23 15:18:00 +08:00
Bin Meng
07ac84eaaa x86: irq: Reserve IRQ9 for ACPI in PIC mode
Reserve IRQ9 which is to be used as SCI interrupt number
for ACPI in PIC mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
dca4d1a2ce x86: acpi: Fix compiler warnings in write_acpi_tables()
Fix the following two build warnings in function 'write_acpi_tables':

  warning: format '%lx' expects argument of type 'long unsigned int',
  but argument 2 has type 'u32' [-Wformat=]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
5cb0f0dc88 x86: Fix build warning in tables.c when CONFIG_SEABIOS
The following build warning is seen in tables.c:

  warning: implicit declaration of function 'memalign'

Add the missing header file to fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
b6524477df x86: Drop asm/acpi.h
Remove asm/acpi.h which is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Simon Glass
a219639d42 dm: Rename disk uclass to ahci
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Bin Meng
7b63b1832b x86: Correct typo of Miao Yan's email address
Miao Yan's email address is wrong in fw_cfg.c. Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-04-22 11:26:32 +08:00
Bin Meng
697ec43146 x86: qemu: Drop our own ACPI implementation
Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set)
does not build anymore after x86 has been fully converted to DM PCI.
Instead of trying to fix the build errors, given we now have the ACPI
support via QEMU's fw_cfg interface, which is a more reliable way to
generate correct ACPI tables than by ourselves, hence drop our own
ACPI implementation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-04-22 11:26:32 +08:00
Simon Glass
c1352119fd arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled
Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:09 -04:00
Stefan Roese
82ceba2ca2 x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
374e78efb0 x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
e5aa8a9b15 x86: Support a chained-boot development flow
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
69ca6fd850 x86: dts: Drop memory SPD compatible string
This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
147ba41d29 x86: ivybridge: Convert to use the common SDRAM code
Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
65dd1507e3 x86: Add common SDRAM-init code
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
7e4a6ae62c x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
1cb1611fc6 x86: Add a function to set the IOAPIC ID
Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
b697b848e8 x86: broadwell: Add support for high-speed I/O lane with ME
Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
2627c7e2c1 x86: broadwell: Add support for SDRAM setup
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
71a8f2080b x86: broadwell: Add power-control support
Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
e7994858ec x86: broadwell: Add reference code support
Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
08cb7420a2 x86: broadwell: Add an LPC driver
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
da3363d5d2 x86: broadwell: Add a northbridge driver
Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
d2c29d9a2c x86: broadwell: Add a SATA driver
Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
b24f5c4f27 x86: broadwell: Add a pinctrl driver
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
1e6f4e5886 x86: broadwell: Add a PCH driver
Add a driver for the broadwell low-power platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
2f3f477b77 x86: Add basic support for broadwell
This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
0adf8d3548 x86: Add support for running Intel reference code
Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.

Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
779653b0cb x86: Drop all the old pin configuration code
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
7ac99be6e2 x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
0a10f440e3 x86: link: Add pin configuration to the device tree
At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
e77b62e290 x86: Update microcode for secondary CPUs
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
6499277827 x86: ivybridge: Show microcode version for each core
Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
6bcb675b2f x86: Record the CPU details when starting each core
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
f7d35bc148 x86: Move common MRC Kconfig options to the common file
At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
005174d661 x86: Allow I/O functions to use pointers
It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:

   struct some_regs {
      u32 ctrl;
      u32 data;
   }

   struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;

   writel(1, &reg->ctrl);
   writel(2, &reg->data);

This does not currently work with inl(), outl(), etc. Add a cast to permit
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
30928c1151 x86: Add macros to clear and set I/O bits
The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.

Add some macros to provide similar features for I/O.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
b70e742d16 x86: ivybridge: Drop sandybridge_early_init()
This function was removed in the previous clean-up. Drop it from the header
file also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
8b900a4175 x86: Move Intel Management Engine code to a common place
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
2a605d4d88 x86: Rename PORT_RESET to IO_PORT_RESET
This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
50dd3da004 x86: Move common CPU code to its own place
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
8c30b57130 x86: Move common LPC code to its own place
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
bb096b9fad x86: Add the root-complex block to common intel registers
This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
06d336cca2 x86: Create a common header for Intel register access
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
9e66506d33 x86: Move microcode code to a common location
This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
1223d737a3 x86: Move cache-as-RAM code into a common location
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
342727ace6 x86: cpu: Add functions to return the family and stepping
These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
5a34957c39 x86: broadwell: Add a few microcode files
Add two microcode files for broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
d116b53f87 x86: Add comments to the SIPI vector
The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
2254e34c3f x86: Tidy up mp_init to reduce duplication
The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
fde467772b x86: Correct duplicate POST values
Two power-on-self-test values are the same. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
d6d50db8a3 x86: gpio: Correct GPIO setup ordering
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
963a811ab4 x86: dts: link: Add board ID GPIOs
At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
a86d45491e x86: dts: link: Move SPD info into the memory controller
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
e9822d44a5 x86: link: Add required GPIO properties
In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
8bf08b4207 x86: Add some more common MSR indexes
Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
6d24a1eebe x86: cpu: Make the vendor table const
This does not need to be modified at run-time, so make it const.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Bin Meng
3cf23719b1 x86: Support booting SeaBIOS
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.

As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
26f9a9b73a x86: Implement functions for writing coreboot table
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
ff94c219e9 x86: Support writing configuration tables in high area
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
ef4d0a524e x86: Simplify codes in write_tables()
Given all table write routines have the same signature, we can
simplify the codes by using a function table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
358bb3ff5b x86: Change write_acpi_tables() signature a little bit
Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
897e1dc86a x86: Use a macro for ROM table alignment
Define ROM_TABLE_ALIGN instead of using 1024 directly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
a5221b5206 x86: Change to use start/end address pair in write_tables()
Add a new variable rom_table_start and pass it to ROM table write
routines. This reads better than previous single rom_table_end.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
f2d0690e28 x86: Clean up coreboot_tables.h
Clean up this file a little bit:
- Remove inclusion of <linux/compiler.h>
- Use tab in the macro definition

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Bin Meng
1329020d21 x86: Move sysinfo related to sysinfo.h
coreboot_tables.h should not include sysinfo related stuff.
Move those to asm/arch-coreboot/sysinfo.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:21 +08:00
Bin Meng
f1d6fda6d3 x86: Move asm/arch-coreboot/tables.h to a common place
Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:21 +08:00
Simon Glass
3f603cbbb8 dm: Use uclass_first_device_err() where it is useful
Use this new function in places where it simplifies the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 15:34:50 -06:00
Bin Meng
a2e3b05e16 x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
87077e97d1 x86: ivybridge: bd82x6x: Support FSP enabled configuration
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
dc5be508b0 x86: fsp: Make sure HOB list is not overwritten by U-Boot
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
4374139627 x86: ivybridge: Add FSP support
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Stephen Warren
4fd64d02b2 x86: fix memalign() parameter order
Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)

Fixes: 45b5a37836 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-21 13:42:51 +08:00
Tom Rini
57dc53a724 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2016-02-08 09:48:04 -05:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Bin Meng
5c884420a5 x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:24 +08:00
Bin Meng
d8277a87d0 x86: Disable DM_PCI_COMPAT
Now that all x86 codes have been converted to use proper DM PCI APIs,
it's time to disable the legacy compatible layer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-05 12:47:24 +08:00
Bin Meng
5a257df702 x86: quark: Use Quark's own PCI config APIs
There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:23 +08:00
Bin Meng
3857ed015f x86: pci: Drop legacy PCI APIs
Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:23 +08:00
Bin Meng
58316f9b9f x86: pci: Use DM PCI APIs in pci_assign_irqs()
Drop legacy PCI APIs usage in pci_assign_irqs() as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
6039200c65 x86: qemu: Convert to use DM PCI API
Use pci_[read|write]_config intead of x86_pci_[read|write]_config.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
66484f0fc0 x86: tnc: Remove IGD and SDVO devices from driver model
With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.

To fix this, manually remove these two devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
2b94d9fca2 x86: tnc: Use DM PCI API in disable_igd()
Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
9e36c53dd0 x86: tnc: Change disable_igd() to have a return value
So far disable_igd() does not have any return value, but we may need
that in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
248c4faa9f x86: irq: Convert to use DM PCI API
Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
b46c2088da x86: irq: Move irq_router to a per driver priv
At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
819133d9f5 x86: irq: Get irq_router's bdf via dm_pci_get_bdf()
There is no need to parse PCH's <reg> property as we have already
a DM PCI API dm_pci_get_bdf() that can handle this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
e75711a4bf x86: minnowmax: Drop io-base property in the pch_pinctrl node
IOBASE is now obtained from PCH driver, drop this <io-base> property.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
2b7ff26115 x86: Drop asm/arch/gpio.h
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
3ddc1c7bd3 x86: ich6_gpio: Convert to use proper DM API
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
ec2af6f82d x86: pch: Implement get_gpio_base op
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
3e389d8ba6 dm: pch: Rename get_sbase op to get_spi_base
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
d02be99e67 dm: pch: Remove pch_get_version op
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
254e677925 x86: quark: Drop unprotect_spi_flash()
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
efd633ccdd x86: tnc: Drop unprotect_spi_flash()
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
1f9eb59d27 spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
81aaa3d9fc x86: Correct spi node alias
With recent changes spi node was moved to a place as a subnode under
pch, so update the alias to refer to its correct place as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 13:53:30 +08:00
Miao Yan
a5dd1e6726 x86: config option for loading ACPI table from QEMU
This patch adds a config option for loading ACPI table from QEMU. When enabled,
U-Boot won't generate ACPI tables, but use those provided by QEMU.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Miao Yan
fa287b1580 x86: qemu: add the ability to load and link ACPI tables from QEMU
This patch adds the ability to load and link ACPI tables provided by QEMU.
QEMU tells guests how to load and patch ACPI tables through its fw_cfg
interface, by adding a firmware file 'etc/table-loader'. Guests are
supposed to parse this file and execute corresponding QEMU commands.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Miao Yan
a3b15a0556 x86: qemu: setup PM IO base for ACPI in southbridge
Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Miao Yan
25757220d6 x86: qemu: re-structure qemu_fwcfg_list_firmware()
Re-write the logic in qemu_fwcfg_list_firmware(), add a function
qemu_fwcfg_read_firmware_list() to handle reading firmware list.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Stefan Roese
d521197d69 x86: baytrail: Add option to disable the internal UART to setup_early_uart()
This patch adds a parameter to the function setup_early_uart() to either
enable or disable the internal BayTrail legacy UART. Since the name
setup_early_uart() does not match its functionality any more, lets
rename it to setup_internal_uart() as well in this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 13:53:30 +08:00
Simon Glass
25d5352c71 x86: ivybridge: Use syscon for the GMA device
Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to work this way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
98655f3a8d x86: Set up a shared syscon numbering schema
Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
67292e4c27 x86: ivybridge: Drop the SMM-locking code
U-Boot does not support SMM yet, so we can drop this code. It is easy to
bring back when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
b2a6235920 x86: ivybridge: Drop XHCI support
This is not used on link which is the only ivybridge board. Drop this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
278d3a4444 x86: ivybridge: Drop special EHCI init
This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
1605b10032 x86: ivybridge: Sort out the calls to bridge_silicon_revision()
This function is called all over the place. Convert it use the driver model
PCI API, and rationalise the calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
a5ea3a7d4a x86: ivybridge: Move code from pch.c to bd82x6x.c
This code relates to the PCH, so we should move it into the same file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
9434c7a35d x86: ivybridge: Convert pch.c to use DM PCI API
Convert this file to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
fad12961b0 x86: ivybridge: Convert report_platform to DM PCI API
Convert these functions to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
c02a4242c8 x86: ivybridge: Convert SDRAM init to use driver model
SDRAM init needs access to the Northbridge controller and the Intel
Management Engine device. Add the latter to the device tree and convert all
of this code to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
1641bb8cc7 x86: ivybridge: Convert sdram_initialise() to use DM PCI API
Convert this function to use the the driver model PCI API. We just need
to pass in the northbridge device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
2588e71132 x86: ivybridge: Convert dram_init() to use DM PCI API
Convert the top part of the DRAM init to use the driver model PCI API.
Further work will complete the transformation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
5213f280fc x86: ivybridge: Convert enable_usb_bar() to use DM PCI API
Convert this function over to use the driver model PCI API. In this case
we want to avoid using the real PCI devices since they have not yet been
probed. Instead, write directly to their PCI configuration address.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
0c7645bde0 x86: ivybridge: Use the I2C driver to perform SMbus init
Move the init code into the I2C driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
4265abd413 x86: ivybridge: Convert lpc init code to DM PCI API
Adjust this code to use the driver model PCI API. This is all called through
lpc_init_extra().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
cdc337ed8f x86: ivybridge: Drop the special PCI driver
There is nothing special about the ivybridge pci driver now, so just use
the generic one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
4e19072907 x86: ivybridge: Move LPC init into the LPC probe() method
Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
865c24eea1 x86: ivybridge: Move lpc_enable() into gma.c
This graphics init code is best placed in the gma init code. Move the code
and drop the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
ddf10c20d2 x86: ivybridge: Use driver model PCI API in sata.c
Adjust the functions in this file to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
01a679084b x86: ivybridge: Use the SATA driver to do the init
Instead of manually initing the device, probe the SATA device and move the
init there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
82935b751b x86: ivybridge: Drop the unused bd82x6x_init_extra()
This function does nothing now so can be dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
d46f2a68e6 x86: ivybridge: Do the SATA init before relocation
The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:39 +08:00
Simon Glass
887cba8f38 x86: ivybridge: Drop unnecessary northbridge setup
This is done by default with PCI auto-config. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:18 +08:00
Simon Glass
1a9dd221c6 x86: ivybridge: Use driver model PCI API in bd82x6x.c
Adjust most of the remaining functions in this file to use the driver model
PCI API. The one remaining function is bridge_silicon_revision() which will
need a little more work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9ed781a6ff x86: ivybridge: Move northbridge and PCH init into drivers
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
ac643e0363 x86: Bring up northbridge, pch and lpc after the CPUs
These devices currently need to be inited early in boot. Once we have the
init in the right places (with each device doing its own init and no
problems with ordering) we should be able to remove this. For now it is
needed to keep things working.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
8b674418e0 x86: Don't show an error when the MRC cache is up to date
When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.

Avoiding printing an error when this happens.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
afd5d50c12 x86: Make x86_init_cpus() static
There are no other implementations of this function, and boards that need it
can implement a CPU driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
279006db4f x86: ivybridge: Move early init code into northbridge.c
This code is now part of the northbridge driver, so move it into the same
place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
d173185d73 x86: ivybridge: Drop the dead MTRR code
This is not used and MTRRs are set up elsewhere now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
709b1902d2 x86: ivybridge: Set up the thermal target correctly
This uses a non-existent node at present. It should use the first CPU node.
The referenced property does not exist (the correct value is the default of
0), but this allows the follow-on init to complete.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9d156b5725 x86: ivybridge: Move CPU init code into the driver
Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
bba22a97a7 x86: ivybridge: Use common CPU init code
The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9fd11c7a8c x86: ivybridge: Move GPIO init to the LPC init() method
This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
fcd30cdfa8 x86: ivybridge: Move sandybridge init to the lpc probe() method
The watchdog can be reset later when probing the LPC after relocation.
Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
17e0a9ab08 x86: ivybridge: Move graphics init much later
We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
f633efa30f x86: ivybridge: Probe the LPC in CPU init
We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
2b27d20529 x86: ivybridge: Rename lpc_init() to lpc_init_extra()
In preparation for adding an init() method to the LPC uclass, rename this
existing function so that it will not conflict.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
977a591893 x86: ivybridge: Move LPC and PCH init into northbridge probe()
Move more code into the northbridge probe() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
655925a9c5 x86: ivybridge: Move northbridge init into the probe() method
Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
e40a6e3f10 x86: ivybridge: Add a driver for the bd82x6x northbridge
Add a driver with an empty probe function where we can move init code in
follow-on patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
5544757ce9 dm: x86: Add a northbridge uclass
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
858361b174 x86: ivybridge: Rename bd82x6x_init()
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
fe40bd4d8f x86: ivybridge: Move more init to the probe() function
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
788cd90864 x86: ivybridge: Move lpc_early_init() to probe()
Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
4acc83d437 x86: ivybridge: Set up the LPC device using driver model
Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
0bdce0751b dm: x86: Drop the weak cpu_irq_init() function
There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
0ac8b1f437 dm: x86: queensbay: Add an interrupt driver
Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
117bfc7fbe dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
b565d66d2c x86: Use the IRQ device when setting up the mptable
Instead of searching for the device tree node, use the IRQ device which has
a record of it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
d3b884b294 dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
12d6929e1f dm: x86: Set up interrupt routing from interrupt_init()
At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().

This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.

Drop pirq_init() since it is no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
e76187a355 dm: x86: Create a driver for x86 interrupts
It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.

As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.

Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
f2b85ab5e6 dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Simon Glass
ca831f4933 dm: Expand the uclass for Platform Controller Hubs (PCH)
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Bin Meng
6071cd62d5 x86: quark: Fix boot breakage
With driver model timer conversion, quark based board does not boot
any more as mdelay() is called during quark_pcie_early_init() which
is before driver model gets initialized. Fix this breakage.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-19 08:32:23 -05:00
Tom Rini
5b8031ccb4 Add more SPDX-License-Identifier tags
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
Tom Rini
4edde96111 Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-01-14 21:51:32 -05:00
Albert ARIBAUD
ecc306639e Fix board init code to respect the C runtime environment
board_init_f_mem() alters the C runtime environment's
stack it is actually already using. This is not a valid
behaviour within a C runtime environment.

Split board_init_f_mem into C functions which do not alter
their own stack and always behave properly with respect to
their C runtime environment.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2016-01-13 21:05:17 -05:00
Miao Yan
3c30fd6ae2 x86: qemu: remove cpu node in device tree
Remove 'cpu' node in device tree for QEMU targets, and let U-Boot detect
and fix up those information at runtime.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13 12:20:16 +08:00
Miao Yan
de752c5e73 x86: qemu: fix cpu device in smp boot
Currently, when booting with more that one CPU enabled, U-Boot scans
'cpu' node in device tree and calculates CPU number. This does not scale
well as changing CPU number also requires modifying .dts and re-compiling
U-Boot.

This patch uses fw_cfg interface provided by QEMU to detect online CPU
number at runtime, and dynamically adds 'cpu' device to U-Boot's driver
model.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13 12:20:16 +08:00
Miao Yan
b28cecdfb8 x86: use actual CPU number for allocating memory
Use actual CPU number, instead of maximum cpu configured, to allocate
stack memory in 'load_sipi_vector'

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13 12:20:15 +08:00
Miao Yan
24fb49073e x86: fix a typo in function name
Rename 'find_cpu_by_apid_id' to 'find_cpu_by_apic_id'. This should be a
typo.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13 12:20:15 +08:00
Miao Yan
5a694056fe x86: qemu: add a cpu uclass driver for qemu target
Add a cpu uclass driver for qemu. Previously, the qemu target gets cpu
number from board dts files, which are manually created at compile time.
This does not scale when more cpus are assigned to guest as the dts files
must be modified as well.

This patch adds a cpu uclass driver for qemu targets to directly read
online cpu number from firmware.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13 12:20:15 +08:00
Miao Yan
f60df20aa9 x86: qemu: add fw_cfg support
The QEMU fw_cfg interface allows the guest to retrieve various data
information from QEMU. For example, APCI/SMBios tables, number of online
cpus, kernel data and command line, etc.

This patch adds support for QEMU fw_cfg interface.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13 12:20:15 +08:00
Bin Meng
87968de31d x86: ivybridge: Add macros for LPC decode ranges
Add several macros for LPC decode registers on PCH.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:15 +08:00
Bin Meng
59fb7fbd49 x86: fsp: Always use hex numbers in the hob command output
In the 'fsp hob' command output, decimal numbers and hexadecimal
numbers are used mixedly. Now change to always use hex numbers
to keep consistency.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:15 +08:00
Bin Meng
fa331fad1e x86: ivybridge: Do not require HAVE_INTEL_ME
Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:15 +08:00
Bin Meng
33fb6c0100 x86: ivybridge: Add microcode blobs for all the steppings
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:15 +08:00
Bin Meng
214feec1c5 x86: fsp: Set up init runtime buffer in update_fsp_configs()
fsp_init() runtime buffer parameter might be different across
different platforms. Move this to update_fsp_configs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
4ce022d396 x86: fsp: Move struct fspinit_rtbuf definition to chipset header
All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf
as defined by the 1.0 spec, however there are FSPs that does not
follow 1.0 spec (possible due to that FSP predates the 1.0 spec),
and future FSP binary that is complaint to v1.1 spec defines an
optional paltform-specific runtime data in the struct fspinit_rtbuf.
Hence move the definition to chipset header.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
e293502280 x86: queensbay: Remove invalid comments in update_fsp_configs()
Those comments in update_fsp_configs() are not correct. Remove them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
3340f2cc0b x86: fsp: Introduce CONFIG_FSP_USE_UPD Kconfig option
Not every FSP supports UPD, thus we introduce a Kconfig option
CONFIG_FSP_USE_UPD and use it to wrap these common UPD handling
codes in fsp_support.c.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
81f84aa6c9 x86: fsp: Rename update_fsp_upd() and change its signature
To support platform-specific configurations (might not always be
UPD on some platform), use a better name update_fsp_configs() and
accepct struct fsp_config_data as its parameter so that platform
codes can handle whatever configuration data for that FSP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
cb379a34c4 x86: fsp: Rename shared_data to fsp_config_data
FSP has several config data like UPD, HDA verb table which can be
overridden or provided by bootloader. Currently in U-Boot only UPD
is handled via struct shared_data. To accommodate any platform, we
rename shared_data to fsp_config_data and move the definition from
common place fsp_support.h to platform-specific place fsp_configs.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
57ac74ff04 x86: fsp: Add boot_mode as a member of struct shared_data
Save boot_mode in struct shared_data for future refactoring.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
f0285fbe4e x86: fsp: Avoid cast stack_top in struct shared_data
Declare stack_top as u32 in struct shared_data and struct common_buf
so that we can avoid casting in fsp_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:13 +08:00
Bin Meng
aa02446406 x86: fsp: Simplify fsp_continue()
There is no need to pass shared_data to fsp_continue() so we can
remove unnecessary codes that simplifies the function a lot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:13 +08:00
Simon Glass
4abe8e40a7 dm: Convert PCI MMC over to use DM PCI API
At present pci_mmc_init() does not correctly use the PCI function since the
list it passes is not terminated. The array size passed to pci_mmc_init() is
actually not used correctly. Fix this and adjust the pci_mmc_init() to scan
all available MMC devices.

Adjust this code to use the new driver model PCI API.

This should move over to the new MMC uclass at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Simon Glass
8beb0bda9c dm: x86: pci: Adjust bios_run_on_x86() to use the DM PCI API
This function should take a struct udevice rather than pci_dev_t. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Simon Glass
3f4e1e8efc dm: pci: video: Convert video and pci_rom to use DM PCI API
Adjust these files to use the driver-model PCI API instead of the legacy
functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Simon Glass
7d8e4042f1 dm: Convert bios_interrupts to use DM PCI API
Adjust this code to use driver model for devices where possible. Since
existing users have not been converted the old code must remain.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Simon Glass
9bf727fcc4 dm: x86: ivybridge: Convert graphics init to use DM PCI API
Use the driver-model PCI functions here where possible. For now we have to
search for the device with pci_bus_find_bdf() but at some point we can put
this in a proper driver and avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Bin Meng
789fa275b3 x86: Remove HAVE_ACPI_RESUME
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:56 +08:00
Bin Meng
d475d59020 x86: Remove CPU_INTEL_SOCKET_RPGA989
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:54 +08:00
Bin Meng
efe2d80cca x86: Clean up ivybridge/chrome Kconfig options
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:52 +08:00
Bin Meng
9bf76c21e0 x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:50 +08:00
Bin Meng
4932443d26 x86: Move i8254_init() to x86_cpu_init_f()
Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:44 +08:00
Bin Meng
c5c5c201fe x86: Fix PCI UART compatible string for crownbay and galileo
With recent ns16550 driver changes, we only changed the legacy UART
(at I/O port 0x3f8) compatible string, but forgot to change the PCI
UART compatible string. Now fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:41 +08:00
Simon Glass
3ba5f74a54 dm: pci: Disable PCI compatibility functions by default
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:38 -07:00
Bin Meng
7030f27ef3 x86: tsc: Move tsc_timer.c to drivers/timer
To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
1d4c83c248 x86: tsc: Remove legacy timer codes
Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.

Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
80af39842e x86: Convert to use driver model timer
Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
4e51fc2351 x86: tsc: Add driver model timer support
This adds driver model timer support to x86 tsc timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
2f80fc5035 x86: tsc: Use notrace from <linux/compiler.h>
Replace __attribute__((no_instrument_function)) with notrace from
<linux/compiler.h>.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
0f3176ed68 x86: Remove MIN_PORT80_KCLOCKS_DELAY
This is not referenced anywhere. Remove it, as well as
tsc_base_kclocks and tsc_prev in the global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix 'Reomve' typo:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Thomas Chou
81cd63a991 ns16550: unify serial_x86
Unify serial_x86, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20 20:41:30 -05:00
Bin Meng
b6ff6ce60c x86: qemu: Convert to use driver model keyboard
Convert to use driver model keyboard on QEMU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:42 -07:00
Bin Meng
60fe101873 x86: crownbay: Convert to use driver model keyboard
Convert to use driver model keyboard on Intel Crown Bay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:42 -07:00
Simon Glass
6b44ae6b06 x86: Add an i8042 device for boards that have it
Some boards have an i8042 device. Enable the driver for all x86 boards, and
add a device tree node for those which may have this keyboard.

Also adjust the configuration so that i8042 is always separate from the VGA,
and rename the stdin driver accordingly. With this commit the keyboard will
not work, but it is fixed in the next commit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-19 20:13:41 -07:00
Bin Meng
902ca5bdf3 x86: Remove legacy pci codes
Now that we have converted all x86 boards to use driver model pci,
remove these legacy pci codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:25 -08:00
Bin Meng
aedefb6f79 x86: qemu: Convert to use driver model pci
Move to driver model for pci on QEMU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:23 -08:00
Bin Meng
487485956b x86: qemu: Move chipset-specific codes from pci.c to qemu.c
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table
from pci.c to qemu.c, to prepare for DM PCI conversion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:22 -08:00
Bin Meng
20cbafa6fa x86: qemu: Remove call to vgabios execution
The call to pci_run_vga_bios() is not needed as this is handled
in the vesa_fb driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:21 -08:00
Bin Meng
e5ffa4bb62 x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.

However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.

To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:20 -08:00
Bin Meng
1eb39a5093 x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to Kconfig
Add Kconfig options for 8259 and 8254.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:19 -08:00
Bin Meng
da3fe24759 x86: Rename pcat_ to i8254 and i8259 accordingly
Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:18 -08:00
Bin Meng
bffeed0158 x86: Initialize i8254 timer counter 1
Initialize counter 1, used to refresh request signal. This is
required for legacy purpose as some codes like vgabios utilizes
counter 1 to provide delay functionality.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:18 -08:00
Bin Meng
0a2ea02068 x86: Fix cosmetic issues in the i8254 and i8259 codes
This cleans up i8254 and i8259 codes to fix several cosmetic
issues, like coding convention and some comments improvement.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:17 -08:00
Bin Meng
360c3013c8 x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERS
PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot.
Remove these dead codes wrapped by it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:16 -08:00
Bin Meng
6c5052716e x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQS
CONFIG_SYS_NUM_IRQS is actually not something we can configure,
but an architecture defined number of ISA IRQs. Move it from
x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:16 -08:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Fabio Estevam
6c2f758cee x86: Use the generic bitops headers
Use the generic bitops and also add custom __ffs() implementation
as per the kernel.

Also align the ffs() implementation with the kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:01 -05:00
George McCollister
e0ae64880b x86: Add support for Advantech SOM-6896
Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
Type 6. This patch adds support for it as a coreboot payload.

On board SATA and SPI are functional. On board Ethernet isn't functional
but since it's optional and ties up a PCIe x4 that is otherwise brought
out, this isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-21 16:29:27 -06:00
Bin Meng
3e45de6ed4 x86: ivybridge: Enable the MRC cache
This works correctly now, so enable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Dropped malloc() and adjusted commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:51 -06:00
Simon Glass
fd8f4729ac x86: ivybridge: Measure the MRC code execution time
This code takes about 450ms without the MRC cache and about 27ms with the
cache. Add a debug timer so that this time can be displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:51 -06:00
Simon Glass
e9b3967c0c x86: ivybridge: Fix car_uninit() to correctly set run state
At present a missing $ causes this code to hang when using the MRC cache/
Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:51 -06:00
Simon Glass
9fbc5ccd79 x86: ivybridge: Check the RTC return value
The RTC can fail, so check the return value for reads.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
53327d3e61 x86: ivybridge: Use 'ret' instead of 'rcode'
For consistency, use 'ret' to handle a return value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
7b95252d82 x86: chromebook_link: Enable the debug UART
Add support for the debug UART on link. This is useful for early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
60994a02a5 x86: Init the debug UART if enabled
If the debug UART is enabled, get it ready for use at the earliest possible
opportunity. This is not actually very early, but until we have a stack it
is difficult to make it work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Bin Meng
ef1683d5c3 x86: Pass correct cpu_index to ap_init()
In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten
by the ap_init() function address. Correct it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
06f16c4148 x86: galileo: Enable mrc cache
Now that we have added MRC cache on quark support codes,
enable it on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
2fc2b83a7d x86: quark: Implement mrc cache
Using existing mrccache library to implement mrc cache support
for Intel Quark.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
c6c80d8b3e x86: ivybridge: Correct two typos for MRC
It should be MRC, not MCR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ec73da82a6 x86: Remove unused rw-mrc-cache properties in the link and panther dts files
"type" and "wipe-value" are never used by the mrccache codes.
Remove them to avoid confusion. This also removes the alignment
comment in the panther dts file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
74e56d1953 x86: baytrail: Issue full system reset in reset_cpu()
With MRC cache enabled, when typing 'reset' in the U-Boot shell,
BayTrail FSP initialization hangs at "Configuring Memory Start":

  Setting BootMode to 0
  Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
  Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
  About to call MrcInit();
  BayleyBay Platform Type
  CurrentMrcData.BootMode = 4
  Taking Fastboot path!
  Configuring Memory Start...

Changing reset_cpu() to do a full system reset fixes this issue.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
638a058941 x86: Enable mrc cache for bayleybay and minnowmax
Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).

Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
8b185041a9 x86: baytrail: Save mrc cache to spi flash
Save MRC cache to SPI flash in arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ff1e18af9d x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()
fsp_init() call has a parameter nvs_buf which is used by FSP as the
MRC cache but currently is blindly set to NULL. Retreive the MRC
cache from SPI flash and pass it to fsp_init() call. After the call,
save FSP produced MRC cache to SPI flash too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
4b9f6a669e x86: Use struct mrc_region to describe a mrc region
Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.

Define a new struct mrc_region and use it instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
42913a1c7a x86: ivybridge: Use APIs provided in the mrccache lib
Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ed800961a0 x86: Add more common routines to manipulate mrc cache
This adds mrccache_reserve(), mrccache_get_region() and
mrccache_save() APIs to the mrccache codes. They are ported
from the ivybridge implementation, but with some changes.
For example, in the mrccache_reserve(), ivybridge version
only reserves the pure MRC data, which causes additional
malloc() when saving the cache as the save API needs some
meta data. Now we change it to save the whole MRC date plus
the meta data to elinimate the need for the malloc() later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
bfa95c538b x86: Add various minor tidy-ups in mrccache codes
Fix some nits, improve some comments and reorder some codes
a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
2fe66dbcbc x86: Do sanity test on the cache record in mrccache_update()
For the cache record to write in mrccache_update(), we should
perform a sanity test to see if it is a valid one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
f6220f1a86 x86: Move mrccache.[c|h] to a common place
mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
e2d76e95d3 x86: Add ENABLE_MRC_CACHE Kconfig option
Create a Kconfig option for enabling MRC cache.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
010921ae7f x86: fsp: Add a hdr sub-command to show header information
It would be helpful to have a command to show FSP header. So far
it only supports FSP header which conforms to FSP spec 1.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
62716ebb75 x86: fsp: Make hob command a sub-command to fsp
Introduce a new fsp command and make the existing hob command a
sub-command to fsp for future extension. Also move cmd_hob.c to
the dedicated fsp sub-directory in arch/x86/lib.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
b325cbb171 x86: fsp: Print GUID whenever applicable in the hob command output
When examining a HOB, it's useful to see which GUID this HOB
belongs to. Add GUID output in the hob command to aid this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
fd755f084e x86: fsp: Compact the output of hob command
Compact hob command output, especially by making hob type string a
little bit shorter so that we can leave room for future extension.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
721e992a8a x86: Add SMBIOS table support
System Management BIOS (SMBIOS) is a specification for how
motherboard and system vendors present management information
about their products in a standard format by extending the BIOS
interface on Intel architecture systems. As of today the latest
spec is 3.0 and can be downloaded from DMTF website. This commit
adds a simple and minimum required implementation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
59ec719df6 x86: Move install_e820_map() out of zimage.c
install_e820_map() has nothing to do with zimage related codes.
Move it to a dedicated place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Bin Meng
19038e1bb6 x86: Initialize GDT entry 1 to be the 32-bit CS as well
Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
2015-10-21 07:46:25 -06:00
Bin Meng
1f124eba11 x86: Allow disabling IGD on Intel Queensbay
Add a Kconfig option to disable the Integrated Graphics Device (IGD)
so that it does not show in the PCI configuration space as a VGA
disaplay controller. This gives a chance for U-Boot to run PCI/PCIe
based graphics card's VGA BIOS and use that for the graphics console.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Bin Meng
5bf935925b x86: ivybridge: Remove the dead codes that programs pci bridge
Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Bin Meng
196193a4d4 x86: fsp: Report correct number of E820 table entries
The logic to calculate the number of E820 table entries is wrong
when walking through the FSP HOB tables. Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-28 21:56:27 -07:00
Bin Meng
c6d4705f41 x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.

We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.

With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
5bf0f7f65d x86: galileo: Add PCIe root port IRQ routing
Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
554778c240 x86: quark: Initialize thermal sensor properly
Thermal sensor on Quark SoC needs to be properly initialized per
Quark firmware writer guide, otherwise when booting Linux kernel,
it triggers system shutdown because of wrong temperature in the
thermal sensor is detected by the kernel driver (see below):

[    5.119819] thermal_sys: Critical temperature reached(206 C),shutting down
[    5.128997] Failed to start orderly shutdown: forcing the issue
[    5.135495] Emergency Sync complete

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
693b5f6c71 x86: quark: Lock HMBOUND register before jumping to kernel
When Linux kernel boots, it hangs at:

[    0.829408] Intel Quark side-band driver registered

This happens when Quark kernel Isolated Memory Region (IMR) driver
tries to lock an IMR register to protect kernel's text and rodata
sections. However in order to have IMR function correctly, HMBOUND
register must be locked otherwise the system just hangs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
8e3683029e x86: quark: Convert to use clrbits, setbits, clrsetbits macros
Change existing codes to use clrbits, setbits, clrsetbits macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
d0b3e3bfbb x86: quark: Add clrbits, setbits, clrsetbits macros for message port access
On Intel Quark, lots of registers on the message port need be
programmed. Add handy clrbits, setbits, clrsetbits macros for
message port access.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
2afb62305e x86: quark: Add PCIe/USB static register programming after memory init
This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
5841c5b0a7 x86: Convert to use driver model eth on quark/galileo
Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
b06862b9d8 x86: quark: Add USB PHY initialization support
USB PHY needs to be properly initialized per Quark firmware writer
guide, otherwise the EHCI controller on Quark SoC won't work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
31b5aebd5e x86: Convert to use driver model pci on quark/galileo
Move to driver model pci for Intel quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
316fd3920f x86: Enable PCIe controller on quark/galileo
Quark SoC holds the PCIe controller in reset following a power on.
U-Boot needs to release the PCIe controller from reset. The PCIe
controller (D23:F0/F1) will not be visible in PCI configuration
space and any access to its PCI configuration registers will cause
system hang while it is held in reset.

Enable PCIe controller per Quark firmware writer guide.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
aa09505ba1 x86: quark: Avoid chicken and egg problem
If we convert to use driver model pci on quark, we will encounter
some chicken and egg problems like below:

- To enable PCIe root ports, we need program some registers on the
  message bus via pci bus. With driver model, the first time to
  access pci bus, the pci enumeration process will be triggered.
  But without first enabling PCIe root ports, pci enumeration
  just hangs when scanning PCIe root ports.
- Similar situation happens when trying to access GPIO from the
  PCIe enabling codes, as GPIO requires its block base address
  to be assigned via a pci configuration register in the bridge.

To avoid such dilemma, replace all pci calls in the quark codes
to use the local version which does not go through driver model.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
5750e5e29a x86: quark: Optimize MRC execution time
Intel Quark SoC has a low end x86 processor with only 400MHz
frequency. Currently it takes about 15 seconds for U-Boot to
boot to shell and the most time consuming part is with MRC,
which is about 12 seconds. MRC programs lots of registers on
the SoC internal message bus indirectly accessed via pci bus.

To speed up the boot, create an optimized version of pci config
read/write dword routines which directly operate on PCI I/O ports.
These two routines are inlined to provide better performance too.
Now it only takes about 3 seconds to finish MRC, which is really
fast (4 times faster than before).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
5bc60d5a44 x86: coreboot: Convert to use more dm drivers
Move to driver model for RTC, USB and ETH on coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Simon Glass
548fb8777d x86: panther: Add PCI and video configuration
Add a PCI node to the device tree. This allows SPI flash and SATA to work
correctly. Also configure the video to come up correctly even though there
is no keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-09-09 07:48:03 -06:00
Simon Glass
6e474eab44 exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices
Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2015-08-31 07:57:28 -06:00
Bin Meng
a1f1582b73 x86: crownbay: Support Topcliff integrated pci uart devices with driver model
In order to make a pci uart device node to be properly bound to its
driver, we need make sure its parent node has a compatible string
which matches a driver that scans all of its child device nodes in
the device tree.

Change all pci bridge nodes under root pci node to use "pci-bridge"
compatible driver, as well as corresponding <reg> properties to
indicate its devfn. At last, adding "u-boot,dm-pre-reloc" to each
of these nodes for driver model to initialize them before relocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:17 -07:00
Bin Meng
4dd02a752c x86: crownbay: Enable on-board SMSC superio keyboard controller
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.

In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:16 -07:00
Simon Glass
86645c8932 x86: minnowmax: Correct pad-offset value for host_en1
This should be 0x250, not 0x258. Fix it.

Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Simon Glass
cce7e0fa2b x86: minnowmax: Add access to GPIOs E0, E1, E2
These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Saket Sinha
bccdf1de75 x86: Add DSDT table for supporting ACPI on QEMU
The DSDT table contains a bytecode that is executed by a driver in the kernel.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Tested with QEMU '-M q35'
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:14 -07:00
Saket Sinha
e94019ede7 x86: Add ACPI table support to QEMU
This patch mainly adds ACPI support to QEMU.
Verified by booting Linux kernel on QEMU Q35.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Minor whitespace fixes and dropped mention of i440FX in commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Saket Sinha
867bcb63e7 x86: Generate a valid ACPI table
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT
ACPI table entries.

Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need
actually write the APCI table just like we did for PIRQ routing, MP table
and SFI tables. With ACPI table existence, linux kernel gets control of
power management, thermal management, configuration management and
monitoring in hardware.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tidied up whitespace and aligned some tabs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:13 -07:00
Bin Meng
c78dfb4fd2 x86: superio: Add keyboard controller support to smsc_lpc47m driver
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:12 -07:00
Bin Meng
fa6af7b4e0 x86: baytrail: Remove the fsp_init_phase_pci() call
It turns out that calling fsp_init_phase_pci() in arch_misc_init()
is subject to break pci device drivers as with driver model, when
the bus enumeration happens is not deterministic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:12 -07:00
Bin Meng
090290f97b x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()
With dm pci conversion, pci config read/write in unprotect_spi_flash()
silently fails as at that time dm pci is not ready and bus enumeration
is not done yet. Actually we don't need to do this in that early phase,
hence we delay this call to arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:12 -07:00
Bin Meng
48aa6c2614 x86: fsp: Add comments about U-Boot entering start.S twice
Add some comments in start.S for the fact that with FSP U-Boot
actually enters the code twice. Also change to use fsp_init()
and fsp_continue for accuracy.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:11 -07:00
Bin Meng
57b10f59b7 x86: fsp: Enlarge the size of malloc() pool before relocation
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Enlarge the size of malloc() pool before relocation since we have
plenty of memory now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:11 -07:00
Bin Meng
5fb0151697 x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:09 -07:00
Bin Meng
5c113ff79c x86: baytrail: Add microcode for BayTrail-I D0 stepping
This commit adds the microcode blob for BayTrail-I D0 stepping,
CPUID signature 30679h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:09 -07:00
Bin Meng
8744bef5a1 x86: kconfig: Hide "System tables" for coreboot
When booting as a coreboot payload, we don't need write any
configuration tables as coreboot does that for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:08 -07:00
Bin Meng
d2f56f46fe x86: kconfig: Hide "System tables" for EFI
Instead of hiding each menu entries under "System tables" for EFI,
hide the main menu completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
a25bc78e2f x86: coreboot: Allow >=4GiB memory bank size
Some platforms may have >=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
c17ca6b5cd x86: Remove calculate_relocation_address()
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
52b778603b x86: coreboot: Correctly report E820 types
coreboot has some extensions (type 6 & 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
89b870814c x86: coreboot: Increase memrange entry number to 32
Increase lib_sysinfo memrange entry number to 32 to sync with coreboot.
This allows a complete E820 table to be reported to the kernel, as on
some platforms (eg: Bayley Bay) having only 16 entires does not cover
all the memory ranges.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:06 -07:00
Simon Glass
ef910819c5 x86: minnowmax: Define and enable interrupt setup
Set up interrupts correctly so that Linux can use all devices. Use
savedefconfig to regenerate the defconfig file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:14 -06:00
Simon Glass
052e34b363 x86: Return -1 when reading a PCI config register fails
This can fail for internal reasons, so return a sensible value rather than
a random one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:13 -06:00
Simon Glass
ecf674b772 x86: Drop FSP error defines and use EFI instead
Now that we have an efi.h header we can use that for FSP error defines.
Drop the FSP ones.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:13 -06:00
Bin Meng
ecfeadabb7 x86: Set APs' req_seq to the reg number from device tree
Multiple APs are brought up simultaneously and they may get the same
seq num in the uclass_resolve_seq() during device_probe(). To avoid
this, set req_seq to the reg number in the device tree in advance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-14 09:50:12 -06:00
Simon Glass
7399515d25 x86: Show the un-relocated IP address in exceptions
When trying to figure out where an exception has occured, the relocated
address is not a lot of help. Its value depends on various factors. Show
the un-relocated IP as well. This can be looked up in System.map directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:12 -06:00
Simon Glass
f0c7d9c746 x86: Switch to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:10 -06:00
Simon Glass
2db9374561 x86: Move the GDT into global_data
Rather than keeping track of the Global Descriptor Table in its own memory
we may as well put it in global_data with everything else. As a first step,
stop using the separately allocated GDT.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:10 -06:00
Simon Glass
93afae5d05 x86: Remove init_gd() function
This is declared but no-longer exists. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
c8896ee481 x86: baytrail: Support running as an EFI payload
We should not fiddle with interrupts or the FSP when running as an EFI
payload. Detect this and skip this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
46f8efee70 x86: baytrail: Tidy up interrupt and FSP init
We should signal to the FSP that PCI enumeration is complete. Perform this
task in a suitable place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
7e4be120e8 x86: Allow pirq_init() to return an error
This function can fail. In this case we should return the error rather than
swallowing it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
412400abaa x86: Split out fsp_init_phase_pci() code into a new function
This code may be useful for boards that use driver model for PCI.

Note: It would be better to have driver model automatically call this
function somehow. However for now it is probably safer to have it under
board control.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
9e3ff9c2b4 x86: Tidy up the PIRQ routing code a little
This code could use a little tightening up. There is some repetition and
an odd use of fdtdec_get_int_array().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Bin Meng
da60fb7934 x86: fsp: Do not assert VPD_IMAGE_REV when DEBUG
When using different release version of Intel FSP, the VPD_IMAGE_REV
is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304).
Remove the asserting of this so that U-Boot does not hang in a debug
build.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Andrew Bradford
f3b84a3032 x86: baytrail: Configure FSP UPD from device tree
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Simon Glass
bbbe55f6f2 x86: Enable debug UART for Minnowmax
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.

Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.

So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-08-06 07:44:30 -06:00
Simon Glass
eeae510007 x86: qemu: Support operation as an EFI payload
Disable a few things which interfere with the EFI init. This allows QEMU to
to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
b4302582f3 x86: baytrail: Support operation as an EFI payload
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
8e36650875 x86: Add helper code for running from EFI
When U-Boot is running from EFI some of the x86 init is replaced with
EFI-specific init. For example, since DRAM has already been set up, we only
need to find it, not init it. Add these functions so that boards can easily
allow booting from EFI if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
e49cceac61 x86: Handle running as EFI payload
When U-Boot runs as an EFI payload it needs to avoid setting up the CPU
again. Also U-Boot currently does not handle interrupts for many devices, so
run with interrupts disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
42fde30500 x86: Add support for passing tables into U-Boot
The EFI stub provides information to U-Boot in a table. This includes the
memory map which is needed to decide where to relocate U-Boot. Collect this
information in the early init code and store it in global_data.

Fix up the BIST code at the same time since we don't have it when booting
from EFI and can assume it is 0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
96a8d409a7 efi: Add 64-bit payload support
Most EFI implementations use 64-bit. Add a way to build U-Boot as a 64-bit
EFI payload. The payload unpacks a (32-bit) U-Boot and starts it. This can
be enabled for x86 boards at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
6f92ed8f1a x86: Add a way to call 32-bit code from 64-bit mode
The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a
function to take care of it. It requires identity-mapped pages and that
the calling code is running below 4GB.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
7dfe8bdeef x86: Add an enum for some commonly-used GDT bits
Rather than add these as open-coded values, create an enum with the commonly
used flags.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
b997abd3f0 x86: Support building the EFI stub
Add support for building a 32/64-bit EFI stub for x86. This involves
building the startup and relocation code for either i386 or x86_64.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
476476e73b efi: Add support for loading U-Boot through an EFI stub
It is useful to be able to load U-Boot onto a board even if is it already
running EFI. This can allow access to the U-Boot command interface, flexible
booting options and easier development.

The easiest way to do this is to build U-Boot as a binary blob and have an
EFI stub copy it into RAM. Add support for this feature, targeting 32-bit
initially.

Also add a way to detect when U-Boot has been loaded via a stub. This goes
in common.h since it needs to be widely available so that we avoid redoing
initialisation that should be skipped.

Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
465a67cf52 x86: Add relocation and link script for a 64-bit EFI application
Add a linker script and relocation code for building 64-bit EFI
applications. This can be used for the EFI stub.

Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
a42bfe02d3 x86: Allow relocation code to build without text base
This code currently requires CONFIG_SYS_TEXT_BASE but this should be
unnecessary. As a first step, remove the build-time limitation and report an
error instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
d6c099c2a1 x86: dts: Add a device tree file for EFI
This contains just enough to bring up the serial UART.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Ben Stoltz
3e9aa32055 x86: Add EFI board code
Add support for the efi-x86 board, which supports running U-Boot as an
EFI 32-bit application.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Ben Stoltz
3dcdd17b43 x86: Add support for U-Boot as an EFI application
Add the required x86 glue code. This includes the initial start-up,
relocation and jumping to efi_main(). We also need to avoid fiddling with
interrupts.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
ed3b4d3736 x86: Add asm/elf.h for x86-specific ELF definitions
Bring in this file from Linux 4.1. It supports relocation features specific
to x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:05 -06:00
Simon Glass
981dca69f6 x86: Support skipping relocation for EFI
When running as an EFI application we must skip relocation. Add support for
this in the x86 relocation code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:05 -06:00
Ben Stoltz
3f1c046cea x86: Set up toolchain flags for running as EFI application
Adjust the toolchain flags to build U-Boot as a relocatable shared library,
as required by EFI.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:05 -06:00
Simon Glass
867a6ac86d efi: Add start-up library code
When running as an EFI application, U-Boot must request memory from EFI,
and provide access to the boot services U-Boot needs.

Add library code to perform these tasks. This includes efi_main() which is
the entry point from EFI. U-Boot is built as a shared library.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
8f3b9694b2 x86: Allow use of global_data with EFI
On x86 the global_data pointer is provided through a somewhat-bizarre and
x86-specific mechanism: the F segment register is set to a pointer to the
start of global_data, so that accesses can use this build-in register.

When running as an EFI application we don't want to mess with the Global
Descriptor Table (GDT) and there is little advantage (in terms of code size)
to doing so.

Allow global_data to be a simple variable in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
8aba36d896 x86: Tidy up a few minor issues with interrupts
Fix a typo, remove an unused field and make sure to use existing #define
constants instead of open-coded values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
8b097916fa x86: Add some missing global_data declarations in files that use gd
Some files use global_data but don't declare it. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
0bc74ab3e6 x86: Tidy up the 64-bit calling code
The GDT works but technically the length is incorrect. Fix this and add a
comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
0d9edd2dfb x86: Drop unused copy_fdt_to_ram()
This is now handled by generic U-Boot code so we do not need an x86 version.
It is no-longer called, so remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Simon Glass
83ec7de3bc x86: Tidy up global_data flags
These flags now overlap some global ones. Adjust the x86-specific flags to
avoid this. Since this requires a change to the start.S code, add a way for
tools to find the 32-bit cold reset entry point. Previously this was at a
fixed offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Simon Glass
b6c9a20556 x86: Use CR0 constants in CPU init
We should use these constants where possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Simon Glass
da3a95d60b x86: Add various minor tidy-ups to the 32-bit startup code
Fix a typo, improve some comments and add a little more detail in some
cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Bin Meng
fe3fbd3024 x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
9b911bed78 x86: Add Intel Bayley Bay board support
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
2774ff720d x86: Add microcode for BayTrail-I B0 stepping
This commit adds the microcode blob for BayTrail-I B0 stepping,
CPUID signature 30671h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
3e79a4ab26 x86: baytrail: Update UPD setting for FSP Gold4 release
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
a2eb65fcad x86: qemu: Add MP initialization
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:38 -06:00
Miao Yan
417576c2f1 x86: Add a 'pause' instruction in __udelay() for QEMU target
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.

This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:38 -06:00
Bin Meng
1ed6648be0 x86: Reserve PCIe ECAM address range in the E820 table
We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
9830d2ebb4 x86: qemu: Turn on PCIe ECAM address range decoding on Q35
Turn on PCIe ECAM address range decoding on Q35.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
a8ebf283e9 x86: qemu: Enable writing MP table
Enable writing MP table for QEMU boads (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
c77b8912d8 x86: Allow cpu-x86 driver to be probed for UP
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
e7cd070da6 x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
53832bb8d6 x86: mpspec: Move writing ISA interrupt entry after PCI
On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
abab912813 x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
a277194341 x86: Convert to use driver model pci on queensbay/crownbay
Move to driver model pci for Intel queensbay/crownbay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:24 -06:00
Bin Meng
6fc0e8a1fa x86: pci: Do not assign irq 0 to pci device
IRQ 0 is reserved and should not be assigned to pci device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
31a2dc6955 x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
93f8a31186 x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-28 10:36:22 -06:00
Bin Meng
8ba25eec86 x86: Change pci option rom area MTRR setting to cacheable
Turn on cache on the pci option rom area to improve the performance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
3ccd49cab4 x86: Simplify architecture defined exception handling in irq_llsr()
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.

With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:21 -06:00
Bin Meng
013cf483c9 x86: Display correct CS/EIP/EFLAGS when there is an error code
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:21 -06:00
Masahiro Yamada
b0c8f4a797 Kill unneeded #include <linux/kconfig.h>
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.

By the way, there are exceptions for the statement above; host
programs.  In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not.  So, some
files still include <linux/config.h> to work around build errors
on host tools.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-27 15:02:12 -04:00
Masahiro Yamada
5f7e310467 x86: delete unneeded declarations of disable_irq() and enable_irq()
These two declarations in arch/x86/include/asm/interrupt.h conflict
with ones in include/linux/compat.h, so x86 boards cannot include
<linux/compat.h>.

The comment /* arch/x86/lib/interrupts.c */ is bogus now, and we do
not see any definitions of disable_irq() and enable_irq() in there.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-22 07:30:31 -06:00
Simon Glass
b9da5086b8 dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Simon Glass
b71f9dca89 dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:19 -06:00
Simon Glass
945cae79e1 x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Bin Meng
a452002259 x86: Configure VESA parameters before loading Linux kernel
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
2015-07-14 18:03:19 -06:00
Bin Meng
9e3a7c9bac x86: Remove MARK_GRAPHICS_MEM_WRCOMB
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
786a08e0dd x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
df07d91956 x86: cmd_mtrr: Improve MTRR list information
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
92587b364b x86: queensbay: Change CPU_ADDR_BITS to 32
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
43dd22f5fc x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Jian Luo
1441d81a79 x86: bios: Allow pci config read/write to host bridge in int1a_handler
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Jian Luo
7b5c349890 x86: bios: Synchronize stack between real and protected mode
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
cdb6babec6 x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
07545d861c x86: Generate a valid MultiProcessor (MP) table
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.

Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
7f5df8d42d x86: Add MultiProcessor (MP) table APIs
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
a2d73fdba6 x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
3d23287828 x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
ba9091f55d x86: Clean up ioapic header file
Remove all the dead/unused macros from asm/ioapic.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
df81749db7 x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
8c38e4d0b8 x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
9c235436a3 x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
d402f922b2 x86: queensbay: Correct Topcliff device irqs
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.

This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
b0014b6423 x86: crownbay: Enable DM RTC support
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
990acd0d51 x86: crownbay: Add MP initialization
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
   overriding the value of OF_CONTROL. Old value: "y", new value: "y")
2015-07-14 18:03:16 -06:00
Bin Meng
63d54a6705 x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
  defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
  CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
  it is not apic related and only used by ivybridge
- Fix coding convention issues

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
61788e468e x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
6e6f4ce4f8 x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
946c2b5259 x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
Ivybridge is not ready for U-Boot MP initialization yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
4c71322b41 x86: kconfig: Fix minor nits in MAX_CPUS
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
063374d2f6 x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
be3f06bcc4 x86: dm: Clean up cpu drivers
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
  file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
  naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
  the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
  cpu_x86_bind()

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
aefaff8ed8 x86: fsp: Move FspInitEntry call to board_init_f()
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.

Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
002610f620 x86: fsp: Load GDT before calling FspInitEntry
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.

To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
343fb99064 x86: Add Kconfig options to be used by arch/x86/cpu/config.mk
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Joe Hershberger
c9bb942e2f Move default y configs out of arch/board Kconfig
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.

Remove the configs that behave this way from the archs.

A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:

SPIFLASH
DISPLAY_BOARDINFO

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-06-25 22:17:55 -04:00
Gabriel Huau
5318f18d2c x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:08 -06:00
Andrew Bradford
afbbd413a3 x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
5c564226fc x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
f2653e8dd9 x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
683b09d783 x86: qemu: Create separate i440fx and q35 device trees
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
65cdd9be3e x86: coreboot: Fix cosmetic issues
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Bin Meng
d04e30b839 x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSP
FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Bin Meng
4be2f42bbc x86: qemu: Adjust VGA initialization
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.

Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id & device id pair.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:40 -06:00
Bin Meng
0fcb7acf67 x86: qemu: Enable legacy IDE I/O ports decode
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
cc7debc719 x86: qemu: Turn on legacy segments decode
By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Andrew Bradford
1dc03c2639 x86: fsp_support: Correct high mem comment typo
High mem starts at 4 GiB.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
67b24970ce x86: Do sanity test on pirq table before writing
If pirq_routing_table points to NULL, that means U-Boot fails to
generate the table before in create_pirq_routing_table(), so we
test it against NULL before actually writing it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
05b98ec346 x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
9c7dea602e x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
9c4f541237 x86: qemu: Add graphics support
It turns out that QEMU x86 emulated graphic card has a built-in
option ROM which can be run perfectly with native mode by U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Bin Meng
6bde2dc5e2 x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video Kconfig
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them depend on VIDEO_VESA driver. Some cosmetic fixes are
applied to the Kconfig help text as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Bin Meng
99a309f323 x86: Make QEMU the default vendor
Now that we have QEMU support, make it the default vendor in the
'make menuconfig' screen.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Bin Meng
a65b25d148 x86: Support QEMU x86 targets
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
   https://patchwork.ozlabs.org/patch/479745/
2015-06-04 02:39:38 -06:00
Simon Glass
281239ad9d x86: Enable multi-core init for Minnowboard MAX
Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This
enables multi-core support in Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:52 -06:00
Simon Glass
ede9709316 x86: Add a CPU driver for baytrail
This driver supports multi-core init and sets up the CPU frequencies
correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:50 -06:00
Simon Glass
bcb0c61e1a x86: Allow CPUs to be set up after relocation
This permits init of additional CPU cores after relocation and when driver
model is ready.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:48 -06:00
Simon Glass
86196c65ac x86: Add functions to set and clear bits on MSRs
Since we do these sorts of operations a lot, it is useful to have a simpler
API, similar to clrsetbits_le32().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:46 -06:00
Simon Glass
45b5a37836 x86: Add multi-processor init
Most modern x86 CPUs include more than one CPU core. The OS normally requires
that these 'Application Processors' (APs) be brought up by the boot loader.
Add the required support to U-Boot to init additional APs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:38 -06:00
Simon Glass
6f41e0e7bc x86: Provide access to the IDT
Add a function to return the address of the Interrupt Descriptor Table.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
52845296be x86: Store the GDT pointer in global_data
When we start up additional CPUs we want them to use the same Global
Descriptor Table. Store the address of this in global_data so we can
reference it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
837a136fc7 x86: Add an mfence macro
Provide access to this x86 instruction from C code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
1a06d2a310 x86: Add defines for fixed MTRRs
Add MSR numbers for the fixed MTRRs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
b551173b73 x86: Add atomic operations
Add a subset of this header file from Linux 4.0 to support atomic operations
in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:33 -06:00
Simon Glass
6388e35725 x86: Add support for the Simple Firmware Interface (SFI)
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:33 -06:00
Simon Glass
9a7d700cca x86: Disable -Werror
This is annoying during development and serves no useful purpose since
warnings are clearly displayed now that we are using Kbuild. Remove this
option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
4051386107 x86: Remove unwanted MMC debugging
This printf() should not have made it into the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
410b10f1e3 x86: fsp: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
ebebf05976 x86: quark: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
5021c81faa x86: ivybridge: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
ff6a8f3c06 x86: Implement reset_cpu() correctly for modern CPUs
The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.

We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power cycle.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:31 -06:00
Simon Glass
87f4cd3a30 x86: link: Add PCH driver to support SPI Flash
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Gabriel Huau
8ddb8cfb1a x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
cc4c8aca1d x86: Correct the typo in write_tables()
It should be #ifdef instead of #if.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
3e4522279d x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/Kconfig
Since all x86 boards have been converted to use DM_SPI and
DM_SPI_FLASH, move them to arch/Kconfig x86 section.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
d99b901e74 x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmetics
Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
fix the indention of its help text.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
029194a3c4 x86: Kconfig: Move platform options forward
Move platform-specific options under in arch/x86/Kconfig forward right
after the board-specific options but before any architecture-specific
options. When it comes to the same Kconfig option, board-specific one
takes take the highest precedence, then platform-specific one, and
finally architecture-specific one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
65c4ac0a83 x86: Kconfig: Divide the target selection to vendor/model
Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/<vendor>/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
f82a7840f1 x86: quark: Turn on legacy segments decode
By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
283a08e52a x86: Check PIRQ routing table sanity in the F segment
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Gabriel Huau
8827227889 x86: minnowmax: add GPIO banks in the device tree
There are 6 banks:
    4 banks for CORE: available in S0 mode
    2 banks for SUS (Suspend): available in S0-S5 mode

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Gabriel Huau
4a34e4b86f x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
afbf1404c1 x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
b5b6b01960 x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).

We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
5e2400e8f8 x86: Write configuration tables in last_stage_init()
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
e3e7fa2cd1 x86: Add a function to assign IRQ numbers to PCI device
Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its interrupt working under PIC mode after OS boots up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
54c6001bba x86: Install a default e820 table in the __weak install_e820_map()
Create a default e820 table with 3 entries which is enough to boot
a Linux kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
24ff8e70e1 x86: Clean up arch/x86/include/asm/e820.h
There are lots of unused codes defined in e820.h, clean it up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
0a9bb489bf x86: Add alias for SPI node in the board dts
Since Intel ICH SPI driver has been converted to driver model, we need
add an alias for SPI node in the board dts files otherwise SPI flash
won't be detected due to 'invalid bus' error.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
19268834fb x86: Set serial port IRQ for SMSC LPC47M
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
9704f23b00 x86: queensbay: Avoid using PCH prefix
The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and Topcliff IOH chipset. For accuracy,
avoid using PCH prefix in the macro.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
5098d73e86 x86: Remove the old VGA driver
CONFIG_VIDEO_VGA is no longer needed thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Simon Glass
8156345dfe sandbox: Move CONFIG_SYS_VSNPRINTF to Kconfig
Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:37 -06:00
Simon Glass
ee2b24340f Kconfig: Move CONFIG_BOOTSTAGE to Kconfig
Move CONFIG_BOOT_STAGE and its associated options to Kconfig. Adjust
existing users and code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:37 -06:00
Masahiro Yamada
58d423b88e dm: select CONFIG_DM* options
As mentioned in the previous commit, adding default values in each
Kconfig causes problems because it does not co-exist with the
"depends on" syntax.  (Please note this is not a bug of Kconfig.)
We should not do so unless we have a special reason.  Actually,
for CONFIG_DM*, we have no good reason to do so.

Generally, CONFIG_DM is not a user-configurable option.  Once we
convert a driver into Driver Model, the board only works with Driver
Model, i.e. CONFIG_DM must be always enabled for that board.
So, using "select DM" is more suitable rather than allowing users to
modify it.  Another good thing is, Kconfig warns unmet dependencies
for "select" syntax, so we easily notice bugs.

Actually, CONFIG_DM and other related options have been added
without consistency: some into arch/*/Kconfig, some into
board/*/Kconfig, and some into configs/*_defconfig.

This commit prefers "select" and cleans up the following issues.

[1] Never use "CONFIG_DM=n" in defconfig files

It is really rare to add "CONFIG_FOO=n" to disable CONFIG options.
It is more common to use "# CONFIG_FOO is not set".  But here, we
do not even have to do it.
Less than half of OMAP3 boards have been converted to Driver Model.
Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is
weird.  Instead, add "select DM" only to appropriate boards, which
eventually eliminates "CONFIG_DM=n", etc.

[2] Delete redundant CONFIGs

Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again
in configs/sandbox_defconfig.
Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and
defines it also in omap3_beagle_defconfig and devkit8000_defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-18 11:11:30 -06:00
Simon Glass
90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
a274e9cac5 dm: x86: Add a uclass for an Low Pin Count (LPC) device
On x86 systems this device is commonly used to provide legacy port access.
It is sort-of a replacement for the old ISA bus.

Add a uclass for this, and allow it to have child devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
452f548753 dm: x86: Add a uclass for a Platform Controller Hub
Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.

The device can have children, so make it scan the device tree for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
ba4575626e dm: x86: spi: Convert ICH SPI driver to driver model
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00