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https://github.com/AsahiLinux/u-boot
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x86: Clean up lapic codes
This commit cleans up the lapic codes: - Delete arch/x86/include/asm/lapic_def.h, and move register and bit defines into arch/x86/include/asm/lapic.h - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic() - Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and CONFIG_AP_IN_SIPI_WAIT - Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as it is not apic related and only used by ivybridge - Fix coding convention issues Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
Simon Glass
parent
61788e468e
commit
63d54a6705
5 changed files with 103 additions and 183 deletions
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@ -13,12 +13,12 @@
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#include <asm/acpi.h>
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#include <asm/cpu.h>
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#include <asm/lapic.h>
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#include <asm/lapic_def.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include <asm/speedstep.h>
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#include <asm/turbo.h>
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#include <asm/arch/bd82x6x.h>
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#include <asm/arch/model_206ax.h>
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static void enable_vmx(void)
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@ -8,50 +8,46 @@
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*/
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#include <common.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/post.h>
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void lapic_setup(void)
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{
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#if NEED_LAPIC == 1
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#ifdef CONFIG_SMP
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Setting up local apic: ");
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/* Enable the local apic */
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enable_lapic();
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/*
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* Set Task Priority to 'accept all'.
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*/
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/* Set Task Priority to 'accept all' */
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lapic_write_around(LAPIC_TASKPRI,
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lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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debug("apic_id: 0x%02lx, ", lapicid());
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#else /* !NEED_LLAPIC */
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#else /* !CONFIG_SMP */
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Disabling local apic: ");
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disable_lapic();
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#endif /* !NEED_LAPIC */
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#endif /* CONFIG_SMP */
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debug("done.\n");
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post_code(POST_LAPIC);
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}
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@ -16,7 +16,19 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
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const void *blob, int node);
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int bd82x6x_init(void);
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struct x86_cpu_priv;
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/**
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* struct x86_cpu_priv - Information about a single CPU
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*
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* @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
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* just a number representing the CPU core
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*
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* TODO: Move this to driver model once lifecycle is understood
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*/
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struct x86_cpu_priv {
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int apic_id;
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int start_err;
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};
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int model_206ax_init(struct x86_cpu_priv *cpu);
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#endif
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@ -1,5 +1,5 @@
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/*
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* From Coreboot file of same name
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* From coreboot file of same name
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*
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* Copyright (C) 2014 Google, Inc
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*
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@ -10,16 +10,61 @@
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#define _ARCH_ASM_LAPIC_H
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#include <asm/io.h>
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#include <asm/lapic_def.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/processor.h>
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/* See if I need to initialize the local apic */
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#if CONFIG_SMP || CONFIG_IOAPIC
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# define NEED_LAPIC 1
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#else
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# define NEED_LAPIC 0
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#endif
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#define LAPIC_DEFAULT_BASE 0xfee00000
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#define LAPIC_ID 0x020
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#define LAPIC_LVR 0x030
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#define LAPIC_TASKPRI 0x080
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#define LAPIC_TPRI_MASK 0xff
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#define LAPIC_RRR 0x0c0
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#define LAPIC_SPIV 0x0f0
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#define LAPIC_SPIV_ENABLE 0x100
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#define LAPIC_ICR 0x300
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#define LAPIC_DEST_SELF 0x40000
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#define LAPIC_DEST_ALLINC 0x80000
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#define LAPIC_DEST_ALLBUT 0xc0000
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#define LAPIC_ICR_RR_MASK 0x30000
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#define LAPIC_ICR_RR_INVALID 0x00000
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#define LAPIC_ICR_RR_INPROG 0x10000
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#define LAPIC_ICR_RR_VALID 0x20000
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#define LAPIC_INT_LEVELTRIG 0x08000
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#define LAPIC_INT_ASSERT 0x04000
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#define LAPIC_ICR_BUSY 0x01000
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#define LAPIC_DEST_LOGICAL 0x00800
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#define LAPIC_DM_FIXED 0x00000
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#define LAPIC_DM_LOWEST 0x00100
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#define LAPIC_DM_SMI 0x00200
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#define LAPIC_DM_REMRD 0x00300
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#define LAPIC_DM_NMI 0x00400
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#define LAPIC_DM_INIT 0x00500
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#define LAPIC_DM_STARTUP 0x00600
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#define LAPIC_DM_EXTINT 0x00700
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#define LAPIC_VECTOR_MASK 0x000ff
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#define LAPIC_ICR2 0x310
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#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xff)
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#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
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#define LAPIC_LVT0 0x350
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#define LAPIC_LVT1 0x360
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#define LAPIC_LVT_MASKED (1 << 16)
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#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
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#define LAPIC_LVT_REMOTE_IRR (1 << 14)
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#define LAPIC_INPUT_POLARITY (1 << 13)
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#define LAPIC_SEND_PENDING (1 << 12)
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#define LAPIC_LVT_RESERVED_1 (1 << 11)
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#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
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#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
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#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
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#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
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static inline __attribute__((always_inline))
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unsigned long lapic_read(unsigned long reg)
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@ -42,21 +87,21 @@ static inline void enable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(LAPIC_BASE_MSR);
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msr = msr_read(MSR_IA32_APICBASE);
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msr.hi &= 0xffffff00;
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msr.lo |= LAPIC_BASE_MSR_ENABLE;
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msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
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msr.lo |= MSR_IA32_APICBASE_ENABLE;
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msr.lo &= ~MSR_IA32_APICBASE_BASE;
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msr.lo |= LAPIC_DEFAULT_BASE;
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msr_write(LAPIC_BASE_MSR, msr);
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msr_write(MSR_IA32_APICBASE, msr);
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}
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static inline void disable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(LAPIC_BASE_MSR);
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msr.lo &= ~(1 << 11);
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msr_write(LAPIC_BASE_MSR, msr);
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msr = msr_read(MSR_IA32_APICBASE);
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msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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static inline __attribute__((always_inline)) unsigned long lapicid(void)
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@ -64,30 +109,24 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
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return lapic_read(LAPIC_ID) >> 24;
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}
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#if !CONFIG_AP_IN_SIPI_WAIT
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/* If we need to go back to sipi wait, we use the long non-inlined version of
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* this function in lapic_cpu_init.c
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*/
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static inline __attribute__((always_inline)) void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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#else
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void stop_this_cpu(void);
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#endif
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
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*
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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* but generally the primitive is invalid, *ptr is output argument.
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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@ -121,25 +160,19 @@ static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
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(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
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}
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#ifdef X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x, y) lapic_write((x), (y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
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#endif
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#define lapic_read_around(x) lapic_read(x)
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#define lapic_write_around(x, y) lapic_write_atomic((x), (y))
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static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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@ -150,30 +183,10 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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void lapic_setup(void);
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#if CONFIG_SMP
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struct device;
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int start_cpu(struct device *cpu);
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#endif /* CONFIG_SMP */
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int boot_cpu(void);
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/**
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* struct x86_cpu_priv - Information about a single CPU
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*
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* @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
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* just a number representing the CPU core
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*
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* TODO: Move this to driver model once lifecycle is understood
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*/
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struct x86_cpu_priv {
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int apic_id;
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int start_err;
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};
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#endif
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@ -1,101 +0,0 @@
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/*
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* Taken from the Coreboot file of the same name
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*
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* (C) Copyright 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_LAPIC_DEF_H
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#define _ASM_LAPIC_DEF_H
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#define LAPIC_BASE_MSR 0x1B
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#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
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#define LAPIC_BASE_MSR_ENABLE (1 << 11)
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#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
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#define LOCAL_APIC_ADDR 0xfee00000
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#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
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#define LAPIC_ID 0x020
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#define LAPIC_LVR 0x030
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#define LAPIC_TASKPRI 0x80
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#define LAPIC_TPRI_MASK 0xFF
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#define LAPIC_ARBID 0x090
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#define LAPIC_RRR 0x0C0
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#define LAPIC_SVR 0x0f0
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#define LAPIC_SPIV 0x0f0
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#define LAPIC_SPIV_ENABLE 0x100
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#define LAPIC_ESR 0x280
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#define LAPIC_ESR_SEND_CS 0x00001
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#define LAPIC_ESR_RECV_CS 0x00002
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#define LAPIC_ESR_SEND_ACC 0x00004
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#define LAPIC_ESR_RECV_ACC 0x00008
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#define LAPIC_ESR_SENDILL 0x00020
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#define LAPIC_ESR_RECVILL 0x00040
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#define LAPIC_ESR_ILLREGA 0x00080
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#define LAPIC_ICR 0x300
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#define LAPIC_DEST_SELF 0x40000
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#define LAPIC_DEST_ALLINC 0x80000
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#define LAPIC_DEST_ALLBUT 0xC0000
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#define LAPIC_ICR_RR_MASK 0x30000
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#define LAPIC_ICR_RR_INVALID 0x00000
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#define LAPIC_ICR_RR_INPROG 0x10000
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#define LAPIC_ICR_RR_VALID 0x20000
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#define LAPIC_INT_LEVELTRIG 0x08000
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#define LAPIC_INT_ASSERT 0x04000
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#define LAPIC_ICR_BUSY 0x01000
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#define LAPIC_DEST_LOGICAL 0x00800
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#define LAPIC_DM_FIXED 0x00000
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#define LAPIC_DM_LOWEST 0x00100
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#define LAPIC_DM_SMI 0x00200
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#define LAPIC_DM_REMRD 0x00300
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#define LAPIC_DM_NMI 0x00400
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#define LAPIC_DM_INIT 0x00500
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#define LAPIC_DM_STARTUP 0x00600
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#define LAPIC_DM_EXTINT 0x00700
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#define LAPIC_VECTOR_MASK 0x000FF
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#define LAPIC_ICR2 0x310
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#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
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#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
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#define LAPIC_LVTT 0x320
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#define LAPIC_LVTPC 0x340
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#define LAPIC_LVT0 0x350
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#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18)
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#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
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#define SET_LAPIC_TIMER_BASE(x) (((x) << 18))
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#define LAPIC_TIMER_BASE_CLKIN 0x0
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#define LAPIC_TIMER_BASE_TMBASE 0x1
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#define LAPIC_TIMER_BASE_DIV 0x2
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#define LAPIC_LVT_TIMER_PERIODIC (1 << 17)
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#define LAPIC_LVT_MASKED (1 << 16)
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#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
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#define LAPIC_LVT_REMOTE_IRR (1 << 14)
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#define LAPIC_INPUT_POLARITY (1 << 13)
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#define LAPIC_SEND_PENDING (1 << 12)
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#define LAPIC_LVT_RESERVED_1 (1 << 11)
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#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
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#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
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#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
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#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
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#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
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#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8))
|
||||
#define LAPIC_MODE_FIXED 0x0
|
||||
#define LAPIC_MODE_NMI 0x4
|
||||
#define LAPIC_MODE_EXINT 0x7
|
||||
#define LAPIC_LVT1 0x360
|
||||
#define LAPIC_LVTERR 0x370
|
||||
#define LAPIC_TMICT 0x380
|
||||
#define LAPIC_TMCCT 0x390
|
||||
#define LAPIC_TDCR 0x3E0
|
||||
#define LAPIC_TDR_DIV_TMBASE (1 << 2)
|
||||
#define LAPIC_TDR_DIV_1 0xB
|
||||
#define LAPIC_TDR_DIV_2 0x0
|
||||
#define LAPIC_TDR_DIV_4 0x1
|
||||
#define LAPIC_TDR_DIV_8 0x2
|
||||
#define LAPIC_TDR_DIV_16 0x3
|
||||
#define LAPIC_TDR_DIV_32 0x8
|
||||
#define LAPIC_TDR_DIV_64 0x9
|
||||
#define LAPIC_TDR_DIV_128 0xA
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue