mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
Simon Glass
parent
3d23287828
commit
a2d73fdba6
3 changed files with 149 additions and 147 deletions
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@ -8,9 +8,116 @@
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/post.h>
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unsigned long lapic_read(unsigned long reg)
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{
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return readl(LAPIC_DEFAULT_BASE + reg);
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}
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
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*
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument.
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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: "=q" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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}
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return x;
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}
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void lapic_write(unsigned long reg, unsigned long v)
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{
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(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
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}
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void enable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_APICBASE);
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msr.hi &= 0xffffff00;
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msr.lo |= MSR_IA32_APICBASE_ENABLE;
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msr.lo &= ~MSR_IA32_APICBASE_BASE;
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msr.lo |= LAPIC_DEFAULT_BASE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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void disable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_APICBASE);
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msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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unsigned long lapicid(void)
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{
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return lapic_read(LAPIC_ID) >> 24;
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}
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static void lapic_wait_icr_idle(void)
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{
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do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
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}
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int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == LAPIC_ICR_RR_VALID) {
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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void lapic_setup(void)
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{
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#ifdef CONFIG_SMP
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@ -21,26 +128,26 @@ void lapic_setup(void)
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enable_lapic();
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/* Set Task Priority to 'accept all' */
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lapic_write_around(LAPIC_TASKPRI,
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lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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lapic_write(LAPIC_TASKPRI,
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lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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lapic_write(LAPIC_SPIV, (lapic_read(LAPIC_SPIV) &
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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lapic_write(LAPIC_LVT0, (lapic_read(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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lapic_write(LAPIC_LVT1, (lapic_read(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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debug("apic_id: 0x%02lx, ", lapicid());
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#else /* !CONFIG_SMP */
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@ -16,7 +16,9 @@
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#include <asm/interrupt.h>
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#include <asm/lapic.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include <asm/sipi.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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@ -59,6 +61,13 @@ static inline void release_barrier(atomic_t *b)
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atomic_set(b, 1);
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}
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static inline void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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/* Returns 1 if timeout waiting for APs. 0 if target APs found */
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static int wait_for_aps(atomic_t *val, int target, int total_delay,
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int delay_step)
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@ -317,9 +326,9 @@ static int start_aps(int ap_count, atomic_t *num_aps)
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}
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/* Send INIT IPI to all but self */
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_INIT);
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_INIT);
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debug("Waiting for 10ms after sending INIT.\n");
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mdelay(10);
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@ -334,9 +343,9 @@ static int start_aps(int ap_count, atomic_t *num_aps)
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}
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}
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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debug("Waiting for 1st SIPI to complete...");
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if (apic_wait_timeout(10000, 50)) {
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debug("timed out.\n");
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@ -359,9 +368,9 @@ static int start_aps(int ap_count, atomic_t *num_aps)
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}
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}
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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debug("Waiting for 2nd SIPI to complete...");
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if (apic_wait_timeout(10000, 50)) {
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debug("timed out.\n");
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@ -9,11 +9,6 @@
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#ifndef _ARCH_ASM_LAPIC_H
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#define _ARCH_ASM_LAPIC_H
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/processor.h>
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#define LAPIC_DEFAULT_BASE 0xfee00000
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#define LAPIC_ID 0x020
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@ -66,126 +61,17 @@
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#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
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#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
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static inline __attribute__((always_inline))
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unsigned long lapic_read(unsigned long reg)
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{
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return readl(LAPIC_DEFAULT_BASE + reg);
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}
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unsigned long lapic_read(unsigned long reg);
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static inline __attribute__((always_inline))
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void lapic_write(unsigned long reg, unsigned long val)
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{
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writel(val, LAPIC_DEFAULT_BASE + reg);
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}
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void lapic_write(unsigned long reg, unsigned long v);
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static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
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{
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do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
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}
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void enable_lapic(void);
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static inline void enable_lapic(void)
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{
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msr_t msr;
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void disable_lapic(void);
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msr = msr_read(MSR_IA32_APICBASE);
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msr.hi &= 0xffffff00;
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msr.lo |= MSR_IA32_APICBASE_ENABLE;
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msr.lo &= ~MSR_IA32_APICBASE_BASE;
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msr.lo |= LAPIC_DEFAULT_BASE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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unsigned long lapicid(void);
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static inline void disable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_APICBASE);
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msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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static inline __attribute__((always_inline)) unsigned long lapicid(void)
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{
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return lapic_read(LAPIC_ID) >> 24;
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}
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static inline __attribute__((always_inline)) void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
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*
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument.
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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: "=q" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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}
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return x;
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}
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static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
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{
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(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
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}
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#define lapic_read_around(x) lapic_read(x)
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#define lapic_write_around(x, y) lapic_write_atomic((x), (y))
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static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == LAPIC_ICR_RR_VALID) {
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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int lapic_remote_read(int apicid, int reg, unsigned long *pvalue);
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void lapic_setup(void);
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