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x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
Simon Glass
parent
b5b6b01960
commit
afbf1404c1
9 changed files with 442 additions and 4 deletions
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@ -5,5 +5,5 @@
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#
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obj-y += fsp_configs.o
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obj-y += tnc.o topcliff.o
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obj-y += irq.o tnc.o topcliff.o
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obj-$(CONFIG_PCI) += tnc_pci.o
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242
arch/x86/cpu/queensbay/irq.c
Normal file
242
arch/x86/cpu/queensbay/irq.c
Normal file
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@ -0,0 +1,242 @@
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/pirq_routing.h>
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#include <asm/arch/device.h>
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#include <asm/arch/tnc.h>
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#include <asm/arch/irq.h>
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static struct irq_routing_table *pirq_routing_table;
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bool pirq_check_irq_routed(int link, u8 irq)
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{
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u8 pirq;
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pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
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pirq &= 0xf;
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/* IRQ# 0/1/2/8/13 are reserved */
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if (pirq < 3 || pirq == 8 || pirq == 13)
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return false;
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return pirq == irq ? true : false;
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}
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int pirq_translate_link(int link)
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{
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return LINK_V2N(link);
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}
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void pirq_assign_irq(int link, u8 irq)
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{
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/* IRQ# 0/1/2/8/13 are reserved */
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if (irq < 3 || irq == 8 || irq == 13)
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return;
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x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
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}
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static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
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u8 device, u8 func, u8 pin, u8 pirq)
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{
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struct irq_info *slot = *slotp;
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slot->bus = bus;
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slot->devfn = (device << 3) | func;
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slot->irq[pin - 1].link = LINK_N2V(pirq);
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slot->irq[pin - 1].bitmap = PIRQ_BITMAP;
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(*entries)++;
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(*slotp)++;
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}
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/* PCIe port downstream INTx swizzle */
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static inline u8 pin_swizzle(u8 pin, int port)
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{
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return (pin + port) % 4;
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}
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__weak int board_fill_irq_info(struct irq_info *slot)
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{
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return 0;
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}
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static int create_pirq_routing_table(void)
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{
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struct irq_routing_table *rt;
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struct irq_info *slot;
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int irq_entries = 0;
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pci_dev_t tcf_bdf;
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u8 tcf_bus, bus;
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int i;
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rt = malloc(sizeof(struct irq_routing_table));
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if (!rt)
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return -ENOMEM;
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memset((char *)rt, 0, sizeof(struct irq_routing_table));
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/* Populate the PIRQ table fields */
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rt->signature = PIRQ_SIGNATURE;
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rt->version = PIRQ_VERSION;
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rt->rtr_bus = 0;
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rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC;
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rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
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rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
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slot = rt->slots;
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/*
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* Now fill in the irq_info entries in the PIRQ table
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*
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* We start from internal TunnelCreek PCI devices first, then
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* followed by all the 4 PCIe ports downstream devices, including
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* the Queensbay platform Topcliff chipset devices.
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*/
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fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV,
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TNC_IGD_FUNC, INTA, PIRQE);
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fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV,
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TNC_SDVO_FUNC, INTA, PIRQF);
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fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV,
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TNC_HDA_FUNC, INTA, PIRQG);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV,
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TNC_PCIE0_FUNC, INTA, PIRQE);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV,
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TNC_PCIE1_FUNC, INTA, PIRQF);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV,
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TNC_PCIE2_FUNC, INTA, PIRQG);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV,
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TNC_PCIE3_FUNC, INTA, PIRQH);
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/* Check which PCIe port the Topcliff chipset is connected to */
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tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0);
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tcf_bus = PCI_BUS(tcf_bdf);
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for (i = 0; i < 4; i++) {
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bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0),
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PCI_SECONDARY_BUS);
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if (bus == tcf_bus)
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break;
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}
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/* Fill in the Topcliff chipset devices' irq info */
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if (i < 4) {
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV,
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TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i));
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tcf_bus++;
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
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TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
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TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
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TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
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TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6,
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TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i));
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}
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/* Call board-specific routine to fill in add-in card's irq info */
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irq_entries += board_fill_irq_info(slot);
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rt->size = irq_entries * sizeof(struct irq_info) + 32;
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pirq_routing_table = rt;
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return 0;
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}
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void pirq_init(void)
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{
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struct tnc_rcba *rcba;
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u32 base;
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base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
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base &= ~MEM_BAR_EN;
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rcba = (struct tnc_rcba *)base;
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/* Make sure all internal PCI devices are using INTA */
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writel(INTA, &rcba->d02ip);
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writel(INTA, &rcba->d03ip);
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writel(INTA, &rcba->d27ip);
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writel(INTA, &rcba->d31ip);
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writel(INTA, &rcba->d23ip);
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writel(INTA, &rcba->d24ip);
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writel(INTA, &rcba->d25ip);
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writel(INTA, &rcba->d26ip);
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/*
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* Route TunnelCreek PCI device interrupt pin to PIRQ
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*
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* Since PCIe downstream ports received INTx are routed to PIRQ
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* A/B/C/D directly and not configurable, we route internal PCI
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* device's INTx to PIRQ E/F/G/H.
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*/
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writew(PIRQE, &rcba->d02ir);
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writew(PIRQF, &rcba->d03ir);
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writew(PIRQG, &rcba->d27ir);
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writew(PIRQH, &rcba->d31ir);
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writew(PIRQE, &rcba->d23ir);
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writew(PIRQF, &rcba->d24ir);
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writew(PIRQG, &rcba->d25ir);
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writew(PIRQH, &rcba->d26ir);
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if (create_pirq_routing_table()) {
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debug("Failed to create pirq routing table\n");
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} else {
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/* Route PIRQ */
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pirq_route_irqs(pirq_routing_table->slots,
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get_irq_slot_count(pirq_routing_table));
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}
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}
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u32 write_pirq_routing_table(u32 addr)
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{
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return copy_pirq_routing_table(addr, pirq_routing_table);
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}
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@ -8,7 +8,8 @@
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/arch/tnc.h>
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#include <asm/arch/device.h>
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#include <asm/arch/irq.h>
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#include <asm/fsp/fsp_support.h>
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#include <asm/processor.h>
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@ -43,3 +44,10 @@ int arch_cpu_init(void)
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return 0;
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}
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int arch_misc_init(void)
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{
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pirq_init();
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return 0;
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}
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94
arch/x86/include/asm/arch-queensbay/device.h
Normal file
94
arch/x86/include/asm/arch-queensbay/device.h
Normal file
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@ -0,0 +1,94 @@
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _QUEENSBAY_DEVICE_H_
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#define _QUEENSBAY_DEVICE_H_
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#include <pci.h>
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/* TunnelCreek PCI Devices */
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#define TNC_HOST_BRIDGE_DEV 0
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#define TNC_HOST_BRIDGE_FUNC 0
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#define TNC_IGD_DEV 2
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#define TNC_IGD_FUNC 0
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#define TNC_SDVO_DEV 3
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#define TNC_SDVO_FUNC 0
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#define TNC_PCIE0_DEV 23
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#define TNC_PCIE0_FUNC 0
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#define TNC_PCIE1_DEV 24
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#define TNC_PCIE1_FUNC 0
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#define TNC_PCIE2_DEV 25
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#define TNC_PCIE2_FUNC 0
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#define TNC_PCIE3_DEV 26
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#define TNC_PCIE3_FUNC 0
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#define TNC_HDA_DEV 27
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#define TNC_HDA_FUNC 0
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#define TNC_LPC_DEV 31
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#define TNC_LPC_FUNC 0
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#define TNC_HOST_BRIDGE \
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PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
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#define TNC_IGD \
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PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
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#define TNC_SDVO \
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PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
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#define TNC_PCIE0 \
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PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
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#define TNC_PCIE1 \
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PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
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#define TNC_PCIE2 \
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PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
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#define TNC_PCIE3 \
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PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
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#define TNC_HDA \
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PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
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#define TNC_LPC \
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PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
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/* Topcliff IOH PCI Devices */
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#define TCF_PCIE_PORT_DEV 0
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#define TCF_PCIE_PORT_FUNC 0
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#define TCF_DEV_0 0
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#define TCF_PKT_HUB_FUNC 0
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#define TCF_GBE_FUNC 1
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#define TCF_GPIO_FUNC 2
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#define TCF_DEV_2 2
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#define TCF_USB1_OHCI0_FUNC 0
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#define TCF_USB1_OHCI1_FUNC 1
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#define TCF_USB1_OHCI2_FUNC 2
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#define TCF_USB1_EHCI_FUNC 3
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#define TCF_USB_DEVICE_FUNC 4
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#define TCF_DEV_4 4
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#define TCF_SDIO0_FUNC 0
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#define TCF_SDIO1_FUNC 1
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#define TCF_DEV_6 6
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#define TCF_SATA_FUNC 0
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#define TCF_DEV_8 8
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#define TCF_USB2_OHCI0_FUNC 0
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#define TCF_USB2_OHCI1_FUNC 1
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#define TCF_USB2_OHCI2_FUNC 2
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#define TCF_USB2_EHCI_FUNC 3
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#define TCF_DEV_10 10
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#define TCF_DMA1_FUNC 0
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#define TCF_UART0_FUNC 1
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#define TCF_UART1_FUNC 2
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#define TCF_UART2_FUNC 3
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#define TCF_UART3_FUNC 4
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#define TCF_DEV_12 12
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#define TCF_DMA2_FUNC 0
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#define TCF_SPI_FUNC 1
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#define TCF_I2C_FUNC 2
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#define TCF_CAN_FUNC 3
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#define TCF_1588_FUNC 4
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#endif /* _QUEENSBAY_DEVICE_H_ */
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55
arch/x86/include/asm/arch-queensbay/irq.h
Normal file
55
arch/x86/include/asm/arch-queensbay/irq.h
Normal file
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@ -0,0 +1,55 @@
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ARCH_IRQ_H_
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#define _ARCH_IRQ_H_
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enum pci_int_pin {
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INTX,
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INTA,
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INTB,
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INTC,
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INTD
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};
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enum pirq_pin {
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PIRQA,
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PIRQB,
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PIRQC,
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PIRQD,
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PIRQE,
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PIRQF,
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PIRQG,
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PIRQH
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};
|
||||
|
||||
/* PIRQ link number and value conversion */
|
||||
#define LINK_V2N(link) (link - 0x60)
|
||||
#define LINK_N2V(link) (link + 0x60)
|
||||
|
||||
#define PIRQ_BITMAP 0xdee0
|
||||
|
||||
struct irq_info;
|
||||
|
||||
/**
|
||||
* board_fill_irq_info() - Board-specific irq_info fill routine
|
||||
*
|
||||
* This fills the irq_info table for any board-specific add-in cards.
|
||||
*
|
||||
* @slot: pointer to the struct irq_info that is to be filled in
|
||||
* @return: number of entries were written to the struct irq_info
|
||||
*/
|
||||
int board_fill_irq_info(struct irq_info *slot);
|
||||
|
||||
/**
|
||||
* pirq_init() - Initialize platform PIRQ routing
|
||||
*
|
||||
* This initializes the PIRQ routing on the platform and configures all PCI
|
||||
* devices' interrupt line register to a working IRQ number on the 8259 PIC.
|
||||
*/
|
||||
void pirq_init(void);
|
||||
|
||||
#endif /* _ARCH_IRQ_H_ */
|
||||
|
|
@ -7,8 +7,43 @@
|
|||
#ifndef _X86_ARCH_TNC_H_
|
||||
#define _X86_ARCH_TNC_H_
|
||||
|
||||
#include <pci.h>
|
||||
/* Memory BAR Enable */
|
||||
#define MEM_BAR_EN 0x00000001
|
||||
|
||||
#define TNC_LPC PCI_BDF(0, 31, 0)
|
||||
/* LPC PCI Configuration Registers */
|
||||
#define LPC_RCBA 0xf0
|
||||
|
||||
/* Root Complex Register Block */
|
||||
struct tnc_rcba {
|
||||
u32 rctl;
|
||||
u32 esd;
|
||||
u32 rsvd1[2];
|
||||
u32 hdd;
|
||||
u32 rsvd2;
|
||||
u32 hdba;
|
||||
u32 rsvd3[3129];
|
||||
u32 d31ip;
|
||||
u32 rsvd4[3];
|
||||
u32 d27ip;
|
||||
u32 rsvd5;
|
||||
u32 d02ip;
|
||||
u32 rsvd6;
|
||||
u32 d26ip;
|
||||
u32 d25ip;
|
||||
u32 d24ip;
|
||||
u32 d23ip;
|
||||
u32 d03ip;
|
||||
u32 rsvd7[3];
|
||||
u16 d31ir;
|
||||
u16 rsvd8[3];
|
||||
u16 d27ir;
|
||||
u16 d26ir;
|
||||
u16 d25ir;
|
||||
u16 d24ir;
|
||||
u16 d23ir;
|
||||
u16 rsvd9[7];
|
||||
u16 d02ir;
|
||||
u16 d03ir;
|
||||
};
|
||||
|
||||
#endif /* _X86_ARCH_TNC_H_ */
|
||||
|
|
|
|||
|
|
@ -53,6 +53,8 @@ int video_bios_init(void);
|
|||
void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
|
||||
void board_init_f_r(void) __attribute__ ((noreturn));
|
||||
|
||||
int arch_misc_init(void);
|
||||
|
||||
/* Read the time stamp counter */
|
||||
static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -4,3 +4,4 @@ CONFIG_TARGET_CROWNBAY=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_SEPARATE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
|
||||
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue