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https://github.com/AsahiLinux/u-boot
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x86: Add common SDRAM-init code
The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
7e4a6ae62c
commit
65dd1507e3
3 changed files with 327 additions and 0 deletions
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@ -13,3 +13,4 @@ obj-y += microcode.o
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endif
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obj-y += pch.o
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obj-$(CONFIG_HAVE_MRC) += report_platform.o
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obj-$(CONFIG_HAVE_MRC) += mrc.o
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271
arch/x86/cpu/intel_common/mrc.c
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271
arch/x86/cpu/intel_common/mrc.c
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@ -0,0 +1,271 @@
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/intel_regs.h>
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#include <asm/mrc_common.h>
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#include <asm/pch_common.h>
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#include <asm/post.h>
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#include <asm/arch/me.h>
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#include <asm/report_platform.h>
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static const char *const ecc_decoder[] = {
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"inactive",
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"active on IO",
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"disabled on IO",
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"active"
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};
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ulong mrc_common_board_get_usable_ram_top(ulong total_size)
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{
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struct memory_info *info = &gd->arch.meminfo;
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uintptr_t dest_addr = 0;
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struct memory_area *largest = NULL;
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int i;
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/* Find largest area of memory below 4GB */
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for (i = 0; i < info->num_areas; i++) {
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struct memory_area *area = &info->area[i];
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if (area->start >= 1ULL << 32)
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continue;
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if (!largest || area->size > largest->size)
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largest = area;
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}
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/* If no suitable area was found, return an error. */
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assert(largest);
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if (!largest || largest->size < (2 << 20))
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panic("No available memory found for relocation");
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dest_addr = largest->start + largest->size;
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return (ulong)dest_addr;
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}
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void mrc_common_dram_init_banksize(void)
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{
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struct memory_info *info = &gd->arch.meminfo;
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int num_banks;
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int i;
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for (i = 0, num_banks = 0; i < info->num_areas; i++) {
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struct memory_area *area = &info->area[i];
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if (area->start >= 1ULL << 32)
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continue;
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gd->bd->bi_dram[num_banks].start = area->start;
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gd->bd->bi_dram[num_banks].size = area->size;
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num_banks++;
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}
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}
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int mrc_add_memory_area(struct memory_info *info, uint64_t start,
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uint64_t end)
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{
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struct memory_area *ptr;
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if (info->num_areas == CONFIG_NR_DRAM_BANKS)
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return -ENOSPC;
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ptr = &info->area[info->num_areas];
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ptr->start = start;
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ptr->size = end - start;
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info->total_memory += ptr->size;
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if (ptr->start < (1ULL << 32))
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info->total_32bit_memory += ptr->size;
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debug("%d: memory %llx size %llx, total now %llx / %llx\n",
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info->num_areas, ptr->start, ptr->size,
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info->total_32bit_memory, info->total_memory);
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info->num_areas++;
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return 0;
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}
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = readl(MCHBAR_REG(0x5000));
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addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
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addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
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debug("memcfg DDR3 clock %d MHz\n",
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(readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
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debug("memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
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debug(" enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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debug(" rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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debug(" DIMMA %d MB width x%d %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? 16 : 8,
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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debug(" DIMMB %d MB width x%d %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 20) & 1) ? 16 : 8,
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap)
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{
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const void *blob = gd->fdt_blob;
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int spd_index;
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struct gpio_desc desc[4];
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int spd_node;
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int node;
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int ret;
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ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
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ARRAY_SIZE(desc), GPIOD_IS_IN);
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if (ret < 0) {
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debug("%s: gpio ret=%d\n", __func__, ret);
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return ret;
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}
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spd_index = dm_gpio_get_values_as_int(desc, ret);
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debug("spd index %d\n", spd_index);
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node = fdt_first_subnode(blob, dev->of_offset);
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if (node < 0)
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return -EINVAL;
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for (spd_node = fdt_first_subnode(blob, node);
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spd_node > 0;
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spd_node = fdt_next_subnode(blob, spd_node)) {
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int len;
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if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
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continue;
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*spd_datap = fdt_getprop(blob, spd_node, "data", &len);
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if (len < size) {
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printf("Missing SPD data\n");
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return -EINVAL;
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}
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debug("Using SDRAM SPD data for '%s'\n",
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fdt_get_name(blob, spd_node, NULL));
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return 0;
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}
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printf("No SPD data found for index %d\n", spd_index);
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return -ENOENT;
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}
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asmlinkage void sdram_console_tx_byte(unsigned char byte)
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{
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#ifdef DEBUG
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putc(byte);
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#endif
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}
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/**
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* Find the PEI executable in the ROM and execute it.
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*
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* @me_dev: Management Engine device
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* @pei_data: configuration data for UEFI PEI reference code
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*/
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static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
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void *pei_data, bool use_asm_linkage)
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{
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unsigned version;
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const char *data;
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report_platform_info(dev);
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debug("Starting UEFI PEI System Agent\n");
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debug("PEI data at %p:\n", pei_data);
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data = (char *)CONFIG_X86_MRC_ADDR;
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if (data) {
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int rv;
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ulong start;
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debug("Calling MRC at %p\n", data);
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post_code(POST_PRE_MRC);
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start = get_timer(0);
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if (use_asm_linkage) {
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asmlinkage int (*func)(void *);
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func = (asmlinkage int (*)(void *))data;
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rv = func(pei_data);
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} else {
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int (*func)(void *);
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func = (int (*)(void *))data;
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rv = func(pei_data);
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}
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post_code(POST_MRC);
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if (rv) {
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switch (rv) {
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case -1:
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printf("PEI version mismatch.\n");
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break;
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case -2:
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printf("Invalid memory frequency.\n");
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break;
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default:
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printf("MRC returned %x.\n", rv);
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}
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printf("Nonzero MRC return value.\n");
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return -EFAULT;
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}
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debug("MRC execution time %lu ms\n", get_timer(start));
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} else {
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printf("UEFI PEI System Agent not found.\n");
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return -ENOSYS;
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}
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version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION));
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debug("System Agent Version %d.%d.%d Build %d\n",
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version >> 24 , (version >> 16) & 0xff,
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(version >> 8) & 0xff, version & 0xff);
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#if CONFIG_USBDEBUG
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/* mrc.bin reconfigures USB, so reinit it to have debug */
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early_usbdebug_init();
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#endif
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return 0;
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}
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int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
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{
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struct udevice *me_dev;
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int ret;
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ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
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if (ret)
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return ret;
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ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
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if (ret)
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return ret;
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quick_ram_check();
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post_code(POST_DRAM);
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report_memory_config();
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return 0;
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}
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55
arch/x86/include/asm/mrc_common.h
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55
arch/x86/include/asm/mrc_common.h
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_MRC_COMMON_H
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#define __ASM_MRC_COMMON_H
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#include <linux/linkage.h>
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/**
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* mrc_common_init() - Set up SDRAM
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*
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* This calls the memory reference code (MRC) to set up SDRAM
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*
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* @dev: Northbridge device
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* @pei_data: Platform-specific data required by the MRC
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* @use_asm_linkage: true if the call to MRC requires asmlinkage, false if it
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* uses normal U-Boot calling
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* @return 0 if OK, -ve on error
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*/
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int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage);
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asmlinkage void sdram_console_tx_byte(unsigned char byte);
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int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap);
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void report_memory_config(void);
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/**
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* mrc_add_memory_area() - Add a new usable memory area to our list
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*
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* Note: @start and @end must not span the first 4GB boundary
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*
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* @info: Place to store memory info
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* @start: Start of this memory area
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* @end: End of this memory area + 1
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*/
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int mrc_add_memory_area(struct memory_info *info, uint64_t start,
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uint64_t end);
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/*
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* This function looks for the highest region of memory lower than 4GB which
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* has enough space for U-Boot where U-Boot is aligned on a page boundary.
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* It overrides the default implementation found elsewhere which simply
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* picks the end of ram, wherever that may be. The location of the stack,
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* the relocation address, and how far U-Boot is moved by relocation are
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* set in the global data structure.
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*/
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ulong mrc_common_board_get_usable_ram_top(ulong total_size);
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void mrc_common_dram_init_banksize(void);
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#endif
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