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x86: qemu: Move chipset-specific codes from pci.c to qemu.c
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
parent
20cbafa6fa
commit
487485956b
3 changed files with 84 additions and 72 deletions
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@ -6,14 +6,9 @@
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/arch/device.h>
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#include <asm/arch/qemu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static bool i440fx;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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@ -50,72 +45,5 @@ void board_pci_setup_hose(struct pci_controller *hose)
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int board_pci_post_scan(struct pci_controller *hose)
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{
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u16 device, xbcs;
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int pam, i;
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
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i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
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pam = i440fx ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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if (i440fx) {
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/*
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* Enable legacy IDE I/O ports decode
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*
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* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
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* However Linux ata_piix driver does sanity check on these two
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* registers to see whether legacy ports decode is turned on.
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* This is to make Linux ata_piix driver happy.
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*/
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x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
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x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
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/* Enable I/O APIC */
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xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
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xbcs |= APIC_EN;
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x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
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} else {
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/* Configure PCIe ECAM base address */
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x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
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CONFIG_PCIE_ECAM_BASE | BAR_EN);
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}
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return 0;
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}
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#ifdef CONFIG_GENERATE_MP_TABLE
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int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
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{
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u8 irq;
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if (i440fx) {
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/*
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* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
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* connected to I/O APIC INTPIN#16-19. Instead they are routed
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* to an irq number controled by the PIRQ routing register.
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*/
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irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
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PCI_INTERRUPT_LINE);
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} else {
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/*
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* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
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* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
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*/
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irq = pirq < 8 ? pirq + 16 : pirq + 12;
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}
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return irq;
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}
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#endif
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@ -6,8 +6,58 @@
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#include <common.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/device.h>
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#include <asm/arch/qemu.h>
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static bool i440fx;
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static void qemu_chipset_init(void)
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{
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u16 device, xbcs;
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int pam, i;
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
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i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
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pam = i440fx ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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if (i440fx) {
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/*
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* Enable legacy IDE I/O ports decode
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*
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* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
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* However Linux ata_piix driver does sanity check on these two
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* registers to see whether legacy ports decode is turned on.
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* This is to make Linux ata_piix driver happy.
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*/
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x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
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x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
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/* Enable I/O APIC */
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xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
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xbcs |= APIC_EN;
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x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
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} else {
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/* Configure PCIe ECAM base address */
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x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
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CONFIG_PCIE_ECAM_BASE | BAR_EN);
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}
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}
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int arch_cpu_init(void)
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{
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@ -39,7 +89,39 @@ void reset_cpu(ulong addr)
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x86_full_reset();
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}
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int arch_early_init_r(void)
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{
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qemu_chipset_init();
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return 0;
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}
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int arch_misc_init(void)
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{
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return pirq_init();
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}
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#ifdef CONFIG_GENERATE_MP_TABLE
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int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
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{
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u8 irq;
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if (i440fx) {
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/*
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* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
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* connected to I/O APIC INTPIN#16-19. Instead they are routed
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* to an irq number controled by the PIRQ routing register.
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*/
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irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
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PCI_INTERRUPT_LINE);
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} else {
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/*
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* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
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* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
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*/
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irq = pirq < 8 ? pirq + 16 : pirq + 12;
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}
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return irq;
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}
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#endif
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@ -15,6 +15,7 @@
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_ARCH_MISC_INIT
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#define CONFIG_ARCH_EARLY_INIT_R
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#define CONFIG_PCI_MEM_BUS 0xc0000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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@ -28,6 +29,7 @@
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0xe000
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_PCI_PNP
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \
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