mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
x86: qemu: Move chipset-specific codes from pci.c to qemu.c
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
parent
20cbafa6fa
commit
487485956b
3 changed files with 84 additions and 72 deletions
|
|
@ -6,14 +6,9 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/arch/device.h>
|
||||
#include <asm/arch/qemu.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static bool i440fx;
|
||||
|
||||
void board_pci_setup_hose(struct pci_controller *hose)
|
||||
{
|
||||
hose->first_busno = 0;
|
||||
|
|
@ -50,72 +45,5 @@ void board_pci_setup_hose(struct pci_controller *hose)
|
|||
|
||||
int board_pci_post_scan(struct pci_controller *hose)
|
||||
{
|
||||
u16 device, xbcs;
|
||||
int pam, i;
|
||||
|
||||
/*
|
||||
* i440FX and Q35 chipset have different PAM register offset, but with
|
||||
* the same bitfield layout. Here we determine the offset based on its
|
||||
* PCI device ID.
|
||||
*/
|
||||
device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
|
||||
i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
|
||||
pam = i440fx ? I440FX_PAM : Q35_PAM;
|
||||
|
||||
/*
|
||||
* Initialize Programmable Attribute Map (PAM) Registers
|
||||
*
|
||||
* Configure legacy segments C/D/E/F to system RAM
|
||||
*/
|
||||
for (i = 0; i < PAM_NUM; i++)
|
||||
x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
|
||||
|
||||
if (i440fx) {
|
||||
/*
|
||||
* Enable legacy IDE I/O ports decode
|
||||
*
|
||||
* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
|
||||
* However Linux ata_piix driver does sanity check on these two
|
||||
* registers to see whether legacy ports decode is turned on.
|
||||
* This is to make Linux ata_piix driver happy.
|
||||
*/
|
||||
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
|
||||
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
|
||||
|
||||
/* Enable I/O APIC */
|
||||
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
|
||||
xbcs |= APIC_EN;
|
||||
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
|
||||
} else {
|
||||
/* Configure PCIe ECAM base address */
|
||||
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
|
||||
CONFIG_PCIE_ECAM_BASE | BAR_EN);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERATE_MP_TABLE
|
||||
int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
|
||||
{
|
||||
u8 irq;
|
||||
|
||||
if (i440fx) {
|
||||
/*
|
||||
* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
|
||||
* connected to I/O APIC INTPIN#16-19. Instead they are routed
|
||||
* to an irq number controled by the PIRQ routing register.
|
||||
*/
|
||||
irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
|
||||
PCI_INTERRUPT_LINE);
|
||||
} else {
|
||||
/*
|
||||
* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
|
||||
* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
|
||||
*/
|
||||
irq = pirq < 8 ? pirq + 16 : pirq + 12;
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -6,8 +6,58 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/post.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/device.h>
|
||||
#include <asm/arch/qemu.h>
|
||||
|
||||
static bool i440fx;
|
||||
|
||||
static void qemu_chipset_init(void)
|
||||
{
|
||||
u16 device, xbcs;
|
||||
int pam, i;
|
||||
|
||||
/*
|
||||
* i440FX and Q35 chipset have different PAM register offset, but with
|
||||
* the same bitfield layout. Here we determine the offset based on its
|
||||
* PCI device ID.
|
||||
*/
|
||||
device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
|
||||
i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
|
||||
pam = i440fx ? I440FX_PAM : Q35_PAM;
|
||||
|
||||
/*
|
||||
* Initialize Programmable Attribute Map (PAM) Registers
|
||||
*
|
||||
* Configure legacy segments C/D/E/F to system RAM
|
||||
*/
|
||||
for (i = 0; i < PAM_NUM; i++)
|
||||
x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
|
||||
|
||||
if (i440fx) {
|
||||
/*
|
||||
* Enable legacy IDE I/O ports decode
|
||||
*
|
||||
* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
|
||||
* However Linux ata_piix driver does sanity check on these two
|
||||
* registers to see whether legacy ports decode is turned on.
|
||||
* This is to make Linux ata_piix driver happy.
|
||||
*/
|
||||
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
|
||||
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
|
||||
|
||||
/* Enable I/O APIC */
|
||||
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
|
||||
xbcs |= APIC_EN;
|
||||
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
|
||||
} else {
|
||||
/* Configure PCIe ECAM base address */
|
||||
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
|
||||
CONFIG_PCIE_ECAM_BASE | BAR_EN);
|
||||
}
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
|
|
@ -39,7 +89,39 @@ void reset_cpu(ulong addr)
|
|||
x86_full_reset();
|
||||
}
|
||||
|
||||
int arch_early_init_r(void)
|
||||
{
|
||||
qemu_chipset_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
return pirq_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERATE_MP_TABLE
|
||||
int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
|
||||
{
|
||||
u8 irq;
|
||||
|
||||
if (i440fx) {
|
||||
/*
|
||||
* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
|
||||
* connected to I/O APIC INTPIN#16-19. Instead they are routed
|
||||
* to an irq number controled by the PIRQ routing register.
|
||||
*/
|
||||
irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
|
||||
PCI_INTERRUPT_LINE);
|
||||
} else {
|
||||
/*
|
||||
* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
|
||||
* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
|
||||
*/
|
||||
irq = pirq < 8 ? pirq + 16 : pirq + 12;
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
|
||||
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
#define CONFIG_ARCH_EARLY_INIT_R
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0xc0000000
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
|
|
@ -28,6 +29,7 @@
|
|||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0xe000
|
||||
|
||||
#define CONFIG_SYS_EARLY_PCI_INIT
|
||||
#define CONFIG_PCI_PNP
|
||||
|
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \
|
||||
|
|
|
|||
Loading…
Reference in a new issue