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https://github.com/AsahiLinux/u-boot
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x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
This commit is contained in:
parent
8ba25eec86
commit
93f8a31186
14 changed files with 36 additions and 9 deletions
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@ -252,7 +252,6 @@ static void pch_rtc_init(pci_dev_t dev)
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/* TODO: Handle power failure */
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if (rtc_failed)
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printf("RTC power failed\n");
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rtc_init();
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}
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/* CougarPoint PCH Power Management init */
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@ -128,6 +128,14 @@ static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry)
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static int read_seed_from_cmos(struct pei_data *pei_data)
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{
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u16 c1, c2, checksum, seed_checksum;
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struct udevice *dev;
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int rcode = 0;
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rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
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if (rcode) {
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debug("Cannot find RTC: err=%d\n", rcode);
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return -ENODEV;
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}
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/*
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* Read scrambler seeds from CMOS RAM. We don't want to store them in
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@ -135,11 +143,11 @@ static int read_seed_from_cmos(struct pei_data *pei_data)
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* the flash too much. So we store these in CMOS and the large MRC
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* data in SPI flash.
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*/
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pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED);
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rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
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debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
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pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
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pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3);
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rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3);
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debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
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pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
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@ -150,8 +158,8 @@ static int read_seed_from_cmos(struct pei_data *pei_data)
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sizeof(u32));
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checksum = add_ip_checksums(sizeof(u32), c1, c2);
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seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK);
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seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
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seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
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seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
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if (checksum != seed_checksum) {
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debug("%s: invalid seed checksum\n", __func__);
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@ -223,13 +231,21 @@ static int build_mrc_data(struct mrc_data_container **datap)
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static int write_seeds_to_cmos(struct pei_data *pei_data)
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{
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u16 c1, c2, checksum;
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struct udevice *dev;
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int rcode = 0;
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rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
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if (rcode) {
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debug("Cannot find RTC: err=%d\n", rcode);
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return -ENODEV;
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}
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/* Save the MRC seed values to CMOS */
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rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
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rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
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debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
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pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
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rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
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rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
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debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
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pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
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@ -240,8 +256,8 @@ static int write_seeds_to_cmos(struct pei_data *pei_data)
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sizeof(u32));
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checksum = add_ip_checksums(sizeof(u32), c1, c2);
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rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
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rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
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rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
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rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
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return 0;
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}
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@ -2,6 +2,7 @@
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "Google Link";
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@ -2,6 +2,7 @@
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "Google Panther";
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@ -10,6 +10,7 @@
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/include/ "skeleton.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "Intel Galileo";
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@ -10,6 +10,7 @@
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "Intel Minnowboard Max";
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@ -10,6 +10,7 @@
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "QEMU x86 (I440FX)";
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@ -20,6 +20,7 @@
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "QEMU x86 (Q35)";
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@ -1,6 +1,7 @@
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/ {
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rtc {
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compatible = "motorola,mc146818";
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u-boot,dm-pre-reloc;
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reg = <0x70 2>;
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};
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};
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@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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CONFIG_DM_RTC=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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CONFIG_DM_RTC=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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@ -15,5 +15,6 @@ CONFIG_SPL_DISABLE_OF_CONTROL=y
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CONFIG_SPI_FLASH=y
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CONFIG_NETDEVICES=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_DM_RTC=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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@ -21,5 +21,6 @@ CONFIG_SPI_FLASH=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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CONFIG_DM_RTC=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_111=y
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CONFIG_DM_RTC=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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