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x86: ivybridge: Use the I2C driver to perform SMbus init
Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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parent
abb0b01e7a
commit
0c7645bde0
4 changed files with 35 additions and 36 deletions
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@ -120,41 +120,6 @@ int arch_cpu_init_dm(void)
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return 0;
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}
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static int enable_smbus(void)
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{
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pci_dev_t dev;
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uint16_t value;
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/* Set the SMBus device statically. */
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dev = PCI_BDF(0x0, 0x1f, 0x3);
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/* Check to make sure we've got the right device. */
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value = x86_pci_read_config16(dev, 0x0);
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if (value != 0x8086) {
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printf("SMBus controller not found\n");
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return -ENOSYS;
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}
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/* Set SMBus I/O base. */
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x86_pci_write_config32(dev, SMB_BASE,
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SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
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/* Set SMBus enable. */
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x86_pci_write_config8(dev, HOSTC, HST_EN);
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/* Set SMBus I/O space enable. */
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x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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/* Disable interrupt generation. */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* Clear any lingering errors, so transactions can run. */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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debug("SMBus controller enabled\n");
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return 0;
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}
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#define PCH_EHCI0_TEMP_BAR0 0xe8000000
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#define PCH_EHCI1_TEMP_BAR0 0xe8000400
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#define PCH_XHCI_TEMP_BAR0 0xe8001000
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@ -271,9 +236,11 @@ int print_cpuinfo(void)
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post_code(POST_EARLY_INIT);
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/* Enable SPD ROMs and DDR-III DRAM */
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ret = enable_smbus();
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ret = uclass_first_device(UCLASS_I2C, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == PEI_BOOT_RESUME)
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@ -283,6 +283,12 @@
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intel,sata-port-map = <1>;
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intel,sata-port0-gen3-tx = <0x00880a7f>;
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};
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smbus: smbus@1f,3 {
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compatible = "intel,ich-i2c";
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reg = <0x0000fb00 0 0 0 0>;
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u-boot,dm-pre-reloc;
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};
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};
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tpm {
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@ -1,5 +1,6 @@
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CONFIG_X86=y
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CONFIG_SYS_MALLOC_F_LEN=0x1800
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CONFIG_DM_I2C=y
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CONFIG_VENDOR_GOOGLE=y
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CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
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CONFIG_TARGET_CHROMEBOOK_LINK=y
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@ -20,6 +21,7 @@ CONFIG_CMD_TPM=y
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CONFIG_CMD_TPM_TEST=y
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CONFIG_OF_CONTROL=y
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CONFIG_CPU=y
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CONFIG_SYS_I2C_INTEL=y
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CONFIG_CMD_CROS_EC=y
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CONFIG_CROS_EC=y
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CONFIG_CROS_EC_LPC=y
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@ -9,6 +9,7 @@
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#include <dm.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/pch.h>
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int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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@ -27,6 +28,29 @@ int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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static int intel_i2c_probe(struct udevice *dev)
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{
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/*
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* So far this is just setup code for ivybridge SMbus. When we have
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* a full I2C driver this may need to be moved, generalised or made
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* dependant on a particular compatible string.
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*
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* Set SMBus I/O base
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*/
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dm_pci_write_config32(dev, SMB_BASE,
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SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
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/* Set SMBus enable. */
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dm_pci_write_config8(dev, HOSTC, HST_EN);
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/* Set SMBus I/O space enable. */
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dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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/* Disable interrupt generation. */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* Clear any lingering errors, so transactions can run. */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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debug("SMBus controller enabled\n");
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return 0;
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}
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