Commit graph

3326 commits

Author SHA1 Message Date
Ajay Kumar
a99cea0313 exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
2358fc8ed9 ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
45c480c9f6 video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
496f0e47e1 arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
e6756f6a2e arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
f0017175e3 exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Przemyslaw Marczak
73eca21128 odroid: kconfig: add odroid_defconfig
This config is valid for two devices:
- Odroid X2,
- Odroid U3.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:50 +09:00
Przemyslaw Marczak
a47fa7906c odroid: add odroid U3/X2 device tree description
This is a standard description for Odroid boards.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:50 +09:00
Przemyslaw Marczak
1fb4dab2a1 arm:reset: call the reset_misc() before the cpu reset
On an Odroid U3 board, the SOC is unable to reset the eMMC card
in the DWMMC mode by the cpu software reset. Manual reset of the card
by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function.
This is done by the reset_misc() function, which is called before reset_cpu().
The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>

Changes v4:
- arch/arm/reset: fix weak function attribute to proper style
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
Przemyslaw Marczak
4fb4d55a35 arch:exynos: boot mode: add get_boot_mode(), code cleanup
This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>

Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)

Changes v6:
- none

changes v7:
- change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
Przemyslaw Marczak
19f1b629bf exynos: pinmux: fix the gpio names for exynos4x12 mmc
This change fixes the bad gpio configuration for the exynos dwmmc.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Beomho Seo <beomho.seo@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
R Sricharan
681f785f7c ARM: DRA72: DDR3: Add emif settings for 666MHz clock
On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-09-04 13:12:49 -04:00
Khoronzhuk, Ivan
e6c9428a2f keystone2: use readl/writel functions instead of redefinition
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
1c4044ae4a ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0
The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but
by mistake, here is used shift instead of mask, so correct it.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-04 13:05:57 -04:00
Masahiro Yamada
a1263632bb mx6: tqma6: get board support back to Kconfig build system
The QS Systems TQMa6 board support was added by commit cb07d74e
and lost by commit e82abaeb.

Commit e82abaeb merged the IMX branch based on pre-Kconfig
and the mainline based on post-Kconfig, simply deleting
the boards.cfg file.  As a result, some boards added just before
the merge were lost.

This commit adds Kconfig, defconfig, MAINTAINERS for TQMa6 board
to work on the Kconfig infrastructure.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-08-31 12:01:04 -04:00
Masahiro Yamada
16e16fdde2 nomadik: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Nomadik board select menu to nomadik/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="nomadik").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30 21:22:00 -04:00
Masahiro Yamada
ef2b694c73 highbank: kconfig: move common settings
Move Highbank-specific settings to highbank/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rob Herring <robh@kernel.org>
2014-08-30 21:22:00 -04:00
Masahiro Yamada
22f2be7a12 orion5x: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Orion5x board select menu to orion5x/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="orion5x").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
c338f09e96 keystone: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Keystone board select menu to keystone/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="keystone").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
6c5431ac81 omap5: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP5 board select menu to omap5/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap5").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
d08215a5f1 omap4: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP4 board select menu to omap4/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap4").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
3cfbcb58d3 omap3: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP3 board select menu to omap3/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap3

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
3491ba6311 davinci: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Davinci board select menu to davinci/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="davinci").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
72df68cc6b exynos: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
47539e2317 kirkwood: kconfig: refactor Kconfig and defconfig
Becuase the board select menu in arch/arm/Kconfig is too big,
move the KirkWood board select menu to kirkwood/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="kirkwood").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Prafulla Wadasdkar <prafulla@marvell.com>
Cc: Luka Perkov <luka@openwrt.org>
2014-08-30 21:21:21 -04:00
Masahiro Yamada
ad17a81c06 versatile: kconfig: move common settings
Move Versatile-specific settings to versatile/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
f40b989863 rmobile: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Rmobile board select menu to rmobile/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="rmobile").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
ddd960e6c4 tegra: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.

Insert the Tegra SoC select menu between the arch select and the
board select.

 Architecture select
 |-- Tegra Platform (Tegra)
     |- Tegra SoC select (Tegra20 / 30 / 114 / 124)
        |- Board select

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:

  config TEGRA
          bool
          select SPL

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
44dcb4036b zynq: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Zynq board select menu to zynq/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="zynq").

Refactor board/xilinx/zynq/MAINTAINERS too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
2014-08-30 21:19:32 -04:00
Benoît Thébaudeau
eeadd3fe0f arm: Add missing .vectors section to linker scripts
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 07:46:41 -04:00
Tom Rini
3f1b6bebe0 arm64: Correct passing of Linux kernel args
The Documentation/arm64/booting.txt document says that pass in x1/x2/x3
as 0 as they are reserved for future use.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30 07:46:40 -04:00
Steve Rae
9dec5270be arm: convert Cygnus and NSP boards to Kconfig
Convert the bcm958300k and the bcm958622hr boards from "boards.cfg" to Kconfig.

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
da1f5ac295 arm: add Cygnus and NSP boards
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
562f01a2ba arm: bcmnsp: Add bcmnsp u-architecture
Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
7986688075 arm: bcmcygnus: Add bcmcygnus u-architecture
Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
c4b4500910 arm: iproc: Initial commit of iproc architecture code
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Stefan Agner
b0e31c7b66 arm: vf610: add NFC clock support
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30 07:46:40 -04:00
Stefan Agner
baa3134440 arm: vf610: add NFC pin mux
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30 07:46:39 -04:00
Marek Vasut
221a49d5bd ARM: Fix overflow in MMU setup
The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.

The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.

Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 07:46:39 -04:00
Jiandong Zheng
2d66a0fd58 arm: bcm281xx: Add Ethernet Clock support
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Sergey Kostanbaev
0bf62d7bc4 arm: ep9315: Add .vectors section to lds and remove obsolete lds
However ep9315 don't use
interrupt vectors during startup, but _startup symbol is used inside uboot to
calculate actual monitor size.

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
2014-08-30 07:46:38 -04:00
Pavel Machek
99b97106f3 socfpga: initialize designware ethernet
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-30 07:46:38 -04:00
Chin Liang See
3ab019e1dc socfpga: Fix SOCFPGA build error for Altera dev kit
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2014-08-29 15:50:54 -04:00
Pavel Machek
51fb455f82 socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.

This fixes structure to match hardware.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29 15:50:50 -04:00
Christian Riesch
db993fc8ec arm: include config.h in arch/arm/lib/vectors.S
config.h is required for CONFIG_SYS_DV_NOR_BOOT_CFG.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
2014-08-29 15:50:43 -04:00
Jeroen Hofstee
8863aa5c98 ARM:asm:io.h use static inline
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-29 15:50:43 -04:00
Tom Rini
6defdc0b55 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-08-29 13:47:42 -04:00
Tom Rini
7f14fb20f8 Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2014-08-29 11:07:35 -04:00
Tom Rini
5ddc329341 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2014-08-29 11:07:10 -04:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
Tom Rini
6af857c50d Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2014-08-29 11:06:26 -04:00
Tom Rini
3e1b36bd58 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-28 13:03:25 -04:00
Lokesh Vutla
7b92252370 ARM: DRA: Enable VTT regulator
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so it is safe enough to enable gpio
on all DRA7 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Sricharan R
f2a1b93b5c ARM: DRA7: Enable software leveling for dra7
Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Vitaly Andrianov
61f66fd5a8 keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-25 10:48:12 -04:00
pekon gupta
9352697aa0 board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.

As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
     SW5.1 (NAND_BOOTn) = OFF (logic-1)
     SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
     SW5.3 (eMMC_BOOTn) = OFF (logic-1)
     SW5.4 (QSPI_BOOTn) = OFF (logic-1)

And also set appropriate SYSBOOT configurations:
     SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
     SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
     SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
     SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
     SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
     SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
     SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
     SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */

Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
2014-08-25 10:48:12 -04:00
Masahiro Yamada
62d636aa2a omap: remove omap5912osk board support
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.

Tom suggested to remove this board.

Remove also omap1510_udc.c because this is the last board
to enable it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
2014-08-21 12:01:12 -04:00
Fabio Estevam
d145878d59 mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:15:23 +02:00
Fabio Estevam
5c045cddaa mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
Configure and enable the ethernet clock for mx6solox.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:14:09 +02:00
Fabio Estevam
080d72f233 mx6sxsabresd: Convert to the new Kconfig style
mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
style happened, so convert it now so that it can build again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:11:12 +02:00
Marek Vasut
b299ab7435 ARM: mx6: Handle the MMDCx_MDCTL COL field caprices
The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:22:52 +02:00
Marek Vasut
fcfdfdd58c ARM: mx6: Prevent overflow in DRAM size detection
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:21:57 +02:00
Marek Vasut
68968901e7 ARM: mx5: Fix CHSCCDR name
Fix the name of the CCM CHSCCDR register.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:19:20 +02:00
Gabriel Huau
a76df70908 mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20 11:52:54 +02:00
Michal Simek
ae2ee77f98 ARM: zynq: Remove spl.h
Do not specify own zynq specific SPL macros
because there is no need for that.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19 08:48:18 +02:00
Michal Simek
dbc31f6a20 ARM: zynq: Move ps7_init() out of spl.h
Prepare for spl.h removal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19 08:48:00 +02:00
Stefan Agner
24d4d422c1 ARM: tegra: add Colibri T30 board support
This adds board support for the Toradex Colibri T30 module.

Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:59:04 -07:00
Stephen Warren
aeb3fcb359 ARM: tegra: Use mem size from MC rather than ODMDATA
In at least Tegra124, the Tegra memory controller (MC) has a register
that controls the memory size. Read this to determine the memory size
rather than requiring this to be redundantly encoded into the ODMDATA.
This way, changes to the BCT (i.e. MC configuration) automatically
updated SW's view of the memory size, without requiring manual changes
to the ODMDATA.

Future work potentially required:
* Clip the memory size to architectural limits; U-Boot probably doesn't
  and won't support either LPAE or Tegra's "swiss cheese" memory layout,
  at least one of which would be required for >2GB RAM.
* Subtract out any carveout required by firmware on future SoCs.

Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:03 -07:00
Bryan Wu
df3443dfa4 ARM: tegra: Disable VPR
On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed).

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:02 -07:00
Stefano Babic
7e9291720d Update aristainetos board to Kconfig
aristainetos board was merged in u-boot-imx before
Kconfig was integrated, but it is not yet
mainline.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2014-08-13 09:30:41 +02:00
Siarhei Siamashka
bf4ca384ad sunxi: dram: Autodetect DDR3 bus width and density
In the case if the 'dram_para' struct does not specify the exact bus
width or chip density, just use a trial and error method to find a
usable configuration.

Because all the major bugs in the DRAM initialization sequence are
now hopefully fixed, it should be safe to re-initialize the DRAM
controller multiple times until we get it configured right. The
original Allwinner's boot0 bootloader also used a similar
autodetection trick.

The DDR3 spec contains the package pinout and addressing table for
different possible chip densities. It appears to be impossible to
distinguish between a single chip with 16 I/O data lines and a pair
of chips with 8 I/O data lines in the case if they provide the same
storage capacity. Because a single 16-bit chip has a higher density
than a pair of equivalent 8-bit chips, it has stricter refresh timings.
So in the case of doubt, we assume that 16-bit chips are used.
Additionally, only Allwinner A20 has all A0-A15 address lines and
can support densities up to 8192. The older Allwinner A10 and
Allwinner A13 can only support densities up to 4096.

We deliberately leave out DDR2, dual-rank configurations and the
special case of a 8-bit chip with density 8192. None of these
configurations seem to have been ever used in real devices. And no
new devices are likely to use these exotic configurations (because
only up to 2GB of RAM can be populated in any case).

This DRAM autodetection feature potentially allows to have a single
low performance fail-safe DDR3 initialiazation for a universal single
bootloader binary, which can be compatible with all Allwinner
A10/A13/A20 based devices (if the ifdefs are replaced with a runtime
SoC type detection).

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:34 +02:00
Siarhei Siamashka
935758b1d5 sunxi: dram: Derive write recovery delay from DRAM clock speed
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b5c71f5f9c sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such hardware actually exists.

As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
d755a5fb20 sunxi: dram: Configurable DQS gating window mode and delay
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.

So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.

Also we allow to enable the active DQS gating window mode, which
works better than the passive mode in practice. The DDR3 spec
says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
The DQS window has to be opened during preamble and closed during
postamble. In the passive window mode, the gating window is opened
and closed by just using the gating delay settings. And because
of the 1/4 cycle delay granularity, accurately hitting the 0.3
cycle long postamble is a bit tough. In the active window mode,
the gating window is auto-closing with the help of monitoring
the DQS line, which relaxes the gating delay accuracy requirements.

But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
e044daa33e sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
It is going to be useful in more than one place.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b8f7cb6ae3 sunxi: dram: Improve DQS gate data training error handling
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors ("found no result" and "found more than one
possible result"). Both are handled now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
013f2d7469 sunxi: dram: Use divisor P=1 for PLL5
This configures the PLL5P clock frequency to something in the ballpark
of 1GHz and allows more choices for MBUS and G2D clock frequency
selection (using their own divisors). In particular, it enables the use
of 2/3 clock speed ratio between MBUS and DRAM.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
1a9717cbb3 sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
speed. Allwinner A13 uses only 16-bit data bus width to connect the
external DRAM, which is halved compared to the 32-bit data bus of sun4i
(Allwinner A10), so it does not make much sense to clock a wider
internal bus at a very high speed. The Allwinner A13 manual specifies
300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer
sun7i hardware (Allwinner A20) has a full width 32-bit external memory
interface again, but still keeps the MBUS clock speed configurable.
Clocking MBUS too low inhibits memory performance and one has to find
the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors:
    http://linux-sunxi.org/A10_DRAM_Controller_Performance

This patch introduces a new 'mbus_clock' parameter for the 'dram_para'
struct and uses it as a desired MBUS clock speed target. If 'mbus_clock'
is not set, 300 MHz is used by default to match the older hardcoded
settings.

PLL5P and PLL6 are both evaluated as possible clock sources. Preferring
the one, which can provide higher clock frequency that is lower or
equal to the 'mbus_clock' target. In the case of a tie, PLL5P has
higher priority.

Attempting to set the MBUS clock speed has no effect on sun4i, but does
no harm either.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
5c18384dea sunxi: dram: Re-introduce the impedance calibration ond ODT
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:

    http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0

The new code supports both of the impedance configuration modes:
   - If the higher bits of the 'zq' parameter in the 'dram_para' struct
     are zero, then the lowest 8 bits are used as the ZPROG value, where
     two divisors encoded in lower and higher 4 bits. One divisor is
     used for calibrating the termination impedance, and another is used
     for the output impedance.
   - If bits 27:8 in the 'zq' parameters are non-zero, then they are
     used as the pre-defined ZDATA value instead of performing the ZQ
     calibration.

Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
94cd301988 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions
The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
cfc89b003b sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
7e40e1926a sunxi: dram: Remove broken impedance and ODT configuration code
We can safely remove it, because none of the currently supported
boards uses these features.

The existing implementation had multiple problems:
   - unnecessary code duplication between sun4i/sun5i/sun7i
   - ZQ calibration was never initiated explicitly, and could be
     only triggered by setting the highest bit in the 'zq' parameter
     in the 'dram_para' struct (this was never actually done for
     any of the known Allwinner devices).
   - even if the ZQ calibration could be started, no attempts were
     made to wait for its completion, or checking whether the
     default automatically initiated ZQ calibration is still
     in progress
   - ODT was only ever enabled on sun4i, but not on sun5i/sun7i

Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.

The impedance and ODT configuration code will be re-introdeced in
one of the next comits.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
f8e88b6837 sunxi: dram: Fix CKE delay handling for sun4i/sun5i
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.

The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i hardware (even the default register value
0x00c80064 is identical). Except that the counter is ticking a bit
slower on sun7i (3 DRAM clock cycles instead of 2), resulting in
longer actual delays for the same settings.

This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i
SoC variants and not just for sun7i alone. Also an explicit udelay(500)
is added immediately after DDR3 reset for extra safety. This is a
duplicated functionality. But since we don't have perfect documentation,
it may be reasonable to play safe. Half a millisecond boot time increase
is not that significant. Boot time can be always optimized later.
Preferebly by the people, who have the hardware equipment to check the
actual signals on the RESET and CKE lines and verify all the timings.

The old code did not configure the SDR_IDCR register for sun4i/sun5i,
but performed the DDR3 reset very early for sun4i/sun5i. This resulted
in a larger time gap between the DDR3 reset and the DDR3 initialization
steps and reduced the chances of CKE delay timing violation to cause
real troubles.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
e626d2d446 sunxi: dram: Respect the DDR3 reset timing requirements
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.

This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
f257796773 sunxi: dram: Remove broken super-standby remnants
If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
this means that DRAM is currently in self-refresh mode and retaining the
old data. Since we have no idea what to do in this situation yet, just
set this register to 0 and initialize DRAM in the same way as on any
normal reboot (discarding whatever was stored there).

This part of code was apparently used by the Allwinner boot0 bootloader
to handle resume from the so-called super-standby mode. But this
particular code got somehow mangled on the way from the boot0 bootloader
to the u-boot-sunxi bootloader and has no chance of doing anything even
remotely sane. For example:
1. in the original boot0 code we had "mctl_write_w(SDR_DPCR,
   0x16510000)" (write to the register) and in the u-boot it now looks
   like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the
   register)
2. in the original boot0 code it was issuing three commands "0x12, 0x17,
   0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
   u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry,
   Self-Refresh entry, Refresh)

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
34759d74a3 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of this implementation is that the DQS gating window can be
successfully found for almost every DLL delay adjustment setup that
gets tried. Thus making it unable to see any real difference between
'good' and 'bad' settings.

Also this code was supposed to be only activated by setting the highest
bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board
dram configuration). But none of the linux-sunxi devices has ever used
it for real. Basically, this code is just a dead weight.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
maxin.john@enea.com
194c1ed400 emif.h: remove duplicated argument to |
Remove the duplicated argument to | in two places. Reported
by Coccinelle (http://coccinelle.lip6.fr/).

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:03 -04:00
Albert ARIBAUD
1899fac925 Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-08-09 16:48:34 +02:00
Peter Crosthwaite
fb8d876698 zynq: spl: Add vectors section to linker script
The vectors section contains the _start symbol which is used as the
program entry point. Add it to the linker script in same fashion as done
for regular u-boot. This allows for correct generation of an spl elf
with a non-zero entry point.

A similar change was applied to sunxi platform in
"sunxi: Fix u-boot-spl.lds to refer to .vectors"
(sha1: 9e5f80d823)

This also allows for placement of the vector table at the hivecs
location by setting the TEXT_BASE to 0xffff0000.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-08-08 11:27:29 +02:00
Fabio Estevam
9cd744ff11 mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED
According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of
register CCM_CIMR corresponds to bit 19 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
326454a88d mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definition
According to the Reference Manual the 'wb_per_at_lpm' field of register
CCM_CLPCR corresponds to bit 16 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
338c9da605 mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset
According to the Reference Manual the 'spdif0_clk_podf' field of register
CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset
definitions accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
2834490245 mx6: imx-regs: Remove unused 'omux' field from iomux struct
'omux' field is not used anywhere and such layout is not valid for mx6solox.

Instead of adding more ifdef's into the structure, let's simply remove this
unused 'omux' field.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-08 10:29:39 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Tom Rini
aa159e681e Merge http://git.denx.de/u-boot-dm 2014-08-04 10:16:27 -04:00
Simon Glass
76a1e584e1 arm: Support pre-relocation malloc()
Add support for re-relocation malloc() in arm's start-up code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-04 05:24:35 -06:00
Simon Glass
aae2aef9c8 arm: Set up global data before board_init_f()
At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f(). However it is
actually set up before this, it just isn't zeroed.

If we zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change (on arm32 only) to simplify the init process. I
don't have the ability to test aarch64 yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
2014-08-04 05:23:59 -06:00
Marek Vasut
dae0f5c644 mmc: s3c: Add SD driver
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 19:24:34 +03:00
Marek Vasut
7eca6b6327 arm: s3c: Unify the S3C24xx SDI structure
Unify the register structure so they can be easily used across all
of S3C24xx lineup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 19:24:23 +03:00
DrEagle
3fe3b4fb1c ARM: kirkwood: add mvsdio driver
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 18:44:56 +03:00
Marc Zyngier
d5db7024aa sunxi: HYP/non-sec: add sun7i PSCI backend
So far, only supporting the CPU_ON method.
Other functions can be added later.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:24 +02:00
Hans de Goede
fc70300136 sunxi: Add CONFIG_MACPWR option
On some boards the ethernet-phy needs to be powered up through a gpio,
add support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Roman Byshko
06cdd94077 sunxi: add defines to control USB Host clocks/resets
The commit adds three defines which will be used in
the EHCI driver to enable USB clock and assert
reset controllers of the corresponding PHYs.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Ian Campbell
a6e50a88d8 ahci: provide sunxi SATA driver using AHCI platform framework
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.

The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.

The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port.  This is added under a
suitable ifdef.

This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Masahiro Yamada
90f984e397 kconfig: delete redundant CONFIG_${ARCH} definition
CONFIG_${ARCH} is defined by Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
dd84058d24 kconfig: add board Kconfig and defconfig files
This commit adds:
 - arch/${ARCH}/Kconfig
    provide a menu to select target boards
 - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
    set CONFIG macros to the appropriate values for each board
 - configs/${TARGET_BOARD}_defconfig
    default setting of each board

(This commit was automatically generated by a conversion script
based on boards.cfg)

In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.

But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:01 -04:00
Tom Rini
362f16b1e9 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-07-29 09:41:35 -04:00
Marc Zyngier
9d195a5461 ARM: HYP/non-sec: remove MIDR check to validate CBAR
Having a form of whitelist to check if we know of a CPU core
and and obtain CBAR is a bit silly.

It doesn't scale (how about A12, A17, as well as other I don't know
about?), and is actually a property of the SoC, not the core.

So either it works and everybody is happy, or it doesn't and
the u-boot port to this SoC is providing the real address via
a configuration option.

The result of the above is that this code doesn't need to exist,
is thus forcefully removed.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:55 +02:00
Marc Zyngier
e771a3d538 ARM: HYP/non-sec/PSCI: emit DT nodes
Generate the PSCI node in the device tree.

Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:52 +02:00
Ma Haijun
e29607ed97 ARM: convert arch_fixup_memory_node to a generic FDT fixup function
Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.

[maz: collapsed 3 patches into one, rewrote commit message]

Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:49 +02:00
Marc Zyngier
38510a4b34 ARM: HYP/non-sec: add the option for a second-stage monitor
Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:26 +02:00
Marc Zyngier
ecf07a7930 ARM: HYP/non-sec: add generic ARMv7 PSCI code
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:18 +02:00
Marc Zyngier
f510aeae68 ARM: HYP/non-sec: allow relocation to secure RAM
The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.

This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
  before entering the payload
- performing an exception return from secure mode directly into
  the payload
- allowing the code to be dynamically relocated to secure RAM
  before switching to non-secure.

This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:09 +02:00
Marc Zyngier
bf433afd60 ARM: HYP/non-sec: add separate section for secure code
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.

Nothing is using it just yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:07:23 +02:00
Marc Zyngier
b726d22da9 ARM: add missing HYP mode constant
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.

Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:35 +02:00
Marc Zyngier
64fd44dcae ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:28 +02:00
Marc Zyngier
800c83522c ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:19 +02:00
Marc Zyngier
c19e0dd741 ARM: HYP/non-sec: move switch to non-sec to the last boot phase
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:05:59 +02:00
Albert ARIBAUD
b1cdd8baa1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-28 12:26:21 +02:00
Albert ARIBAUD
48b3ed217f Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2014-07-28 10:54:54 +02:00
Albert ARIBAUD
740f41d3cb Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-07-28 10:12:45 +02:00
pekon gupta
222a3113b4 ARM: omap: clean redundant PISMO_xx macros used in OMAP3
PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
  by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
  merging of common platform code in following commit
      commit a0a37183bd
      ARM: omap: merge GPMC initialization code for all platform

+-----------------+-----------------------------------------------------------+
| Macro           | Reason for removal                                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE                         |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE                      |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so     |
|                 | configuring GPMC chip-select for smallest allowable       |
|                 | segment (GPMC_SIZE_16M) is enough.                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of    |
|                 | 128MB (GPMC_SIZE_128M)                                    |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR      |  Unused Macros                                            |
| PISMO1_NAND     |                                                           |
| PISMO2_CS0      |                                                           |
| PISMO2_CS1      |                                                           |
| PISMO1_ONENAND  |                                                           |
| PISMO2_NAND_CS0 |                                                           |
| PISMO2_NAND_CS1 |                                                           |
| PISMO1_NOR_BASE |                                                           |
| PISMO1_NAND_BASE|                                                           |
| PISMO2_CS0_BASE |                                                           |
+-----------------+-----------------------------------------------------------+

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
pekon gupta
77cd89e755 ARM: omap: fix GPMC address-map size for NAND and NOR devices
Fixes commit a0a37183bd
    ARM: omap: merge GPMC initialization code for all platform

1) NAND device are not directly memory-mapped to CPU address-space, they are
 indirectly accessed via following GPMC registers:
 - GPMC_NAND_COMMAND_x
 - GPMC_NAND_ADDRESS_x
 - GPMC_NAND_DATA_x
 Therefore from CPU's point of view, NAND address-map can be limited to just
 above register addresses. But GPMC chip-select address-map can be configured
 in granularity of 16MB only.
 So this patch uses GPMC_SIZE_16M for all NAND devices.

2) NOR device are directly memory-mapped to CPU address-space, so its
 address-map size depends on actual addressable region in NOR FLASH device.
 So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
 size configuration.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
Rajendra Nayak
8c16dd6fa7 ARM: OMAP: Fix handling of errata i727
The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
a906847966 board: k2e-evm: add board support
This patch adds Keystone2 k2e_evm evaluation board support.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
1284246eb9 ARM: keystone2: spl: add K2E SoC support
Keystone2 K2E SoC has slightly different spl pll settings then
K2HK, so correct this.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
20187fd11c ARM: keystone2: add MSMC cache coherency support for K2E SOC
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
4dca7f0acc ARM: keystone2: clock: add K2E clock support
This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
5c76f78858 ARM: keystone2: add K2E SoC hardware definitions
This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
8dfc15f56c ARM: keystone: clock: move K2HK SoC dependent code in separate file
This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
3d31538625 k2hk: use common KS2_ prefix for all hardware definitions
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
7b26c1f608 keystone2: add possibility to turn off all dsps
By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
4984bce41f keystone2: move cpu_to_bus() to keystone.c
The SoC related common functions in board.c should be placed to
a common keystone.c arch file.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
35c547c2bc ARM: keystone2: keystone_nav: make it dependent on keystone driver
This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Hao Zhang
101eec50f0 keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
0b86858956 keystone: ddr3: add ddr3.h to hold ddr3 API
It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
04b7ce0773 ARM: keystone2: psc: use common PSC base
Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
6d3bbdb0e7 ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c
These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
fb2fcb798a ARM: omap: Fix GPMC init for OMAP3 platforms
Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Tested on TAO3530 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:09 -04:00
Tom Rini
c4f80f5003 am335x_evm / gumstix pepper: Correct DDR settings
As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers.  Upon further inspection these
had been touching reserved fields (and having no impact).  These came in
from historical bring-up code and can be discarded.  Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.

Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-By: Ash Charles <ashcharles@gmail.com>
2014-07-25 16:26:08 -04:00
Nobuhiro Iwamatsu
fafcfc5a98 arm: rmobile: Add support R8A7794
Renesas R8A7794 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Michal Simek
03606ff42e ARM: zynq: Show ECC status on the same line as DRAM size
Without this patch is DRAM size one line below DRAM:
which is not nice

Origin:
I2C:   ready
DRAM:  Memory: ECC disabled
1 GiB
MMC:   zynq_sdhci: 0

Fixed by this patch:
I2C:   ready
DRAM:  ECC disabled 1 GiB
MMC:   zynq_sdhci: 0

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-23 15:36:55 +02:00
Heiko Schocher
a0ae0091d7 i.MX6: add enable_spi_clk()
add enable_spi_clk(), so board code can enable spi clocks.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:42 +02:00
Heiko Schocher
aafe4020c1 i.MX6: define struct pwm_regs and PWMCR_* defines
add defines for pwm modul found on imx6.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Heiko Schocher
4a4d3a7db7 imx6: add gpr2 usb_otg_id iomux select control define
add IOMUXC_GPR1_USB_OTG_ID_OFFSET and IOMUXC_GPR1_USB_OTG_ID_SEL_MASK
define for the USB_OTG_ID_SEL bit.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
aeadf0655c mx6: Adjust the GPR offset for mx6solox
On mx6solox there is an additional 0x4000 offset for the GPR registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
0a11d6f29c mx6: Remove duplication of iomuxc structure
There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
registers.

The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.

So remove iomuxc_base_regs structure and use iomuxc instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
a3df99b50f mx6: soc: Do not apply the PFD erratum for mx6solox
The PFD issue is not present on mx6solox, so skip it in this case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Ian Campbell
7c48b01510 sunxi: use setbits_le32 to enable the DMA clock
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:25 +01:00
Ian Campbell
abce2c6220 sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:25 +01:00
Hans de Goede
ae5de5a19d sunxi: Fix reset hang on sun5i
Do the same as the Linux kernel does, this fixes the SoC hanging on reset
about 50% of the time.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:22 +01:00
Hans de Goede
6620377e4b sunxi: Add i2c support
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
2014-07-18 19:41:30 +01:00
Hans de Goede
0db2bbdc04 mvtwsi: convert to CONFIG_SYS_I2C framework
Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).

The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-07-16 19:56:24 +01:00
Stefano Babic
dab5e3469d Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
	boards.cfg
2014-07-16 08:51:30 +02:00
Tom Rini
84f24ac827 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-07-11 14:54:48 -04:00
Fabio Estevam
d95b6ab87c mx6: clock: Do not enable sata and ipu clocks
mx6sx does not have sata nor ipu blocks, so do not handle such clocks.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
f586040451 mx6sx: Add pin definitions
Add the pin definitions for mx6sx.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
05d54b827f mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family.

Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet

Add the initial support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Eric Nelson
e153333eeb i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10
The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB displays on Dual-Lite and Solo processors.

These settings now match the i.MX6 Dual and Quad core versions.

Note that this fixes a regression in commit b47abc3 and that
this is the second time we've had a regression on these two
pads (See commit e654ddf).

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2014-07-10 15:23:56 +02:00
Felipe Balbi
5ba95541b7 usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x
Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-07-09 22:11:51 +02:00
Tom Rini
22692ec0fb Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-07-09 09:21:51 -04:00
Fabio Estevam
157f45da91 mx6: soc: Update the comments of set_ldo_voltage()
Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.

Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.

Update the comments to align with the new set_ldo_voltage() implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-09 15:10:10 +02:00
Andre Renaud
2eb268f6fd MX6: Correct calculation of PLL_SYS
DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors

Signed-off-by: Andre Renaud <andre@bluewatersys.com>
2014-07-09 14:55:30 +02:00
Ian Campbell
799aff38df sunxi: Avoid unused variable warning.
Mark rc as __maybe_unused since it is infact unused on systems with neither
EMAC nor GMAC.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Tom Rini <trini@ti.com>
2014-07-08 07:45:06 +01:00
Alexey Ignatov
072b2d8872 kmake: include DTB section into u-boot.bin if CONFIG_OF_EMBED enabled
Fixes a bug when objcopy doesn't put .dtb.init.rodata section to resulting
u-boot.bin, so u-boot was unable to find embedded DTB.
2014-07-07 19:47:24 -04:00
Cooper Jr., Franklin
8038b497e7 am43xx: Tune the system to avoid DSS underflows
* This is done by limiting the ARM's bandwidth and setting DSS priority in
  the EMIF controller to ensure underflows do not occur.
2014-07-07 19:42:34 -04:00
Franklin S. Cooper Jr
2c95211167 am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
  non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
  different timings are required for alpha, beta and production boards.

Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
2014-07-07 19:42:34 -04:00
Jeroen Hofstee
878cae6b02 ARM: emif4: wait for CM_DLL_READYST to be set
The code intends for the CM_DLL_READYST to be set, but
actually polls till any bit is set since the logical
AND is used instead of the bitwise one is used. Fix it.

cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-07 19:42:33 -04:00
Tom Rini
6ee3d00d1d Merge branch 'master' of git://git.denx.de/u-boot-i2c 2014-07-07 10:10:52 -04:00
Hans de Goede
c26fb9db0e sunxi: Add emac glue, enable emac on the cubieboard
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:45 +01:00
Hans de Goede
f84269c5c0 sunxi: Add sun5i support
Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
boards.

The only differences compared to the already supported sun4i and sun7i
families are all in the DRAM controller initialization:

-Different hcpr values
-Different MBUS settings
-Some other small initialization changes

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
745325a97d sunxi: Add sun4i support
Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
and add the Cubieboard board which uses the A10 SoC.

Compared to sun7 only the DRAM controller is a bit different:
-Controller reset bits are inverted, but only for Rev. A
-Different hpcr values
-No MBUS on sun4i
-Various other initialization changes

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
c7e79dec85 sunxi: Implement reset_cpu
There is no way to reset the cpu, so use the watchdog for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
9e5f80d823 sunxi: Fix u-boot-spl.lds to refer to .vectors
Adjust the u-boot-spl.lds linker script to match the changes made in the
41623c91b0 "arm: move exception handling out
of start.S files" commit.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 17:41:13 +01:00
Chin Liang See
23f23f23d5 socfpga: Relocate arch common functions away from board
To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Detlev Zundel <dzu@denx.de>
2014-07-05 10:14:46 +02:00
Shaibal.Dutta
fe0d925299 arm: Fix armv8 compilation error
Fix following compilation error when CONFIG_ARM64 is defined

Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'

Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com>
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Darwin Rambo <drambo@broadcom.com>
2014-07-05 09:30:20 +02:00
Jeroen Hofstee
ed6c7f7f6e arm: spl: fix include guard
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-05 09:28:21 +02:00
Chin Liang See
dc4d4aa14b socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2014-07-05 00:27:27 +02:00
Chin Liang See
05b884b5cd socfpga: Adding DesignWare watchdog support
To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-07-05 00:24:18 +02:00
Sergey Kostanbaev
7237d22baa arm: ep9315: Return back Cirrus Logic EDB9315A board support
This patch returns back support for old ep93xx processors family

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
2014-07-04 23:45:48 +02:00
Jeroen Hofstee
fcfddfd504 ARM: cache_v7: use __weak
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.

cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@ti.com>
2014-07-04 19:57:22 +02:00
York Sun
f749db3a75 ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-07-04 19:48:41 +02:00
J. German Rivera
b940ca64b2 armv8/fsl-lsch3: Add support to load and start MC Firmware
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
2014-07-03 08:40:58 +02:00
York Sun
2f78eae506 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-07-03 08:40:51 +02:00
York Sun
22932ffc03 ARMv8: Adjust MMU setup
Make MMU function reusable. Platform code can setup its own MMU tables.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
2014-07-03 08:40:48 +02:00
J. German Rivera
0d031e046c Added 64-bit MMIO accessors for ARMv8
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
2014-07-03 08:40:31 +02:00
Darwin Rambo
261d27605c arm: Add support for semihosting for armv8 fastmodel targets.
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use semihosting to load the kernel/ramdisk/dtb. This eliminates the need
for a bootwrapper and produces a more realistic boot sequence with
virtual models.

Though the semihosting code is quite generic, support for armv7 in
fastmodel is less useful due to the wide range of available silicon
and the lack of a free armv7 fastmodel, so this change contains an
untested armv7 placeholder for the service trap opcode.

Please refer to doc/README.semihosting for a more detailed description
of semihosting and how it is used with the armv8 virtual platforms.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Cc: trini@ti.com
Cc: fenghua@phytium.com.cn
Cc: bhupesh.sharma@freescale.com
2014-07-03 08:35:45 +02:00
Stephen Warren
68049a082b i2c: tegra: use repeated start for reads
I2C read transactions are typically implemented as follows:

START(write) address REPEATED_START(read) data... STOP

However, Tegra's I2C driver currently implements reads as follows:

START(write) address STOP START(read) data... STOP

This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-07-03 06:29:19 +02:00
Albert ARIBAUD
304f936aea Merge remote-tracking branch 'u-boot-samsung/master'
Conflicts:
	boards.cfg

Conflict was trivial between goni maintainer change and
lager_nor removal.
2014-07-01 20:52:51 +02:00
Albert ARIBAUD
019b57cc1d Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2014-07-01 15:48:25 +02:00
Albert ARIBAUD
e99f30e105 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-01 15:11:18 +02:00
Albert ARIBAUD
d6694aff56 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-06-30 23:00:34 +02:00
Stefano Babic
5d2ad2bc33 vf610: fix build due to missing sys_proto.h
commit 67a04ab3ab
fix the build for MX25. The same error
happens for VF610 SOC.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-06-25 12:48:06 +02:00
Albert ARIBAUD
01a3647abd Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2014-06-25 10:40:23 +02:00
Albert ARIBAUD
ed1d98d801 Merge branch 'u-boot/master' into 'u-boot-arm/master' 2014-06-25 10:39:58 +02:00
Akshay Saraswat
8e4ab1d582 Exynos5420: Introduce support for the Peach-Pit board
While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit
line of devices, there could be other boards using the same chip, so a
common configuration file is being added (exynos5420.h) as well
as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi).

The peach board as declared in boards.cfg is a copy of smdk5420
declaration. The configuration files are similar, but define different
default device trees, console serial ports and prompts.

The device tree files for smdk5420 and peach-pit inherit from the same
common file.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-23 08:45:44 +09:00
Akshay Saraswat
eacf46d340 Exynos5420: Let macros be used for exynos5420
Macros defined in exynos5_setup.h specific to SMDK5420
are required for Peach-Pit too. Hence, replacing
CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these
macros for all the boards based on Exynos5420.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-23 08:45:44 +09:00
Simon Glass
8946034a31 tegra: dts: Bring in GPIO bindings from linux
These files are taken from Linux 3.14.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-06-20 11:56:33 -06:00
Simon Glass
5957ac2a9f Makefile: Support include files for .dts files
Linux supports this, and if we are to have compatible device tree files,
U-Boot should also.

Avoid giving the device tree files access to U-Boot's include/ directory.
Only include/dt-bindings is accessible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-06-20 11:55:03 -06:00
Simon Glass
ad827e1649 arm: Support iotrace feature
Support the iotrace feature for ARM, when enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-20 11:54:40 -06:00
Stefano Babic
734af242c2 OMAP: disable gpmc timeout safely for reenabling
gpmc timeout is disabled and the reset counter
is set to 0. However, if later a driver activates
the timeout setting the reset to a valid value,
the old reset value with zero is still valid
for the first access. In fact, the timeout block
loads the reset counter after a successful access.

Found on a am335x board with a FPGA connected
to the GPMC bus together with the NAND.
When the FPGA driver in kernel activates
the timeout, the system hangs at the first access
by the NAND driver.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-06-19 17:53:59 -04:00
Jeroen Hofstee
fd3f401bc1 omap3: board: trivial: add void for no args
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-06-19 17:53:58 -04:00
Felipe Balbi
9f1220a9ca cpu: armv7: am33x: ddr: write emif ref_ctrl_shadow register
Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-06-19 17:53:58 -04:00
Khoronzhuk, Ivan
909ea9aa26 ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.c
Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-06-19 17:53:58 -04:00
Khoronzhuk, Ivan
3e01ed00da mtd: nand: davinci: add header file for driver definitions
The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <trini@ti.com>
2014-06-19 17:53:58 -04:00
Ash Charles
2868a5dff3 omap: Don't enable GPMC CS0 with nothing attached
If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set
for GPMC on chip select #0---size is 0.  In this case, the GPMC
configuration should be reset but not enabled.  Enabling causes the
Gumstix DuoVero board to hang when entering Linux.

Signed-off-by: Ash Charles <ashcharles@gmail.com>
[trini: Switch to testing base as GPMC_SIZE_256M is 0x0]
Signed-off-by: Tom Rini <trini@ti.com>
2014-06-19 17:53:41 -04:00
Jeroen Hofstee
c42ff090e4 tegra20: display: fix checking of return value
The calling code seems a bit in doubt about the return
value of fdtdec_lookup_phandle. Since it returns a negative
value on error (and fdt_node_offset_by_phandle as well),
check for that.

cc: Wei Ni <wni@nvidia.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-06-19 09:18:05 -07:00
Stefano Babic
f2f07e8553 imx: correct HAB status for new chip TO
According to:

http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0

ENGR00287268 mx6: fix the secure boot issue on the new tapout chip
commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b

newer i.MX6 silicon revisions have an updated ROM and HAB API table.
Please see also:

i.MX Applications Processors Documentation
Engineering Bulletins
EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison

With this change the secure boot status is correctly displayed

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-06-17 17:45:09 +02:00
Fabio Estevam
bad40e089f mx6: Fix definition of IOMUXC_GPR12_DEVICE_TYPE_RC
mx6 reference manual incorrectly states that the DEVICE_TYPE field of
IOMUXC_GPR12 register should be configured as '0010' for setting the PCI
controller in RC mode. The correct value should be '0100' instead.

This also aligns with the same value used in the mx6 pci kernel driver.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-06-17 16:27:51 +02:00
Masahiro Yamada
a811db5a8c arm: zynq: fix a bug in Zynq linker script
Commit 41623c91 moved exception handlers to ".vectores" section
but it missed to adjust Zynq linker script.

Zynq boards hang up after relocation because "_start" symbol
does not point to the correct address and gd->relocaddr gets insane.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Tested-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-06-17 12:28:26 +02:00
Wu, Josh
d337a09c30 ARMv7: at91: enable ICache and DCache.
For at91 armv7 SoC (SAMA5D3x), only LCD and macb used DMA.
Now as the lcd and macb driver already support dcache. So we can
enable dcache now.

Also we can enable icache without any problem.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-06-14 18:07:03 +02:00
Akshay Saraswat
ed32522fe0 Exynos5420: DMC: Add software read leveling
Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:14 +09:00
Doug Anderson
c9334fcda9 DMC: exynos5420: Gate CLKM to when reading PHY_CON13
when CLKM is running.  If we stop CLKM when sampling it the glitches
all go away, so we'll do that as per Samsung suggestion.

We also check the "is it locked" bits of PHY_CON13 and loop until they
show the the value sampled actually represents a locked value.  It
doesn't appear that the glitching and "is it locked" are related, but
it seems wise to wait until the PHY tells us the value is good before
we use it.  In practice we will not loop more than a couple times (and
usually won't loop at all).

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:13 +09:00
Akshay Saraswat
aacdd79095 Exynos5420: Remove code for enabling read leveling
This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:13 +09:00
Akshay Saraswat
cfde7588d8 Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init
Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-13 17:05:13 +09:00
Minkyu Kang
7922a2d479 Revert "exynos: Enable PSHOLD in SPL"
This reverts commit eb0dd9986c.
2014-06-13 17:00:56 +09:00
Vasili Galka
7d89982b7a Remove ${objtree}/include/asm/proc/ link
mkconfig links ${objtree}/include/asm/proc/ to
${srctree}/arch/${arch}/include/asm/proc-armv/. This seems to be a
remnant from the past. Ever since its introduction in 2003 it is used
only in ARM build and always links to same place, so let's simplify
the code, remove it and reference directly where needed.

Successful MAKEALL for ARM and PowerPC verified on Linux.

Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-06-11 16:27:05 -04:00
Vasili Galka
4b9ca09399 cosmetic: Whitespace fix
Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-06-11 16:27:05 -04:00
Thomas Betker
73671dad49 Check run_command() return code properly
run_command() returns 0 for success, 1 for failure. Fix places which
assume that failure is indicated by a negative return code.

Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
2014-06-11 16:25:47 -04:00
Simon Glass
5cc16cbf25 am33xx/omap: Enable CONFIG_OF_CONTROL
Add support for device tree control and add device tree files for the
beaglebone black initially.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-11 16:25:46 -04:00
Simon Glass
7e4154a553 am33xx/omap: Allow cache enable for all Sitara/OMAP
Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined.
This speeds up the Beaglebone Black boot considerable.

(Tested only on Beaglebone Black with SD card boot)

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-11 16:25:39 -04:00
Masahiro Yamada
0a26e1d6c3 arm: fix a double-definition error of _start symbol
The symbol "_start" is defined twice in arch/arm/lib/vectors.S:
around line 48 and line 54.

If CONFIG_SYS_DV_NOR_BOOT_CFG is defined (as on calimain board),
build fails:

  arch/arm/lib/vectors.S: Assembler messages:
  arch/arm/lib/vectors.S:54: Error: symbol `_start' is already defined
  make[1]: *** [arch/arm/lib/vectors.o] Error 1
  make: *** [arch/arm/lib] Error 2

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-06-09 10:36:40 +02:00
Mark Rutland
b924d586d7 arm64: zero cntvoff_el2
Currently cntvoff_el2 is initialised with an arbitrary bag of bits
derived from the initial value of cnthctl_el2 on the current CPU. This is
somewhat odd and problematic as some of these bits are UNKNOWN at reset
and may differ across CPUs (which may cause an OS at EL1 to observe time
going backwards across CPUs).

This patch instead initialises cntvoff_el2 with xzr, giving the register
a consistent value of zero on all CPUs.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Tom Rini <trini@ti.com>
Acked-by: David.Feng <fenghua@phytium.com.cn>
2014-06-09 10:24:02 +02:00
Chao Fu
cb6d04d606 arm: vf610: Add QSPI support for VF610TWR
Add QSPI support for VF610TWR, such as clock and iomux.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
2014-06-09 09:18:15 +02:00
Alison Wang
9d2ca0984b arm: imx: Add two macros for VF610 in IOMUX_PAD structure
Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in
IOMUX_PAD structure.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
2014-06-09 09:18:12 +02:00
Tom Rini
55e8250bd3 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-06-08 07:58:41 -04:00
Albert ARIBAUD
5ed28948a3 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-06-08 09:14:19 +02:00
Tom Rini
64ce2fbd6c arm:am33xx: Add a scale_vcores() hook
Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher.  Add a similar hook to start with.

Signed-off-by: Tom Rini <trini@ti.com>
2014-06-06 17:46:16 -04:00
Hannes Petermaier
25b0a729aa arch-am33xx: Add defines for timer0-7
For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.

Also the 'Timer register bits' are expanded.

By the way we add defines for all timers within AM335x SoC.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
2014-06-06 17:46:15 -04:00
Lokesh Vutla
ccd2f8db81 ARM: AM43xx: Fix UART clocks enabling
After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-06-06 17:46:15 -04:00
Murali Karicheri
afee59cd49 keystone: init: enable UART1 to be able use it from kernel
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.

Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-06-06 17:46:14 -04:00
Tom Rini
196311dc72 arm:am33xx: Rework s_init and add board_early_init_f
With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared.  When SPL booting, this is handled by setting gd
to point to SRAM in s_init.  However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.

Signed-off-by: Tom Rini <trini@ti.com>
2014-06-06 17:46:14 -04:00
Tom Rini
87acf194a2 arm:am33xx: Make dram_init call sdram_init() in some contexts
We have two contexts for booting these platforms.  One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads.  The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL.  In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.

In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus).  In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.

Signed-off-by: Tom Rini <trini@ti.com>
2014-06-06 17:46:14 -04:00
Sourav Poddar
7a5f71bc40 am43xx_evm: Add qspiboot target
The ePOS EVM and EVM SK have QSPI as an option to boot.  Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices.  As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.

Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-06-06 17:46:12 -04:00
pekon gupta
68128e0a86 omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:07 -04:00
Stefano Babic
67a04ab3ab MX25: fix build due to missing sys_proto.h
THe mx25 arch does not have a sys_proto.h file.
Instead of creating a dummy file, the file
is not included for this SOC.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-06-06 10:58:47 +02:00
Tim Harvey
22452fd821 imx: sata: return failure if not IMX6Q/IMX6D
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return
instead of configuring the SATA clock and GPR13 registers.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:14:52 +02:00
Tim Harvey
5bf497e3fd imx: iomux: add macros to setup iomux for multiple SoC types
Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:07:26 +02:00
Tim Harvey
fe0f7f7842 mx6: add mmdc configuration for MX6Q/MX6DL
- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
  chip-specific data

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:07:26 +02:00
Tim Harvey
8d05b161fc mx6: add structs for mmdc and ddr iomux registers
Add memory-mapped structures for MMDC iomux and configuration. Note that whi
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
registers differ. This requires two sets of structures.

Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration registers that can be used to
configure the MMDC dynamically.

We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-06-06 10:07:25 +02:00
Tim Harvey
b07161c321 imx: add comments and remove unused struct fields
Add comment block for the imx_ddr_size function and remove the extra unused
fields from struct esd_mmdc_regs which are also not common between IMX53 and
IMX6.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-06-06 10:07:25 +02:00
Tim Harvey
887717dbb9 mx6: add boot device support for SPL
Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-06-06 10:07:25 +02:00
Masahiro Yamada
9f2ec3f543 spl: consolidate arch/arm/include/asm/arch-*/spl.h
arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.

But many of them just define BOOT_DEVICE_* macros.

Those macros are used in the "switch (boot_device) { ... }"
statement in common/spl/spl.c.

So they should not be archtecture specific, but be described as
a simpile enumeration.

This commit merges most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.

With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Bo Shen <voice.shen@atmel.com> [on sama5d3xek board for at91 part]
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stefano Babic <sbabic@denx.de> [applying Tim's i.MX6 patches]
Acked-by: Tom Rini <trini@ti.com>
2014-06-06 10:05:34 +02:00
Masahiro Yamada
ba8dd7755e kbuild: move cmd_mkimage to scripts/Makefile.lib
Because cmd_mkimage is used in various subdirectories,
it seems reasonable to define it in scripts/Makefile.lib.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-06-05 17:01:58 -04:00
Masahiro Yamada
2aff23cadf arm: fdt_control: fix a build error with CONFIG_OF_EMBED=y
The build fails if a non-generic ARM board is compiled
with CONFIG_OF_EMBED=y.

The correct symbol name for embedded FDT is not __dtb_db_begin,
but __dtb_dt_begin. (A typo introduced by commit 6ab6b2af)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-06-05 14:38:38 -04:00
Stephen Warren
e6607cffef ARM: tegra: enable USB device mode and UMS on some boards
For each of Jetson TK1, Venice2, and Beaver:

- Enable the first USB controller in DT, and describe its configuration.

- Enable USB device/gadget support. This allows the user to type e.g.
  "ums 0 mmc 0" at the command-line to cause U-Boot to act a USB device
  implementing the USB Mass Storage protocol, and expose MMC device 0
  that way.

This allows a host PC to mount the Tegra device's MMC, partition it, and
install a filesystem on it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-06-05 11:25:54 -07:00
Albert ARIBAUD
cc49da249c Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-06-02 08:43:48 +02:00
Doug Anderson
567802bbd6 Exynos: Make sure ps_hold gets set in the SPL
Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-31 14:22:20 +09:00
Tom Rini
90b51c33f3 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-30 11:34:39 -04:00
Simon Glass
ae4223f444 Remove unnecessary use of hush header file
Some files include hush.h but don't actually use it. Remove this where
possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Simon Glass
14ccc30b34 exynos: dts: Enable LCD for snow
Enable LCD for snow. This is a 1366 x 768 panel.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Simon Glass
eb0dd9986c exynos: Enable PSHOLD in SPL
There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.

Add a call in SPL to enable PSHOLD.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Simon Glass
63e62674fb exynos: dts: Correct EC interrupt GPIO
Now that the GPIO numbering series has been applied, we can use the correct
GPIO for the EC interrupt.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:18 +09:00
Wu, Josh
cf874c190e ARM: at91sam9m10g45ek: enable mci0 support
Also we enable the mmc command in configuration file.

As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION,
so remove the redundant CONFIG_DOS_PARTITION definition.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-27 00:10:54 +02:00
Wu, Josh
168a48f39f ARM: at91sam9x5: define the AT91FAMILY and ARM926EJS in SoC header
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-27 00:10:51 +02:00
Wu, Josh
2ff22cf4a8 ARM: at91: remove AT91X40 macro since it is not use any more
The at91x40.h is not exist. So we remove it.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-27 00:10:50 +02:00
Andreas Bießmann
5c390a5b26 arm:at91: enable ROM loadable atmel image
For sama5d3xek we need to modify the SPL image for correct detection by ROM
code.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
2014-05-27 00:10:49 +02:00
Bo Shen
12bbc0ba81 ARM: atmel: switch to main crystal osc for SPL boot
If without switch to main crystal oscillator, the sama5d3 SoC will
use internal on chip RC oscillator.
In order to get better accuracy, switch to main crystal oscillator.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-27 00:10:40 +02:00
Ian Campbell
50827a5991 sunxi: non-FEL SPL boot support for sun7i
Add support for booting from an MMC card.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:31:03 +02:00
Ian Campbell
e24ea55c04 sunxi: mmc support
On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > +	case 1:
> > +#if CONFIG_MMC1_PG

> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?

It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...

> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.

...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.

> Other than this please add my:
>
> Reviewed-by: Stefan Roese <sr@denx.de>

Thanks!

8<---------------------------------

>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support

This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Cc: Aaron Maoye <leafy.myeh@allwinnertech.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:26:43 +02:00
Ian Campbell
5835823da3 sunxi: add gmac Ethernet support
Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i)
processors. Enable for the Cubietruck.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:25:12 +02:00
Ian Campbell
cba69eeeaa sunxi: add sun7i cpu, board and start of day support
This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.

Signed-off-by: Adam Sampson <ats@offog.org>
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:40 +02:00
Ian Campbell
286c3c3a5e sunxi: add sun7i dram setup support
This patch adds DRAM initialisation support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:30 +02:00
Ian Campbell
fe1b4db05e sunxi: add sun7i pinmux and gpio support
This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:21 +02:00
Ian Campbell
643cf0ea02 sunxi: add sun7i clocks and timer support.
This patch adds the basic clocks and timer support for the Allwinner A20
(sun7i) processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

Some of the code here is common to multiple sunxi subarchtectures, hence files
are named sun4i which is the earliest similar variant.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:12 +02:00
Stefan Agner
56d83d1c04 arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-05-25 15:46:12 +02:00
David Feng
1277bac0d2 Arm64 fix a bug of vbar_el3 initialization
Signed-off-by: David Feng <fenghua@phytium.com.cn>
2014-05-25 15:26:00 +02:00
Albert ARIBAUD
33144ea443 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-05-24 09:50:00 +02:00
Sergey Alyoshin
21254713d3 am33xx: report silicon revision instead of code
As revision code 1 is for silicon revision 2.0, it is easily confused with
silicon revision 1.0.

Device type report also reworked in same style.

Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
2014-05-23 19:40:39 -04:00
Lokesh Vutla
d7630da6f4 ARM: OMAP: Fix omap_sdram_size calculation
Last section of DMM is used for trapping tiler unmapped sections.
Corresponding trap_size should be deducted from total SDRAM size
only if trap section is overlapping with available SDRAM
based on DMM sections. Fixing the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-05-23 19:40:38 -04:00
Tom Rini
939911a64b armv7:TI: Add <asm/ti-common/sys_proto.h> and migrate omap_hw_init_context
The omap_hw_init_context function (and assorted helpers) is the same for
all OMAP-derived parts as when CHSETTINGS are used, that's the same and
our DDR base is also always the same.  In order to make this common we
simply need to update the names of the define for DDR address space
which is also common.

Cc: Sricharan R. <r.sricharan@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-05-23 19:40:05 -04:00
Lokesh Vutla
02847fcc92 ARM: DRA7xx: ctrl: Fix efuse register addresses
Efuse register addresses are wrongly programmed.
Fixing the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00
Lokesh Vutla
9fcf3d3a1d ARM: DRA72x: Update EMIF data
DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00
Lokesh Vutla
4d6bf5542e ARM: DRA72x: clocks: Update the hwdata
Adding the prcm, dplls, control module hooks for DRA72x.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00
Keerthy
8b0d1bbc7e ARM: DRA72x: volt: Update the pmic offsets
TPS65917 is used in DRA722 evm. Update the address offsets accordingly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00
Lokesh Vutla
ee77a2389b ARM: DRA72x: Add Silicon ID support
Add silicon ID code for DRA722 silicon.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-05-23 19:40:04 -04:00
pekon gupta
a0a37183bd ARM: omap: merge GPMC initialization code for all platform
GPMC controller on TI's OMAP SoC is general purpose controller to interface
with different types of external devices like;
 - parallel NOR flash
 - parallel NAND flash
 - OneNand flash
 - SDR RAM
 - Ethernet Devices like LAN9220

Though GPMC configurations may be different for each platform depending on
clock-frequency and external device interfacing with controller. But
initialization sequence remains common across all platfoms.

Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c
files into single omap-common/mem-common.c

However, actual platforms specific register config values are still sourced
from corresponding platform specific headers like;
 AM33xx: arch/arm/include/asm/arch-am33xx/mem.h
 OMAP3:  arch/arm/include/asm/arch-omap3/mem.h
 OMAP4:  arch/arm/include/asm/arch-omap4/mem.h
 OMAP4:  arch/arm/include/asm/arch-omap5/mem.h

Also, CONFIG_xx passed by board-profile decide config for which set of macros
need to be used for initialization
 CONFIG_NAND:    initialize GPMC for NAND device
 CONFIG_NOR:     initialize GPMC for NOR device
 CONFIG_ONENAND: initialize GPMC for ONENAND device

Signed-off-by: Pekon Gupta <pekon@ti.com>
[trini: define GPMC_SIZE_256M for omap3]
Signed-off-by: Tom Rini <trini@ti.com>
2014-05-23 19:39:36 -04:00
Albert ARIBAUD
3eb5e19863 Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2014-05-23 22:50:43 +02:00
Albert ARIBAUD
c534d2fdcf Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2014-05-23 22:50:23 +02:00
pekon gupta
cd324a6dd2 ARM: omap5: add platform specific info for GPMC and ELM controllers
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.

Platform specific information added into arch-xx/../hardware.h
 - CPU related platform specific details like base-address of GPMC and ELM

Platform specific information added into arch-xx/../mem.h
 - Generic configs for GPMC and ELM initialization.
 - Hardware parameters or constrains specific to GPMC and ELM IP like;
   number of max number of chip-selects available

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-05-23 16:12:02 -04:00
pekon gupta
e4426d07b6 ARM: omap4: add platform specific info for GPMC and ELM controllers
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.

Platform specific information added into arch-xx/../hardware.h
 - CPU related platform specific details like base-address of GPMC and ELM

Platform specific information added into arch-xx/../mem.h
 - Generic configs for GPMC and ELM initialization.
 - Hardware parameters or constrains specific to GPMC and ELM IP like;
   number of max number of chip-selects available

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-05-23 16:12:02 -04:00
Tom Rini
f6ed9d5094 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-22 14:29:41 -04:00
Nobuhiro Iwamatsu
dbfd1159ab arm: rmobile: koelsch: Fix QoS revision 0.240 and 0.320
Add register define of DBSC3 operation adjustment register,
and add initial value.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
dd73018b16 arm: rmobile: r8a7791: Fix MOD_SEL3 function table about FN_SEL_IEB
FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns.
However FN_SEL_IEB but we only use 3. It adds empty patterns as 0.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
7880356b89 gpio: r8a7790-gpio: Fix typo in macro
Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
f2c51fdc93 gpio: r8a7791-gpio: Fix typo in macro
Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:19 +09:00
Nobuhiro Iwamatsu
e6f2c20689 arm: rmobile: Add define of SCIF register for R8A7790 and R8A7791
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21 10:09:18 +09:00
Albert ARIBAUD
05d134b084 Merge remote-tracking branch 'u-boot/master'
Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
2014-05-20 10:05:42 +02:00
Albert ARIBAUD
a26acb7dc9 Merge remote-tracking branch 'u-boot-sh/rmobile'
Conflicts:
	boards.cfg

Trivial conflict, maintainer change plus board addition
2014-05-16 20:43:04 +02:00
Albert ARIBAUD
6a2f30a03a Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-05-16 17:56:50 +02:00
Albert ARIBAUD
a90bed77a6 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-05-16 16:49:50 +02:00
Jaehoon Chung
ea5ee2d7fb ARM: dts: exnyos: enable dw-mmc controller
Enabled the dw-mmc controller.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
7d3ca0f89d ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC
Exynos serise can be supported the dw-mmc controller.
So, it's good that used the general prefix as "_EXYNOS_DWMMC".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
39c4975622 ARM: exynos: clock: modify the set_mmc_clk for exynos4
Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Beomho Seo
cd0ae61cc2 board: trats2: Enable device tree on Trats2
This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.

Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Beomho Seo
00ee81300f arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.

Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Beomho Seo
77ee62d882 arm: exynos: pinmux: add sdmmc4 gpio configratuion
For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.

Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Albert ARIBAUD
44cfc3a83f Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2014-05-15 17:19:45 +02:00
Albert ARIBAUD
9f5f51540d Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-05-15 16:36:02 +02:00
Albert ARIBAUD
41623c91b0 arm: move exception handling out of start.S files
Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15 16:24:53 +02:00
Albert ARIBAUD
60a4f39fcd arm: remove unused _end_vect and _vectors_end symbols
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15 16:24:47 +02:00
Albert ARIBAUD
23ff29bc17 arm: pxa: move SP check from start.S to cpuinfo.c
PXA start.S has a PXA (variant) specific check in
start.S. Move it to cpuinfo.c.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marex@denx.de>
2014-05-15 16:24:41 +02:00
Albert ARIBAUD
cd6cc3440f arm: move reset_cpu from start.S into cpu.c
CPUs arm946es and sa1100 both define the reset_cpu()
function in their start.S file. Move this cpu-specific code
into cpu.c so that start.S only contains ARM generic code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15 16:24:37 +02:00
Albert ARIBAUD
b4ee1491b9 arm1136: move cache code from start.S to cache.c
arch/arm/cpu/arm1136/start.S contain a cache flushing function.
Remove the function and move its code into arch/arm/lib/cache.c.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15 16:24:26 +02:00
Masahiro Yamada
9f9d41bad1 zynq: add UART nodes to device tree to initialize UART with OF
Commit c9416b92 added OF UART initialization support
but aliases nodes are missing in device tree.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board]
Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15 13:57:31 +02:00
Masahiro Yamada
7d34c5de72 zynq: add memory nodes to device tree to initialize DRAM with OF
Commit 9e0e37ac added OF RAM initialization support
but memory nodes are missing in device tree.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board]
Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15 13:57:30 +02:00
Masahiro Yamada
580a54c5d4 zynq: import zynq-7000.dtsi from Linux Kernel
Our current motivation is to use OF initialization for RAM and UART.
But adding full DTS would be helpful in future, for instance,
for OF configuration of Ethernet, MMC, USB, etc.

This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5
and adjusts the license comment block for SPDX.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15 13:57:29 +02:00
Stefano Babic
e7f9350525 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-15 10:27:32 +02:00
Stephen Warren
a4539a2aa7 usb: tegra: support device mode
A few changes are made to the Tegra EHCI driver so that it can set
everything up for device-mode operation on the first USB controller.
This can be used in conjunction with ci_udc.c to operate as a USB
device.

Detailed changes are:

* Rename set_host_mode() to set_up_vbus() since that's really what it
  does.

* Modify set_up_vbus() to know whether it's initializing in host or
  device mode, and:

  - Skip the external VBUS check in device mode, since external VBUS is
    expected in this case.

  - Disable VBUS output in device mode.

* Modify init_phy_mux() to know whether it's initializing in host or
  device mode, and hence skip setting USBMODE_CM_HC (which enables host
  mode) in device mode. See the comments in that function for why this
  is safe w.r.t. the ordering requirements of PHY selection.

* Modify init_utmi_usb_controller() to force "b session valid" in device
  mode, since the HW requires this. This is done in UTMI-specific code,
  since we only support device mode on the first USB controller, and that
  controller can only talk to a UTMI PHY.

* Enhance ehci_hcd_init() to error-check the requested host-/device-mode
  vs. the dr_mode (dual-role mode) value present in device tree, and the
  HW configurations which support device mode.

* Enhance ehci_hcd_init() not to skip HW initialization when switching
  between host and device mode on a controller. This requires remembering
  which mode the last initialization used.

Cc: Jim Lin <jilin@nvidia.com>
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-15 00:21:17 +02:00
Masahiro Yamada
66e6715c5f zynq: treat ps7_init.c/h as external files to ignore them
ps7_init.c and ps7_init.h are supposed to be exported by hw project
and copied to board/xilinx/zynq/ directory.

We want them to be ignored by git.
So what we should do is to always treat them as external files
rather than replacing ps7_init.c

This commit does:

 - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c
   and delete board/xilinx/zynq/ps7_init.c

 - Compile board/xilinx/zynq/ps7_init.c only when it exists

 - Add .gitignore to ignore ps7_init.c/h

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:52:46 +02:00
Michal Simek
eb8c54bfaa ARM: zynq: ehci: Added USB host driver support
Added USB host driver for zynq.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:35 +02:00
Michal Simek
3cc3fa8672 ARM: zynq: Add MIO detection code
Add run-time MIO pin detection to get actual
pin configuration for specific periphery.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:35 +02:00
Mike Looijmans
dc4a1a2729 ARM: zynq: Fix bootmode mask
Bootmode mask was defined as 0x0F, but documentation mentions 0x07.
Experiments show that bit "3" is the JTAG chain configuration.
Change the mask to "7" to allow systems with a different chain
configuration to boot correctly.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
2da7a745b6 ARM: zynq: Setup correct slcr_lock value
The driver should setup slcr state according
to slcr operations.

Reported-by: Andrey Filippov <andrey@elphel.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
6e04769caf ARM: zynq: slcr: Fix incorrect commentary
Fix c&p error in zynq_slcr_devcfg_enable() commentary
and extending it with description according
to Zynq TRM also in zynq_slcr_devcfg_disable().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
1540fb725b ARM: zynq: Call zynq board_init() in SPL
Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2014-05-14 07:43:34 +02:00
Michal Simek
10fa49f428 ARM: zynq: Do not use half memory size for ECC case
Memory size should be specified without ECC place.
If you need to have half memory size, please change
u-boot configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Siva Durga Prasad Paladugu
96a2859e54 ARM: zynq: Added efuse status register base address
Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
ec9638659f ARM: zynq: Fix sparse warning in ddrc.c
Warning:
arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
3b5b599f17 ARM: zynq: Fix sparse warnings in slcr.c
Warnings:
arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:33 +02:00
Dmitry Lifshitz
d57b649e6c ARM: OMAP5: add CKO buffer control mask
Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-05-13 19:43:00 -04:00
Dmitry Lifshitz
4b5d383924 ARM: OMAP5: add UART4 support
Add UART4 base address.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-05-13 19:43:00 -04:00
Yegor Yefremov
4b97bcbe20 am33xx: add SSC enable macro
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2014-05-13 19:42:59 -04:00
Stephen Warren
2364e151e4 ARM: tegra: use a CPU freq that all SKUs can support
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.

Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:

repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]

According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.

At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.

An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.

While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.

Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:32 -07:00
Stephen Warren
bb14469ae0 ARM: tegra: add function to enable input clamping on tristate
The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Stephen Warren
eceb3f26f4 ARM: tegra: add GPIO initialization table function
The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Stephen Warren
4a68d3431a ARM: tegra: allow pinmux mux option not to be set by init tables
Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.

For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Stephen Warren
48ec7a9468 ARM: tegra: fix CPU VDD comment in Tegra30 CPU init code
The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
implies. Fix the comment.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Stephen Warren
f175603f7c ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICE
If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.

A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE

1) It isn't documented in README. The same is true for a lot of similar
   defines used by api_storage.c.

2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
   valid values are 0..n-1 not 0..n.

However, I this patch does not address those shortcomings.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Akshay Saraswat
f6ae1ca058 S5P: Exynos: Add GPIO pin numbering and rename definitions
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
  To have consistent 0..n-1 GPIO numbering the banks are divided
  into different parts where ever they have holes in them.

* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
  These changes were done to enable cmd_gpio for EXYNOS and
  cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
  getting a error during compilation.

* Adds support for name to gpio conversion in s5p_gpio to enable
  gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
  to decode the input gpio name to gpio number.
  Example: SMDK5420 # gpio set gpa00

Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-13 15:20:38 +09:00
York Sun
2a1680e30e common/board_f: Initialized global data for generic board
Some platforms (tested on mpc85xx, mpc86xx) use global data before calling
function baord_inti_f(). The data should not be cleared later. Any arch
which uses global data in generic board board_init_f() should define
CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Simon Glass <sjg@chromium.org>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Simon Glass <sjg@chromium.org>
2014-05-12 15:20:05 -04:00
Masahiro Yamada
8e2615752e bd_info: remove bi_barudrate member from struct bd_info
gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
2014-05-12 15:19:45 -04:00
Thomas Diener
bf0adb861e imx25: Add new hardware registers
Signed-off-by: Thomas Diener <dietho@gmx.de>
2014-05-09 15:10:53 +02:00
Fabio Estevam
98d2cffd23 iomux-v3: Add support for mx6sl LVE bit
On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL
register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>
2014-05-09 15:10:53 +02:00
Albert ARIBAUD
d2a3e91139 Merge branch 'u-boot/master'
Conflicts:
	drivers/net/Makefile

(trivial merge)
2014-05-09 11:50:14 +02:00
Nobuhiro Iwamatsu
ede4d5e387 usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs
The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-04-30 10:30:56 +02:00
Stefano Babic
3deb22a484 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-04-29 17:41:19 +02:00
Fabio Estevam
694c3bc107 mx6slevk: Add SPI NOR flash support
mx6slevk has a m25p32 SPI NOR flash connected to ESCSPI port.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-04-28 14:00:16 +02:00
Stefano Babic
563491b7b3 mx6: fix weird formatting in imx6q-sabreauto.dts
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-28 13:45:29 +02:00
Nobuhiro Iwamatsu
e05b98dadf arm: rmobile: Add register infomation of PLL regsiter
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
fb3af517ef arm: rmobile: r8a7791: Add support ES2 revision
There is ES2 is a new revision to R8A7791.
This adds support this revision.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
f637656dd4 arm: rmobile: r8a7790: Add support ES2 revision
There is ES2 is a new revision to R8A7790.
This adds support this revision.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
73ff6801e6 arm: rmobile: Update print_cpuinfo function
The print_cpuinfo fucntion has same code.
It has a code of many common.  This adds a table of CPU information, duplicate
using for-loop.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
5dd8dbd7db arm: rmobile: Add prototype for function to get the CPU information to rmobile.h
These functions are defined but has no prototype declaration. Add them.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
a028abea6c arm: rmobile: Add rmobile_get_cpu_rev_fraction() for R-Car SoCs
This adds rmobile_get_cpu_rev_fraction to get fraction revision for R-Car SoCs.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
210f7b2d26 arm: rmobile: Add 1 to value of the CPU revision in rmobile_get_cpu_rev_integer()
Value that can be obtained in the rmobile_get_cpu_rev_integer() starts at 0.
However, revisions to start from 1, which adds 1.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
9b7fa2fed6 arm: rmobile: Merge functions to get the CPU information of R8A7790 and R8A7791
Functions to get the CPU information of R8A7790 and R8A7791 are common.
This merges these as cpu_info-rcar.c.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:12 +09:00
Nobuhiro Iwamatsu
42c53ab0a7 arm: rmobile: r8a779x: Fix L2 cache init and latency setting
L2CTLR only need to update for cluster 0.
This changes L2CTLR to initialize only when cluster is 0.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:11 +09:00
Nobuhiro Iwamatsu
5723e24df5 arm: rmobile: Coordinate the common part of the header file of r8a7790 and r8a7791
Header files of R8A7790 and R8A7791 have common part of many.
This coordinates as rcar-base.h.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-28 04:35:11 +09:00
Albert ARIBAUD
c9aab0f9dd Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-04-21 21:01:35 +02:00
Tom Rini
b149c4c399 ARM:tegra20: Remove aes debug prints
In 6e7b9f4 some of the debug prints for AES code moved into the generic
code, so we remove these additional calls.

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Tom Warren <twarren@nvidia.com>
2014-04-18 16:14:17 -04:00
Stephen Warren
53eb768dfb aes: make apply_cbc_chain_data non-static
Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart
code. This function was recently moved into the core aes.c and made
static, which prevents the Tegra code from compiling. Make it public
again to avoid the compile errors:

arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’:
arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration]
arch/arm/cpu/built-in.o: In function `sign_object':
.../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data'
.../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data'

Fixes: 6e7b9f4fa0 ("aes: Move the AES-128-CBC encryption function to common code")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-04-18 16:14:17 -04:00
Masahiro Yamada
d8d7cbd96a kbuild: use boolean macros to select tegra*-common directory
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-17 17:44:35 -04:00
Manish Badarkhe
893b92f86f arm, da850: staticize funtions
Make funtions static which are locally used in file
and remove the declaration from header file.

Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com>
2014-04-17 17:24:40 -04:00
Tom Rini
d0e6d34d7c am335x: Switch to CONFIG_SKIP_LOWLEVEL_INIT from guarding SPL or NOR_BOOT
In the case of SPL or NOR_BOOT (no SPL involved) we need to include
certain code in the build.  Use !CONFIG_SKIP_LOWLEVEL_INIT rather than
CONFIG_SPL_BUILD || CONFIG_NOR_BOOT to make the code clearer, and to
make supporting XIP QSPI boot clearer in the code.

Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
2014-04-17 17:24:40 -04:00
Karicheri, Muralidharan
fc9a8e8d40 keystone2: net: add keystone ethernet driver
Ethernet driver configures the CPSW, SGMI and Phy and uses
the the Navigator APIs. The driver supports 4 Ethernet ports and
can work with only one port at a time.

Port configurations are defined in board.c.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
2014-04-17 17:24:39 -04:00
Vitaly Andrianov
30fe8c150f keystone2: add keystone multicore navigator driver
Multicore navigator consists of Network Coprocessor (NetCP) and
Queue Manager sub system. More details on the hardware can
be obtained from the following links:-

Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6
Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9

Multicore navigator driver implements APIs to configure
the Queue Manager and NetCP Pkt DMA.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:39 -04:00
Vitaly Andrianov
ef509b9063 k2hk: add support for k2hk SOC and EVM
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README for details on the board, build and other
information.

This patch add support for keystone architecture and k2hk evm.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
2014-04-17 17:24:38 -04:00
Vitaly Andrianov
e8459dcc33 i2c, davinci: convert driver to new mutlibus/mutliadapter framework
- add davinci driver to new multibus/multiadpater support
    - adapted all config files, which uses this driver

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-04-17 17:24:38 -04:00
Karicheri, Muralidharan
356d15ebb2 i2c, davinci: move i2c_defs.h to the drivers/i2c directory
This patch moves the davinci i2c_defs.h file to drivers.i2c directory.
It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs.

Not used "git mv" command to move the file because small part of
it with definitions specific for Davinci SOCs has to remain in the
arch/arm/include/asm/arch-davinci.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:38 -04:00
Vitaly Andrianov
11bc755722 arm: add support for arch timer
This patch add basic support for the architecture timer found on recent
ARMv7 based SoCs.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
2014-04-17 17:24:38 -04:00
Tom Rini
79b079f35c dra7xx_evm: Add QSPI_4 support, qspiboot build target
We previously only supported QSPI_1 (single) support.  Add QSPI_4 (quad)
read support as well.  This means we can be given one of two boot device
values, but don't care which it is, so perform a fixup on the QSPI_4
value.  We add a qspiboot build target to better show how you would use
QSPI as a boot device in deployment.  When we boot from QSPI, we can
check the environment for 'boot_os' to control Falcon Mode.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-17 17:24:37 -04:00
Nishanth Menon
548a64d845 OMAP3: beagle-xm: generate fake USB ethernet MAC address from dieid
Similar to OMAP5uEVM, PandaBoard, BeagleBoard-XM has a USB based
ethernet without MAC address embedded. So fake a MAC address following
the similar strategy used on OMAP5 and PandaBoard family.

Signed-off-by: Nishanth Menon <nm@ti.com>
2014-04-17 14:39:54 -04:00
Nishanth Menon
79e7e87f91 omap3/sys_info: provide interface to read die id
introduce get_die_id() function which allows generation of
information such as fake MAC address from the processor ID code.

Signed-off-by: Nishanth Menon <nm@ti.com>
2014-04-17 14:39:54 -04:00
Nishanth Menon
8a0c6d6fa9 OMAP: common: consolidate fake USB ethernet MAC address creation
TI platforms such as OMAP5uevm, PandaBoard, use equivalent
logic to generate fake USB MAC address from device unique DIE ID.

Consolidate this to a generic location such that other TI platforms such
as BeagleBoard-XM can also use the same.

NOTE: at this point in time, I dont yet see a need for a generic dummy
ethernet MAC address creation function, but if there is a need in the
future, this can be further abstracted out.

Signed-off-by: Nishanth Menon <nm@ti.com>
2014-04-17 14:39:54 -04:00
Wolfgang Denk
a88e55c4c6 ARM: OMAP: replace custom sr32() by standard I/O accessors
Replace the custom bit manipulation function sr32() by standard I/O
accessors.  A major motivation for this cleanup was the fact, that a
number of calls of that function resulted in 32 bit wide shift
operations on u32 data, which according to the C-ISO/IEC-9899-Standard
provokes undefined behaviour:

	6.5.7 Bitwise shift operators
	...
        If the value of the right operand is negative or is greater
        than or equal to the width of the promoted left operand, the
        behavior is undefined.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-04-17 14:39:54 -04:00
Wolfgang Denk
4e4685027c ARM: OMAP: hide custom bit manipulation function sr32()
The only remaining user of the custom bit manipulation function sr32()
is arch/arm/cpu/armv7/omap3/clock.c, so  make it a static function in
that file to prepare complete removal.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-04-17 14:39:54 -04:00
Wolfgang Denk
e7300f463d ARM: OMAP: remove sr32() from OMAP board code
Replace the custom sr32() bit manipulation function in
arch/arm/cpu/armv7/omap3/board.c and board/ti/panda/panda.c
by standard I/O accessors.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-04-17 14:39:54 -04:00
Tom Rini
0f507779ca Merge branch 'next' 2014-04-17 14:33:25 -04:00
Stephen Warren
d381294aef ARM: tegra: pack pinmux data tables tighter
Use smaller fields in the Tegra pinmux structures in order to pack the
data tables into a smaller space. This saves around 1-3KB for the SPL
and around 3-8KB for the main build of U-Boot, depending on the board,
which SoC it uses, and how many pinmux table entries there are.

In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the
values of PMUX_FUNC_RSVD* to values which require 16 bits to store them,
but instead let their values be assigned automatically, so they end up
fitting into 8 bits.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stefan Agner
8f9fd6caaf usb: tegra: combine header file
Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication, mainly for
Tegra30 and newer devices.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stefan Agner
b1d615f3f1 usb: tegra: fix PHY configuration
On Tegra30 and later, the PTS (parallel transceiver select) and STS
(serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
rather than PORTSC1_0 register. Since the reset configuration
usually matches the intended configuration, this error did not show
up on Tegra30 devices.

Also use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stephen Warren
e04bfdacb3 ARM: tegra: add Jetson TK1 board
Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of
its design with Venice2.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stephen Warren
d68c942927 ARM: tegra: Tegra124 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra124_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

There are differences in the set of drive groups. I have validated this
against the TRM. There are differences order of pin definitions in
pinmux.c; these previously had significant mismatches with the correct
order:-( I adjusted a few entries in pinmux-config-venice2.h since the
set of legal functions for some pins was updated to match the TRM.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stephen Warren
1fa3a63413 ARM: tegra: Tegra114 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:06 -07:00
Stephen Warren
803d01edc2 ARM: tegra: Tegra30 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra30_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted one entry in
pinmux-config-cardhu.h due to this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
70ad375ee4 ARM: tegra: Tegra20 pinmux cleanup
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
dfb42fc95d ARM: tegra: pinmux naming consistency fixes
Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
  are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
  compiles. A separate per-SoC change will be made immediately following,
  in order to keep individual patch size down.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
a45fa43685 ARM: tegra: reduce public pinmux API
Remove a few unused functions from the pinmux header. They aren't
currently used, and removing them prevents any new usage from appearing.
This will ease moving to just pinmux_config_table() and
padgrp_config_table() in the future.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
e296995767 ARM: tegra: pinctrl: remove duplication
Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the
duplication by creating pinmux-common.c for all the identical code.

This leaves:
* arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of
  the various pins/pin groups, drive groups, and mux functions.
* arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table
  stating which pin groups support which mux functions.

The code in pinmux-common.c is semantically identical to that in the
various original pinmux.c, but had some consistency and cleanup fixes
applied during migration.

I removed the definition of struct pmux_tri_ctlr, since this is different
between SoCs (especially Tegra20 vs all others), and it's much simpler to
deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c,
and warmboot_avp.c needed updates due to this, since they previously
hijacked this struct to encode the location of some non-pinmux registers.
Now, that code simply calculates these register addresses directly using
simple and obvious math. I like this method better irrespective of the
pinmux code cleanup anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
19ed7b4ecf ARM: tegra: use apb_misc.h in more places
Tegra's "APB misc" register region contains various miscellaneous
registers and the Tegra pinmux registers. Some code that touches the
misc registers currently uses struct pmux_tri_ctlr, which is intended to
be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl,
which is intended to be a definition of the miscellaneous registers.
Convert all such code to use struct apb_misc_pp_ctrl, since struct
pmux_tri_ctlr goes away in the next patch.

This requires adding a missing field definition to struct
apb_misc_pp_ctrl, and moving the header into a more common location.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
07bbd48b47 ARM: tegra: prototype pinmux_init() in board.h
pinmux_init() is a board-level function, not a pinmux driver function.
Move the prototype to a board header rather than the driver header.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
6ac1e542c6 ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
For consistency with other SoCs, modify Tegra20's enum pmux_func to:

* Remove PMUX_FUNC values that aren't real
* Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0;
  this will be assumed by pinmux_set_func() in a future patch.

Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a
private define inside the driver to prevent this from causing compilaton
errors. This will be cleaned up when the pin tables are re-written in a
later patch in this series.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
dd45948dd7 ARM: tegra: pinctrl: remove vddio
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Stephen Warren
0d2c0d5788 ARM: tegra: pinctrl: remove func_safe
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:04 -07:00
Eric Benard
e688a99c07 imx-common/video: add detect_hdmi
this function is used by several board together with board_video_skip
to detect if hdmi is plugged is order to select the display to use.
So move it in imx-common to share it.

Signed-off-by: Eric Bénard <eric@eukrea.com>
2014-04-15 12:23:57 +02:00
Eric Benard
93ad66ced3 imx-common: add board_video_skip
this function is shared by several boards and thus can be factorized

Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-04-15 12:23:56 +02:00
Albert ARIBAUD
519fdde9e6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	include/configs/trats.h
	include/configs/trats2.h
	include/mmc.h
2014-04-08 09:25:08 +02:00
David Feng
c71645ad2b arm64 patch: gicv3 support
This patch add gicv3 support to uboot armv8 platform.

Changes for v2:
  - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
  - move smp_kick_all_cpus() from gic.S to start.S, it would be
    implementation dependent.
  - Each core initialize it's own ReDistributor instead of master
    initializeing all ReDistributors. This is advised by arnab.basu
    <arnab.basu@freescale.com>.

Signed-off-by: David Feng <fenghua@phytium.com.cn>
2014-04-08 00:15:12 +02:00
Mela Custodio
91290cf728 bootstage: arm: fix fdt stashing code
The conditional is using a variable that is not defined.

Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com>
2014-04-07 23:03:13 +02:00
Leo Yan
42ddfad6ab ARMv8: fix bug for flush data cache by set/way
When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula to calculate the offset: log2(Associativity * 2 - 1), so finally
it cannot flush data cache properly.

Signed-off-by: Leo Yan <leoy@marvell.com>
2014-04-07 22:27:22 +02:00
York Sun
88590148fa armv8: Flush dcache before switching to EL2
For ARMv8, U-boot has been running at EL3 with cache and MMU enabled.
Without proper setup for EL2, cache and MMU are both disabled (out of
reset). Before switching, we need to flush the dcache to make sure the
data is in the main memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: David.Feng <fenghua@phytium.com.cn>
2014-04-07 22:19:00 +02:00
Marcel Ziswiler
6c81a93db7 arm: vf610: add enet1 support
This patch contains several changes required for second Ethernet
(enet1/RMII1) port on vf610
- ANADIG PLL5 control definitions required for Ethernet RMII1 clock
- Secondary Ethernet (enet1) MAC RMII1 base address definition
- RMII1 iomux definitions
- VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for
  internal (e.g. crystal-less) Ethernet clocking.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-04-07 20:15:44 +02:00
Marcel Ziswiler
c7098965e3 arm: vf610: add uart0 clock/iomux definitions
Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux
definitions for UART0 (aka. SCI0).

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-04-07 20:15:37 +02:00
Marcel Ziswiler
25839c0197 arm: vf610: fix anadig register struct
The anadig_reg structure started at the wrong offset (fixed by adding
reserved_0x000[4]), was missing some reserved field required for
alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl)
and further contained a too short reserved field causing further miss-
alignment (reserved_0x0C4[7]). Also, rename all the reserved fields
and using a memory offset based scheme for.

Discovered and tested by temporarily putting the following debug
instrumentation into board_init():
    struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
    printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl);
    printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl);

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-04-07 20:15:29 +02:00
Łukasz Majewski
42f5e8a25a build:arm: Remove setting of CROSS_COMPILE environment variable
After Kbuild introduction, the CROSS_COMPILE environment variable has been
set to some default value (prefix arm-linux-).

This shall be removed since it breaks building u-boot for native arm target
(like qemu ARM).
Moreover not all compilers have arm-linux- prefix.

Additionally the u-boot cross compiles with CROSS_COMPILE= set explicitly-
e.g.:
CROSS_COMPILE=/ .... /arm-v7a-linux-gnueabi- make

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-07 20:04:36 +02:00
Albert ARIBAUD
284bb60ed6 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-04-07 19:13:42 +02:00
Nitin Garg
b7588e3bdc ARM: Add workaround for Cortex-A9 errata 761320
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-04-07 18:11:01 +02:00
Nitin Garg
f71cbfe3ca ARM: Add workaround for Cortex-A9 errata 794072
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2014-04-07 18:11:00 +02:00
York Sun
1e6ad55c05 armv8/cache: Change cache invalidate and flush function
When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wrapper.

Invalidating large cache can ben slow on emulator, so we postpone doing
so until I-cache is enabled, and before enabling D-cache.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
2014-04-07 17:43:41 +02:00
York Sun
83571bcab1 armv8/cache: Flush D-cache, invalidate I-cache for relocation
If D-cache is enabled, we need to flush it, and invalidate i-cache before
jumping to the new location. This should be done right after relocation.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
2014-04-07 17:43:36 +02:00
York Sun
f5222cfd49 armv8/cache: Consolidate setting for MAIR and TCR
Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
sub-architecture.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
2014-04-07 17:43:32 +02:00
Andreas Färber
2c67e0e7cf arm: Handle .gnu.hash section in ldscripts
Avoids "could not find output section .gnu.hash" ld.bfd errors on openSUSE.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-04-07 11:12:18 +02:00
Chin Liang See
ddfeb0aaf4 socfpga: Adding Clock Manager driver
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
2014-04-07 10:41:50 +02:00
Marek Vasut
1a9df13d5b arm: mxs: Add support for generating signed BootStream
This patch adds the groundwork for generating signed BootStream, which
can be used by the HAB library in i.MX28. We are adding a new target,
u-boot-signed.sb , since the process for generating regular non-signed
BootStream is much easier. Moreover, the signed bootstream depends on
external _proprietary_ _binary-only_ tool from Freescale called 'cst',
which is available only under NDA.

To make things even uglier, the CST or HAB mandates a kind-of circular
dependency. The problem is, unlike the regular IVT, which is generated
by mxsimage, the IVT for signed boot must be generated by hand here due
to special demands of the CST. The U-Boot binary (or SPL binary) and IVT
are then signed by the CST as a one block. But here is the problem. The
size of the entire image (U-Boot, IVT, CST blocks) must be appended at
the end of IVT. But the size of the entire image is not known until the
CST has finished signing the U-Boot and IVT. We solve this by expecting
the CST block to be always 3904B (which it is in case two files, U-Boot
and the hand-made IVT, are signed in the CST block).

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-04-04 11:44:59 +02:00
Stefano Babic
1cad23c5f4 Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-04 11:35:30 +02:00
Stefano Babic
5dd73bc0a4 Revert "arm: mxs: Add support for generating signed BootStream"
This reverts commit 53e6b14e03.

Patch does not merge anymore with u-boot-arm and must be rebased.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-04 11:29:29 +02:00
Stefano Babic
fa9c021632 mx6: add example DTB for mx6qsabreauto
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2014-04-02 10:46:21 +02:00
Stefano Babic
e64348f5eb imx: add rules for U-Boot DTB support
Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-02 10:45:35 +02:00
Stefano Babic
bb2637be09 mxs: fix warning in SPL with console support
Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-02 10:42:06 +02:00
Marek Vasut
9926eb31b7 arm: mxs: Add serial console support into SPL
Add support for serial console into the i.MX23/i.MX28 SPL. A full,
uncrippled serial console support comes very helpful when debugging
various spectacular hardware bringup issues early in the process.
Because we do not use SPL framework, but have our own minimalistic
SPL, which is compatible with the i.MX23/i.MX28 BootROM, we do not
use preloader_console_init(), but instead use a similar function to
start the console. Nonetheless, to avoid blowing up the size of the
SPL binary, this support is enabled only if CONFIG_SPL_SERIAL_SUPPORT
is defined, which is disabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-04-01 10:25:11 +02:00
Marek Vasut
65ed5e8572 arm: mxs: Properly set GD pointer in SPL
Set the GD pointer in the SPL to a defined symbol so various
functions from U-Boot can be used without adverse side effects.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-04-01 10:23:01 +02:00
Marek Vasut
53e6b14e03 arm: mxs: Add support for generating signed BootStream
This patch adds the groundwork for generating signed BootStream, which
can be used by the HAB library in i.MX28. We are adding a new target,
u-boot-signed.sb , since the process for generating regular non-signed
BootStream is much easier. Moreover, the signed bootstream depends on
external _proprietary_ _binary-only_ tool from Freescale called 'cst',
which is available only under NDA.

To make things even uglier, the CST or HAB mandates a kind-of circular
dependency. The problem is, unlike the regular IVT, which is generated
by mxsimage, the IVT for signed boot must be generated by hand here due
to special demands of the CST. The U-Boot binary (or SPL binary) and IVT
are then signed by the CST as a one block. But here is the problem. The
size of the entire image (U-Boot, IVT, CST blocks) must be appended at
the end of IVT. But the size of the entire image is not known until the
CST has finished signing the U-Boot and IVT. We solve this by expecting
the CST block to be always 3904B (which it is in case two files, U-Boot
and the hand-made IVT, are signed in the CST block).

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-03-31 18:28:50 +02:00
Marek Vasut
9c2c8a3129 arm: mxs: Adjust the load address of U-Boot and SPL for HAB
When using HAB, there are additional special requirements on the placement of
U-Boot and the U-Boot SPL in memory. To fullfill these, this patch moves the
U-Boot binary a little further from the begining of the DRAM, so the HAB CST
and IVT can be placed in front of the U-Boot binary. This is necessary, since
both the U-Boot and the IVT must be contained in single CST signature. To
make things worse, the IVT must be concatenated with one more entry at it's
end, that is the length of the entire CST signature, IVT and U-Boot binary
in memory. By placing the blocks in this order -- CST, IVT, U-Boot, we can
easily align them all and then produce the length field as needed.

As for the SPL, on i.MX23/i.MX28, the SPL size is limited to 32 KiB, thus
we place the IVT at 0x8000 offset, CST right past IVT and claim the size
is correct. The HAB library accepts this setup.

Finally, to make sure the vectoring in SPL still works even after moving
the SPL from 0x0 to 0x1000, we add a small function which copies the
vectoring code and tables to 0x0. This is fine, since the vectoring code
is position independent.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-03-31 18:28:50 +02:00
Masahiro Yamada
b4722fefd0 tegra: fix Makefile to pass per-file CFLAGS
Since Kbuild was introduced, warmboot_avp.o has been compiled
without -march=armv4t.

Makefile should be adjusted to pass a per-file option.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
2014-03-31 11:33:28 -04:00
Przemyslaw Marczak
680d8f03ea cpu: exynos4: add ace sha base address
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2014-03-28 15:06:31 -04:00
Marek Vasut
463bb19eeb spl: Fix guardian macros in spl.h
Fix the macros guarding the spl.h header for various platforms. Due to
a typo and a propagation of it, the macros went out-of-sync with their
ifdef check, so fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-03-28 15:06:30 -04:00
Masahiro Yamada
254d68b601 kbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/lib
U-Boot has supported two kinds of asm-offsets.h.

One is generic for all architectures and its source is located at
./lib/asm-offsets.c.

The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.

Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.

It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.

This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.

By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
2014-03-28 15:06:29 -04:00
Marek Vasut
b97241b312 kbuild: Rename UIMAGE to MKIMAGE
U-Boot uses the 'mkimage' tool to produce various image types,
not only uImage image type. Rename the invocation name from
UIMAGE to MKIMAGE.

The following command was used to do the replacement:
git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \
 xargs -i sed -i "s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@" {}

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-28 15:06:29 -04:00
Albert ARIBAUD
ab6423cae0 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.

Conflicts:
	board/samsung/common/board.c
2014-03-25 10:53:15 +01:00
Pantelis Antoniou
93bfd61677 mmc: Split mmc struct, rework mmc initialization (v2)
The way that struct mmc was implemented was a bit of a mess;
configuration and internal state all jumbled up in a single structure.

On top of that the way initialization is done with mmc_register leads
to a lot of duplicated code in drivers.

Typically the initialization got something like this in every driver.

	struct mmc *mmc = malloc(sizeof(struct mmc));
	memset(mmc, 0, sizeof(struct mmc);
	/* fill in fields of mmc struct */
	/* store private data pointer */
	mmc_register(mmc);

By using the new mmc_create call one just passes an mmc config struct
and an optional private data pointer like this:

	struct mmc = mmc_create(&cfg, priv);

All in tree drivers have been updated to the new form, and expect
mmc_register to go away before long.

Changes since v1:

* Use calloc instead of manually calling memset.
* Mark mmc_register as deprecated.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 12:58:56 +02:00
Marek Vasut
6e7b9f4fa0 aes: Move the AES-128-CBC encryption function to common code
Move the AES-128-CBC encryption function implemented in
tegra20-common/crypto.c into lib/aes.c . This is well re-usable common
code. Moreover, clean the code up a bit and fix the kerneldoc-style
annotations.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-03-21 16:43:53 -04:00
Albert ARIBAUD
63f347ec4c Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-03-13 18:32:26 +01:00
Marek Vasut
47c9c76b8a arm: exynos: Squash bogus warnings in pinmux
Squash these warnings in pinmux.c found with GCC 4.8:

/arch/arm/cpu/armv7/exynos/pinmux.c: In function 'exynos_pinmux_config':
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'count' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count' was declared here
  int i, start, count;
                ^
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start' was declared here
  int i, start, count;
         ^
/arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may be used uninitialized in this function [-Wmaybe-uninitialized]
   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
                   ^
/arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was declared here
  struct s5p_gpio_bank *bank;
                        ^
/arch/arm/cpu/armv7/exynos/pinmux.c: In function 'exynos_pinmux_config':
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'count' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count' was declared here
  int i, start, count;
                ^
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start' may be used uninitialized in this function [-Wmaybe-uninitialized]
  for (i = start; i < start + count; i++) {
                            ^
/arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start' was declared here
  int i, start, count;
         ^
/arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may be used uninitialized in this function [-Wmaybe-uninitialized]
   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
                   ^
/arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was declared here
  struct s5p_gpio_bank *bank;
                        ^

Note that the warning is bogus, the function can never be called with invalid
'peripheral' argument. GCC just cannot analyze this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-13 09:46:57 +09:00
Masahiro Yamada
4ab3fc5eba kirkwood: kwbimage: refactor CONFIG_SYS_KWD_CONFIG
Pull out "$(SRCTREE)/" from CONFIG_SYS_KWD_CONFIG
and push it into the top Makefile.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Dave Purdy <david.c.purdy@gmail.com>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Cc: Luka Perkov <luka@openwrt.org>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Jason Cooper <u-boot@lakedaemon.net>
Cc: Siddarth Gore <gores@marvell.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Eric Cooper <ecc@cmu.edu>
Cc: Suriyan Ramasami <suriyan.r@gmail.com>
2014-03-12 17:04:52 -04:00
Masahiro Yamada
07e27ce013 kbuild,mxs: use short logs for MXS images
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-03-12 17:04:37 -04:00
Tom Rini
d73f38f7ba am33xx: Rework #ifdef's around s_init for clarity
The s_init function is only called on SPL or XIP cases, so lets only
build it for them.  This makes the #if logic within the function a bit
clearer as to when we are or are not calling things, and makes it easier
to see that for example preloader_console_init isn't ever called in the
non-XIP full U-Boot case.

Signed-off-by: Tom Rini <trini@ti.com>
2014-03-12 14:51:45 -04:00
Piotr Wilczek
1ecab0f30f board:trats2: Enable device tree on Trats2
This patch enables to run Trats2 board on device tree.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:55:00 +09:00
Piotr Wilczek
fe60164792 board:trats: Enable device tree on Trats
This patch enables to run Trats board on device tree.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:55:00 +09:00
Piotr Wilczek
3f41ffe4b5 board:universal: Enable device tree on Universal
This patch enables to run Universal board on device tree.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:55:00 +09:00
Piotr Wilczek
bf7716d6a3 board:origen: Enable device tree on Origen
This patch enables to run Origen board on device tree.

Uart, DRAM and MMC init functions are removed as their
generic replacements form the common board file are used.

The config file is modified to contain only board specific options.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:55:00 +09:00
Piotr Wilczek
8e5e1e6a92 arm:exynos: add common DTS file for exynos 4
This patch adds common dtsi file and config header for all
Exynos 4 based boards.

Patch additionaly adds board specific (weak) functions for
board_early_init_f and board_power_init functions.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Piotr Wilczek
3577fe8be9 drivers:mmc:sdhci: enable support for DT
This patch enables support for device tree for sdhci driver.
Non DT case is still supported.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Piotr Wilczek
de461c526e video:mipidsim:fdt: Add DT support for mipi dsim driver
This patch enables parsing mipi data from device tree.
Non device tree case is still supported.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Piotr Wilczek
b8dfcdb7d3 exynos4:pinmux:fdt: decode peripheral id
This patch adds api to decode peripheral id based on interrupt number.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Tom Rini
5495dae7aa Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-03-10 14:22:54 -04:00
Ian Campbell
c6f3d50b9b ahci-plat: Provide a weak scsi_init hook
This allow the platform to register the platform ahci device.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2014-03-10 13:50:31 -04:00
Bo Shen
27019e4a94 arm: atmel: sama5d3: add nand spl boot support
Add NAND SPL boot support with hardware PMECC.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 19:19:13 +01:00
Bo Shen
8a45b0ba87 arm: atmel: sama5d3: add spi spl boot support
Add SPI SPL boot support for sama5d3xek board.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 19:18:33 +01:00
Andreas Henriksson
3ed7c4875d at91 gpio: fix typo in compatibility macro
It's called _pio_ in the version that was added to git.
Apparently it got renamed without updating the macros before it was
applied, c.f.
http://u-boot.10912.n7.nabble.com/U-Boot-PATCH-3-9-V3-add-a-new-AT91-GPIO-driver-td75922.html

Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 18:24:54 +01:00
Andreas Henriksson
81724e09a0 at91sam9263ek: add mmc support
Add support for using the Atmel MCI driver on at91sam9263ek.
This change is modeled after the existing at91sam9260ek support.

Please note that this hooks up slot1 (MCI1) for SD. Not both.

Tested with at91bootstrap and u-boot on dataflash in slot 0
and fat-formatted 8GB SDHC in slot 1 on first revision
at91sam9263ek (which must use dataflash in slot0 to boot).

CONFIG_ATMEL_MCI_PORTB not tested.

Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se>
[remove empty line]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-03-09 18:24:52 +01:00
Masahiro Yamada
388b2e520b kbuild: move "checkthumb" to ARM archprepare
"checkthumb" makes sense only for ARM architecture.
Move it to arch/arm/config.mk.

To make sure gcc supports THUMB mode before beginning build,
run "checkthumb" during "archprepare".

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-07 10:59:06 -05:00
Masahiro Yamada
cd2e46cb38 kbuild: add CONFIG_ prefix to USE_PRIVATE_LIBGCC
Before this commit, USE_PRIVATE_LIBGCC was defined in
arch-specific config.mk and referenced in
arch/$(ARCH)/lib/Makefile.

We are not happy about parsing config.mk again and again.
We have to keep the same behavior with a different way.

By adding "CONFIG_" prefix, this macro appears
in include/autoconf.mk, include/spl-autoconf.mk.
(And treating USE_PRIVATE_LIBGCC as CONFIG macro
is reasonable enough.)

Tegra SoC family defined USE_PRIVATE_LIBGCC as "yes"
in arch/arm/cpu/arm720t/tegra*/config.mk,
whereas did not define it in arch/arm/cpu/armv7/tegra*/config.mk.

It means Tegra enables PRIVATE_LIBGCC only for SPL.
We can describe the same behavior by adding

  #ifdef CONFIG_SPL_BUILD
  # define CONFIG_USE_PRIVATE_LIBGCC
  #endif

to include/configs/tegra-common.h.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-03-07 10:59:06 -05:00
Stephen Warren
716ff5ce1d ARM: tegra: simplify halt_avp()
In order to completely halt the AVP processor, we should simply write
FLOW_MODE_STOP without any extra options that allow wakeup. Amend the
code to do this.

I believe that enabling FIQ_1 and IRQ_1 allow the CPU to be awoken by
interrupts. We don't want this; if later SW wishes to use the AVP, it
should be reset and booted from scratch.

Related, the bits that were previously IRQ_1 and FIQ_1 have a slightly
different definition starting with Tegra114, so the values we're
writing don't entirely make sense there anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-05 16:59:08 -07:00
Stephen Warren
87fb553b90 ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124
Tegra124 moved the CSITE block's base address. Fix U-Boot to use
the correct address.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-05 16:59:08 -07:00
Stephen Warren
f3026c1683 ARM: tegra: fix pmc_pwrgate_timer_mult register definition
Register pmc_pwrgate_timer_mult has a different layout on Tegra114 and
Tegra124. Reflect this in pmc.h.

Also, simply write the whole of the register in start_cpu() rather than
doing a read-modify-write; the register is simple enough that the code
can easily construct the entire desired value.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-05 16:59:08 -07:00
Stephen Warren
cd7efc2a94 ARM: tegra: move CONFIG_TEGRAnn
<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize
some definitions, since some modules moved between generations. Move
the definition of CONFIG_TEGRAnn to a header that's included earlier,
so that it's set by the time tegra.h needs to use it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-05 16:59:07 -07:00
Tom Rini
e4b87e5b1d Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2014-03-04 21:23:42 -05:00