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ARM: keystone2: add K2E SoC hardware definitions
This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Hao Zhang
Tom Rini
parent
b1babef856
commit
5c76f78858
3 changed files with 105 additions and 44 deletions
44
arch/arm/include/asm/arch-keystone/hardware-k2e.h
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44
arch/arm/include/asm/arch-keystone/hardware-k2e.h
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@ -0,0 +1,44 @@
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/*
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* K2E: SoC definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2E_H
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#define __ASM_ARCH_HARDWARE_K2E_H
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/* PA SS Registers */
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#define KS2_PASS_BASE 0x24000000
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_MOD_RST 0
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#define KS2_LPSC_USB_1 1
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#define KS2_LPSC_USB 2
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#define KS2_LPSC_EMIF25_SPI 3
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#define KS2_LPSC_TSIP 4
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#define KS2_LPSC_DEBUGSS_TRC 5
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#define KS2_LPSC_TETB_TRC 6
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#define KS2_LPSC_PKTPROC 7
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#define KS2_LPSC_PA KS2_LPSC_PKTPROC
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#define KS2_LPSC_SGMII 8
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#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
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#define KS2_LPSC_CRYPTO 9
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#define KS2_LPSC_PCIE 10
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#define KS2_LPSC_VUSR0 12
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#define KS2_LPSC_CHIP_SRSS 13
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#define KS2_LPSC_MSMC 14
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#define KS2_LPSC_EMIF4F_DDR3 23
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#define KS2_LPSC_PCIE_1 27
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#define KS2_LPSC_XGE 50
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/* Chip Interrupt Controller */
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
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/* Number of DSP cores */
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#define KS2_NUM_DSPS 1
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#endif
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@ -10,46 +10,16 @@
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#ifndef __ASM_ARCH_HARDWARE_K2HK_H
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#define __ASM_ARCH_HARDWARE_K2HK_H
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#define KS2_PLL_CNTRL_BASE 0x02310000
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#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
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#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL_KEY 0x5a69
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#define KS2_RSTCTRL_MASK 0xffff0000
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#define KS2_RSTCTRL_SWRST 0xfffe0000
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#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
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#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
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#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
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#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
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#define KS2_ARM_PLL_EN BIT(13)
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#define KS2_SPI0_BASE 0x21000400
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#define KS2_SPI1_BASE 0x21000600
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#define KS2_SPI2_BASE 0x21000800
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#define KS2_SPI_BASE KS2_SPI0_BASE
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/* Chip configuration unlock codes and registers */
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#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
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#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
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#define KS2_KICK0_MAGIC 0x83e70b13
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#define KS2_KICK1_MAGIC 0x95a4f1e0
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/* PA SS Registers */
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#define KS2_PASS_BASE 0x02000000
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/* PLL control registers */
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#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
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#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
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#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
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#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
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#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
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#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
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#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
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#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
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#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
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#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_MOD 0
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@ -106,25 +76,11 @@
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#define KS2_LPSC_XGE 50
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#define KS2_LPSC_ARM_SREFLEX 51
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/* DDR3A definitions */
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#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
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#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
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#define KS2_DDR3A_DDRPHYC 0x02329000
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/* DDR3B definitions */
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#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
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#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
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#define KS2_DDR3B_DDRPHYC 0x02328000
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/* Queue manager */
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#define KS2_QM_MANAGER_BASE 0x02a02000
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#define KS2_QM_DESC_SETUP_BASE 0x02a03000
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#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
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#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
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#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
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/* MSMC control */
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#define KS2_MSMC_CTRL_BASE 0x0bc00000
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/* Number of DSP cores */
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#define KS2_NUM_DSPS 8
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@ -69,6 +69,11 @@ typedef volatile unsigned int *dv_reg_p;
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#define NOSRA_MASK 0x08000000
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#define ECC_MASK 0x00000001
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/* DDR3 definitions */
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#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
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#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
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#define KS2_DDR3A_DDRPHYC 0x02329000
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#define KS2_DDR3_MIDR_OFFSET 0x00
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#define KS2_DDR3_STATUS_OFFSET 0x04
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#define KS2_DDR3_SDCFG_OFFSET 0x08
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@ -85,12 +90,46 @@ typedef volatile unsigned int *dv_reg_p;
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#define KS2_UART0_BASE 0x02530c00
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#define KS2_UART1_BASE 0x02531000
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/* Boot Config */
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#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
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#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
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#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
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/* PSC */
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#define KS2_PSC_BASE 0x02350000
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#define KS2_LPSC_GEM_0 15
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#define KS2_LPSC_TETRIS 52
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#define KS2_TETRIS_PWR_DOMAIN 31
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/* Chip configuration unlock codes and registers */
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#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
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#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
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#define KS2_KICK0_MAGIC 0x83e70b13
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#define KS2_KICK1_MAGIC 0x95a4f1e0
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/* PLL control registers */
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#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
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#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
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#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
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#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
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#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
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#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
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#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
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#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
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#define KS2_PLL_CNTRL_BASE 0x02310000
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#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
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#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL_KEY 0x5a69
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#define KS2_RSTCTRL_MASK 0xffff0000
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#define KS2_RSTCTRL_SWRST 0xfffe0000
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/* SPI */
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#define KS2_SPI0_BASE 0x21000400
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#define KS2_SPI1_BASE 0x21000600
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#define KS2_SPI2_BASE 0x21000800
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#define KS2_SPI_BASE KS2_SPI0_BASE
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/* AEMIF */
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#define KS2_AEMIF_CNTRL_BASE 0x21000a00
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
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@ -98,10 +137,24 @@ typedef volatile unsigned int *dv_reg_p;
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/* Flag from ks2_debug options to check if DSPs need to stay ON */
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#define DBG_LEAVE_DSPS_ON 0x1
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/* Queue manager */
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#define KS2_QM_MANAGER_BASE 0x02a02000
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#define KS2_QM_DESC_SETUP_BASE 0x02a03000
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#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
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#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
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#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
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/* MSMC control */
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#define KS2_MSMC_CTRL_BASE 0x0bc00000
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/hardware-k2hk.h>
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#endif
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#ifdef CONFIG_SOC_K2E
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#include <asm/arch/hardware-k2e.h>
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#endif
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#ifndef __ASSEMBLY__
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static inline int cpu_is_k2hk(void)
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{
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@ -111,6 +164,14 @@ static inline int cpu_is_k2hk(void)
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return (part_no == 0xb981) ? 1 : 0;
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}
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static inline int cpu_is_k2e(void)
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{
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unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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unsigned int part_no = (jtag_id >> 12) & 0xffff;
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return (part_no == 0xb9a6) ? 1 : 0;
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}
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static inline int cpu_revision(void)
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{
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unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
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