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sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'

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It is going to be useful in more than one place.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Siarhei Siamashka 2014-08-03 05:32:50 +03:00 committed by Hans de Goede
parent b8f7cb6ae3
commit e044daa33e
2 changed files with 16 additions and 14 deletions
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27
arch/arm/cpu/armv7/sunxi/dram.c
View file

@ -152,23 +152,28 @@ static void mctl_enable_dll0(u32 phase)
udelay(22);
}
/* Get the number of DDR byte lanes */
static u32 mctl_get_number_of_lanes(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
return 4;
else
return 2;
}
/*
* Note: This differs from pm/standby in that it checks the bus width
*/
static void mctl_enable_dllx(u32 phase)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 i, n, bus_width;
u32 i, number_of_lanes;
bus_width = readl(&dram->dcr);
number_of_lanes = mctl_get_number_of_lanes();
if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
n = DRAM_DCR_NR_DLLCR_32BIT;
else
n = DRAM_DCR_NR_DLLCR_16BIT;
for (i = 1; i < n; i++) {
for (i = 1; i <= number_of_lanes; i++) {
clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
(phase & 0xf) << 14);
clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
@ -177,12 +182,12 @@ static void mctl_enable_dllx(u32 phase)
}
udelay(2);
for (i = 1; i < n; i++)
for (i = 1; i <= number_of_lanes; i++)
clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
DRAM_DLLCR_DISABLE);
udelay(22);
for (i = 1; i < n; i++)
for (i = 1; i <= number_of_lanes; i++)
clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
DRAM_DLLCR_NRESET);
udelay(22);

3
arch/arm/include/asm/arch-sunxi/dram.h
View file

@ -122,9 +122,6 @@ struct dram_para {
#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
#define DRAM_DCR_NR_DLLCR_32BIT 5
#define DRAM_DCR_NR_DLLCR_16BIT 3
#define DRAM_DCR_NR_DLLCR_8BIT 2
#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)