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Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner <stefan@agner.ch> |
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cpu | ||
dts | ||
imx-common | ||
include/asm | ||
lib | ||
config.mk |