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usb: tegra: fix PHY configuration

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On Tegra30 and later, the PTS (parallel transceiver select) and STS
(serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
rather than PORTSC1_0 register. Since the reset configuration
usually matches the intended configuration, this error did not show
up on Tegra30 devices.

Also use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stefan Agner 2014-03-02 19:46:49 +01:00 committed by Tom Warren
parent b03f4b3742
commit b1d615f3f1
3 changed files with 27 additions and 9 deletions
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5
arch/arm/include/asm/arch-tegra/usb.h
View file

@ -91,11 +91,6 @@
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1 (1 << 3)
/* PORTSC1, USB1, defined for Tegra20 */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
#define PTS_UTMI 0
#define PTS_RESERVED 1
#define PTS_ULPI 2

7
arch/arm/include/asm/arch-tegra20/usb.h
View file

@ -147,9 +147,14 @@ struct usb_ctlr {
#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
/* PORTSC1, USB1 */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
/* PORTSC, USB2, USB3 */
#define PTS_SHIFT 30
#define PTS_MASK (3U << PTS_SHIFT)
#define STS (1 << 29)
#endif /* _TEGRA20_USB_H_ */

24
drivers/usb/host/ehci-tegra.c
View file

@ -486,9 +486,21 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
#if defined(CONFIG_TEGRA20)
if (config->periph_id == PERIPH_ID_USBD) {
clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
PTS_UTMI << PTS1_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS1);
} else {
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
}
#else
clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
clrbits_le32(&usbctlr->hostpc1_devlc, STS);
#endif
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
@ -546,7 +558,13 @@ static int init_ulpi_usb_controller(struct fdt_usb *config)
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
#if defined(CONFIG_TEGRA20)
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
PTS_ULPI << PTS_SHIFT);
#else
clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
PTS_ULPI << PTS_SHIFT);
#endif
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);