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ARM: tegra: pinctrl: remove vddio
This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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0d2c0d5788
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8 changed files with 0 additions and 86 deletions
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@ -24,7 +24,6 @@
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struct tegra_pingroup_desc {
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const char *name;
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enum pmux_func funcs[4];
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enum pmux_vddio vddio;
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enum pmux_pin_io io;
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};
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@ -54,7 +53,6 @@ struct tegra_pingroup_desc {
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/* Convenient macro for defining pin group properties */
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#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
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{ \
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.vddio = PMUX_VDDIO_ ## vdd, \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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@ -15,7 +15,6 @@
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struct tegra_pingroup_desc {
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const char *name;
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enum pmux_func funcs[4];
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enum pmux_vddio vddio;
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enum pmux_pin_io io;
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};
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@ -45,7 +44,6 @@ struct tegra_pingroup_desc {
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/* Convenient macro for defining pin group properties */
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#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
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{ \
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.vddio = PMUX_VDDIO_ ## vdd, \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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@ -259,7 +259,6 @@ enum pmux_pullid {
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struct tegra_pingroup_desc {
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const char *name;
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enum pmux_func funcs[4];
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enum pmux_vddio vddio;
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enum pmux_ctlid ctl_id;
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enum pmux_pullid pull_id;
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};
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@ -286,7 +285,6 @@ struct tegra_pingroup_desc {
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/* Convenient macro for defining pin group properties */
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#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
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{ \
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.vddio = PMUX_VDDIO_ ## vdd, \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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@ -24,7 +24,6 @@
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struct tegra_pingroup_desc {
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const char *name;
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enum pmux_func funcs[4];
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enum pmux_vddio vddio;
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enum pmux_pin_io io;
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};
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@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
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/* Convenient macro for defining pin group properties */
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#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
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{ \
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.vddio = PMUX_VDDIO_ ## vdd, \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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@ -449,27 +449,6 @@ enum pmux_pin_rcv_sel {
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(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
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((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
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/* Available power domains used by pin groups */
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enum pmux_vddio {
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PMUX_VDDIO_BB = 0,
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PMUX_VDDIO_LCD,
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PMUX_VDDIO_VI,
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PMUX_VDDIO_UART,
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PMUX_VDDIO_DDR,
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PMUX_VDDIO_NAND,
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PMUX_VDDIO_SYS,
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PMUX_VDDIO_AUDIO,
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PMUX_VDDIO_SD,
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PMUX_VDDIO_CAM,
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PMUX_VDDIO_GMI,
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PMUX_VDDIO_PEXCTL,
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PMUX_VDDIO_SDMMC1,
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PMUX_VDDIO_SDMMC3,
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PMUX_VDDIO_SDMMC4,
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PMUX_VDDIO_NONE
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};
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#define PGRP_SLWF_NONE -1
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#define PGRP_SLWF_MAX 3
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#define PGRP_SLWR_NONE PGRP_SLWF_NONE
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@ -458,27 +458,6 @@ enum pmux_pin_rcv_sel {
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(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
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((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
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/* Available power domains used by pin groups */
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enum pmux_vddio {
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PMUX_VDDIO_BB = 0,
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PMUX_VDDIO_LCD,
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PMUX_VDDIO_VI,
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PMUX_VDDIO_UART,
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PMUX_VDDIO_DDR,
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PMUX_VDDIO_NAND,
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PMUX_VDDIO_SYS,
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PMUX_VDDIO_AUDIO,
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PMUX_VDDIO_SD,
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PMUX_VDDIO_CAM,
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PMUX_VDDIO_GMI,
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PMUX_VDDIO_PEXCTL,
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PMUX_VDDIO_SDMMC1,
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PMUX_VDDIO_SDMMC3,
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PMUX_VDDIO_SDMMC4,
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PMUX_VDDIO_NONE
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};
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#define PGRP_SLWF_NONE -1
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#define PGRP_SLWF_MAX 3
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#define PGRP_SLWR_NONE PGRP_SLWF_NONE
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@ -257,21 +257,6 @@ enum pmux_tristate {
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PMUX_TRI_TRISTATE = 1,
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};
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/* Available power domains used by pin groups */
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enum pmux_vddio {
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PMUX_VDDIO_BB = 0,
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PMUX_VDDIO_LCD,
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PMUX_VDDIO_VI,
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PMUX_VDDIO_UART,
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PMUX_VDDIO_DDR,
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PMUX_VDDIO_NAND,
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PMUX_VDDIO_SYS,
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PMUX_VDDIO_AUDIO,
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PMUX_VDDIO_SD,
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PMUX_VDDIO_NONE
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};
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enum {
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PMUX_TRISTATE_REGS = 4,
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PMUX_MUX_REGS = 7,
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@ -509,27 +509,6 @@ enum pmux_pin_ioreset {
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(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
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((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
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/* Available power domains used by pin groups */
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enum pmux_vddio {
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PMUX_VDDIO_BB = 0,
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PMUX_VDDIO_LCD,
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PMUX_VDDIO_VI,
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PMUX_VDDIO_UART,
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PMUX_VDDIO_DDR,
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PMUX_VDDIO_NAND,
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PMUX_VDDIO_SYS,
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PMUX_VDDIO_AUDIO,
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PMUX_VDDIO_SD,
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PMUX_VDDIO_CAM,
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PMUX_VDDIO_GMI,
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PMUX_VDDIO_PEXCTL,
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PMUX_VDDIO_SDMMC1,
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PMUX_VDDIO_SDMMC3,
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PMUX_VDDIO_SDMMC4,
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PMUX_VDDIO_NONE
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};
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#define PGRP_SLWF_NONE -1
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#define PGRP_SLWF_MAX 3
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#define PGRP_SLWR_NONE PGRP_SLWF_NONE
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