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sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i
The older differences were likely justified by the need to mitigate the CKE delay timing violations on sun4i/sun5i. The CKE problem is already resolved, so now we can use the sun7i variant of this code everywhere. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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1 changed files with 0 additions and 11 deletions
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@ -446,10 +446,6 @@ unsigned long dramc_init(struct dram_para *para)
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/* Disable any pad power save control */
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mctl_disable_power_save();
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/* reset external DRAM */
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#ifndef CONFIG_SUN7I
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mctl_ddr3_reset();
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#endif
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mctl_set_drive();
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/* dram clock off */
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@ -491,18 +487,11 @@ unsigned long dramc_init(struct dram_para *para)
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reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
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writel(reg_val, &dram->dcr);
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#ifdef CONFIG_SUN7I
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dramc_clock_output_en(1);
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#endif
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mctl_set_cke_delay();
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#ifdef CONFIG_SUN7I
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mctl_ddr3_reset();
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#else
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/* dram clock on */
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dramc_clock_output_en(1);
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#endif
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udelay(1);
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