mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
parent
c19e0dd741
commit
800c83522c
1 changed files with 1 additions and 0 deletions
|
@ -46,6 +46,7 @@ _secure_monitor:
|
|||
#endif
|
||||
|
||||
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
|
||||
isb
|
||||
|
||||
#ifdef CONFIG_ARMV7_VIRT
|
||||
mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
|
||||
|
|
Loading…
Reference in a new issue