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ARM: tegra: Tegra114 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren
Tom Warren
parent
803d01edc2
commit
1fa3a63413
5 changed files with 669 additions and 742 deletions
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@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void)
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debug("enable_cpu_power_rail entry\n");
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/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
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pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
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pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
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pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
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pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
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/*
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* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
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@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config)
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case PERIPH_ID_UART4:
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switch (config) {
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case FUNCMUX_UART4_GMI:
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pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
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pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
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pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
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pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
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PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
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PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
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PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
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PMUX_FUNC_UARTD);
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pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
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pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
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pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
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pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
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pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
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pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
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pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
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pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
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pinmux_tristate_disable(PINGRP_GMI_A16);
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pinmux_tristate_disable(PINGRP_GMI_A17);
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pinmux_tristate_disable(PINGRP_GMI_A18);
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pinmux_tristate_disable(PINGRP_GMI_A19);
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pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
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pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
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pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
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pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
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break;
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}
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break;
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@ -1,78 +1,57 @@
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra114 pin multiplexing functions */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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/* Convenient macro for defining pin group properties */
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#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
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{ \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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PMUX_FUNC_ ## f2, \
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PMUX_FUNC_ ## f3, \
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}, \
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#define PIN(pin, f0, f1, f2, f3) \
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{ \
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.funcs = { \
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PMUX_FUNC_##f0, \
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PMUX_FUNC_##f1, \
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PMUX_FUNC_##f2, \
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PMUX_FUNC_##f3, \
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}, \
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}
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/* Input and output pins */
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#define PINI(pg_name, vdd, f0, f1, f2, f3) \
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PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
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#define PINO(pg_name, vdd, f0, f1, f2, f3) \
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PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
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#define PIN_RESERVED {}
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/* A pin group number which is not used */
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#define PIN_RESERVED \
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PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
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static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
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/* NAME VDD f0 f1 f2 f3 */
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PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
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PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
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PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
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PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
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PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
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PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
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PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
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PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
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PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
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PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
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PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
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PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
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PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
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PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
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PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
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PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
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PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
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PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
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PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
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PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
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PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
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PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
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PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
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PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
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PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
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static const struct pmux_pingrp_desc tegra114_pingroups[] = {
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/* pin, f0, f1, f2, f3 */
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/* Offset 0x3000 */
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PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
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PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
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PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
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PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
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PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
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PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
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PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
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PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
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PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
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PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
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PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
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PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
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PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
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PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
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PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB),
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PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB),
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PIN(PV0, USB, RSVD2, RSVD3, RSVD4),
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PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
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PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
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PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
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PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
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PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
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PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
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PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
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PIN_RESERVED,
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PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
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PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
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PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
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PIN_RESERVED,
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/* Offset 0x3068 */
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PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
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PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
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PIN_RESERVED,
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PIN_RESERVED,
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PIN_RESERVED,
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@ -111,12 +90,12 @@ static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
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PIN_RESERVED,
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PIN_RESERVED,
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PIN_RESERVED,
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PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
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PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
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PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
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PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
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PIN_RESERVED,
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PIN_RESERVED,
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/* Offset 0x3110 */
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PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
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PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
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PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
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PIN_RESERVED,
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PIN_RESERVED,
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PIN_RESERVED,
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@ -132,175 +111,183 @@ static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
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PIN_RESERVED,
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PIN_RESERVED,
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PIN_RESERVED,
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PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
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PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
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PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
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PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
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PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
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PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
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PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
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PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
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PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
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PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
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PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
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PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
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PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
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PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
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PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
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PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
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PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
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PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
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PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
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PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
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PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
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PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
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PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
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PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
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PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
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PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
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PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
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PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
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PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
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PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
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PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
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PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
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PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
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PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
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PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
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PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
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PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
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PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
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PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
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PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
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PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
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PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
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PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
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PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
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PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
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PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
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PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
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PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
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PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
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PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
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PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
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PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
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PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
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PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
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PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
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PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
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PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
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PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
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PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
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PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
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PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
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PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
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PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
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PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
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PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
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PIN_RESERVED, /* Reserved by t114: 0x3280 */
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PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
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PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
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PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
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PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
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PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
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PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
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PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
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PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
|
||||
PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
|
||||
PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
|
||||
PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
|
||||
PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
|
||||
PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
|
||||
PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
|
||||
PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
|
||||
PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
|
||||
PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
|
||||
PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
|
||||
PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
|
||||
PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
|
||||
PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
|
||||
PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
|
||||
PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
|
||||
PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
|
||||
PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
|
||||
PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
|
||||
PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
|
||||
PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
|
||||
PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
|
||||
PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
|
||||
PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
|
||||
PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
|
||||
PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
|
||||
PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
|
||||
PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
|
||||
PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
|
||||
PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
|
||||
PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
|
||||
PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
|
||||
PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
|
||||
PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
|
||||
PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
|
||||
PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
|
||||
PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
|
||||
PIN_RESERVED,
|
||||
PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
|
||||
PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
|
||||
PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
|
||||
PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
|
||||
PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
|
||||
PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
|
||||
PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
|
||||
PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
|
||||
PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
|
||||
PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
|
||||
PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
|
||||
PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
|
||||
PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
|
||||
PIN_RESERVED, /* Reserved by t114: 0x3404 */
|
||||
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x3164 */
|
||||
PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
|
||||
PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
|
||||
PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4),
|
||||
PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4),
|
||||
PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4),
|
||||
PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4),
|
||||
PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
|
||||
PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA),
|
||||
PIN(PU0, OWR, UARTA, RSVD3, RSVD4),
|
||||
PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4),
|
||||
PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4),
|
||||
PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB),
|
||||
PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB),
|
||||
PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB),
|
||||
PIN(PU6, PWM3, UARTA, USB, DISPLAYB),
|
||||
PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
|
||||
PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
|
||||
PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4),
|
||||
PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4),
|
||||
PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4),
|
||||
PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4),
|
||||
PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
|
||||
PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
|
||||
PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
|
||||
PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE),
|
||||
PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
|
||||
PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
|
||||
PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
|
||||
PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
|
||||
PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
|
||||
PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
|
||||
PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
|
||||
PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
|
||||
PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
|
||||
PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2),
|
||||
PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4),
|
||||
PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4),
|
||||
PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4),
|
||||
PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV),
|
||||
PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS),
|
||||
PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS),
|
||||
PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB),
|
||||
PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4),
|
||||
PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV),
|
||||
PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV),
|
||||
PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT),
|
||||
PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE),
|
||||
PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE),
|
||||
PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE),
|
||||
PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4),
|
||||
PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC),
|
||||
PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE),
|
||||
PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
|
||||
PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
|
||||
PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
|
||||
PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
|
||||
PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x3284 */
|
||||
PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4),
|
||||
PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3),
|
||||
PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4),
|
||||
PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4),
|
||||
PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4),
|
||||
PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4),
|
||||
PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4),
|
||||
PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4),
|
||||
PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
|
||||
PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
|
||||
PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
|
||||
PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
|
||||
PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
|
||||
PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
|
||||
PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB),
|
||||
PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB),
|
||||
PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB),
|
||||
PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
|
||||
PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
|
||||
PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
|
||||
PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
|
||||
PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x32fc */
|
||||
PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL),
|
||||
PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL),
|
||||
PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
|
||||
PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
|
||||
PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
|
||||
PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
|
||||
PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4),
|
||||
PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4),
|
||||
PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
|
||||
PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
|
||||
PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
|
||||
PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
|
||||
PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
|
||||
PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
|
||||
PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
|
||||
PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
|
||||
PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
|
||||
PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4),
|
||||
PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
|
||||
PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4),
|
||||
PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
|
||||
PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4),
|
||||
PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4),
|
||||
PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4),
|
||||
PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4),
|
||||
PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4),
|
||||
PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4),
|
||||
PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4),
|
||||
PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4),
|
||||
PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4),
|
||||
PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4),
|
||||
PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2),
|
||||
PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4),
|
||||
PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4),
|
||||
PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x3390 */
|
||||
PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
|
||||
PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
|
||||
PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
|
||||
PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
|
||||
PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
|
||||
PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x33e0 */
|
||||
PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC),
|
||||
PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
|
||||
PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
|
||||
PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
|
||||
PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
|
||||
PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
|
||||
PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
|
||||
PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
|
||||
PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
|
||||
PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4),
|
||||
PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
|
||||
};
|
||||
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
|
||||
|
|
|
|||
|
|
@ -1,375 +1,311 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_PINMUX_H_
|
||||
#define _TEGRA114_PINMUX_H_
|
||||
|
||||
/*
|
||||
* Pin groups which we adjust. There are three basic attributes of each pin
|
||||
* group which use this enum:
|
||||
*
|
||||
* - function
|
||||
* - pullup / pulldown
|
||||
* - tristate or normal
|
||||
*/
|
||||
enum pmux_pingrp {
|
||||
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
|
||||
PINGRP_ULPI_DATA1,
|
||||
PINGRP_ULPI_DATA2,
|
||||
PINGRP_ULPI_DATA3,
|
||||
PINGRP_ULPI_DATA4,
|
||||
PINGRP_ULPI_DATA5,
|
||||
PINGRP_ULPI_DATA6,
|
||||
PINGRP_ULPI_DATA7,
|
||||
PINGRP_ULPI_CLK,
|
||||
PINGRP_ULPI_DIR,
|
||||
PINGRP_ULPI_NXT,
|
||||
PINGRP_ULPI_STP,
|
||||
PINGRP_DAP3_FS,
|
||||
PINGRP_DAP3_DIN,
|
||||
PINGRP_DAP3_DOUT,
|
||||
PINGRP_DAP3_SCLK,
|
||||
PINGRP_GPIO_PV0,
|
||||
PINGRP_GPIO_PV1,
|
||||
PINGRP_SDMMC1_CLK,
|
||||
PINGRP_SDMMC1_CMD,
|
||||
PINGRP_SDMMC1_DAT3,
|
||||
PINGRP_SDMMC1_DAT2,
|
||||
PINGRP_SDMMC1_DAT1,
|
||||
PINGRP_SDMMC1_DAT0,
|
||||
PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
|
||||
PINGRP_CLK2_REQ,
|
||||
PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
|
||||
PINGRP_DDC_SCL,
|
||||
PINGRP_DDC_SDA,
|
||||
PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
|
||||
PINGRP_UART2_TXD,
|
||||
PINGRP_UART2_RTS_N,
|
||||
PINGRP_UART2_CTS_N,
|
||||
PINGRP_UART3_TXD,
|
||||
PINGRP_UART3_RXD,
|
||||
PINGRP_UART3_CTS_N,
|
||||
PINGRP_UART3_RTS_N,
|
||||
PINGRP_GPIO_PU0,
|
||||
PINGRP_GPIO_PU1,
|
||||
PINGRP_GPIO_PU2,
|
||||
PINGRP_GPIO_PU3,
|
||||
PINGRP_GPIO_PU4,
|
||||
PINGRP_GPIO_PU5,
|
||||
PINGRP_GPIO_PU6,
|
||||
PINGRP_GEN1_I2C_SDA,
|
||||
PINGRP_GEN1_I2C_SCL,
|
||||
PINGRP_DAP4_FS,
|
||||
PINGRP_DAP4_DIN,
|
||||
PINGRP_DAP4_DOUT,
|
||||
PINGRP_DAP4_SCLK,
|
||||
PINGRP_CLK3_OUT,
|
||||
PINGRP_CLK3_REQ,
|
||||
PINGRP_GMI_WP_N,
|
||||
PINGRP_GMI_IORDY,
|
||||
PINGRP_GMI_WAIT,
|
||||
PINGRP_GMI_ADV_N,
|
||||
PINGRP_GMI_CLK,
|
||||
PINGRP_GMI_CS0_N,
|
||||
PINGRP_GMI_CS1_N,
|
||||
PINGRP_GMI_CS2_N,
|
||||
PINGRP_GMI_CS3_N,
|
||||
PINGRP_GMI_CS4_N,
|
||||
PINGRP_GMI_CS6_N,
|
||||
PINGRP_GMI_CS7_N,
|
||||
PINGRP_GMI_AD0,
|
||||
PINGRP_GMI_AD1,
|
||||
PINGRP_GMI_AD2,
|
||||
PINGRP_GMI_AD3,
|
||||
PINGRP_GMI_AD4,
|
||||
PINGRP_GMI_AD5,
|
||||
PINGRP_GMI_AD6,
|
||||
PINGRP_GMI_AD7,
|
||||
PINGRP_GMI_AD8,
|
||||
PINGRP_GMI_AD9,
|
||||
PINGRP_GMI_AD10,
|
||||
PINGRP_GMI_AD11,
|
||||
PINGRP_GMI_AD12,
|
||||
PINGRP_GMI_AD13,
|
||||
PINGRP_GMI_AD14,
|
||||
PINGRP_GMI_AD15,
|
||||
PINGRP_GMI_A16,
|
||||
PINGRP_GMI_A17,
|
||||
PINGRP_GMI_A18,
|
||||
PINGRP_GMI_A19,
|
||||
PINGRP_GMI_WR_N,
|
||||
PINGRP_GMI_OE_N,
|
||||
PINGRP_GMI_DQS,
|
||||
PINGRP_GMI_RST_N,
|
||||
PINGRP_GEN2_I2C_SCL,
|
||||
PINGRP_GEN2_I2C_SDA,
|
||||
PINGRP_SDMMC4_CLK,
|
||||
PINGRP_SDMMC4_CMD,
|
||||
PINGRP_SDMMC4_DAT0,
|
||||
PINGRP_SDMMC4_DAT1,
|
||||
PINGRP_SDMMC4_DAT2,
|
||||
PINGRP_SDMMC4_DAT3,
|
||||
PINGRP_SDMMC4_DAT4,
|
||||
PINGRP_SDMMC4_DAT5,
|
||||
PINGRP_SDMMC4_DAT6,
|
||||
PINGRP_SDMMC4_DAT7,
|
||||
PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
|
||||
PINGRP_GPIO_PCC1,
|
||||
PINGRP_GPIO_PBB0,
|
||||
PINGRP_CAM_I2C_SCL,
|
||||
PINGRP_CAM_I2C_SDA,
|
||||
PINGRP_GPIO_PBB3,
|
||||
PINGRP_GPIO_PBB4,
|
||||
PINGRP_GPIO_PBB5,
|
||||
PINGRP_GPIO_PBB6,
|
||||
PINGRP_GPIO_PBB7,
|
||||
PINGRP_GPIO_PCC2,
|
||||
PINGRP_JTAG_RTCK,
|
||||
PINGRP_PWR_I2C_SCL,
|
||||
PINGRP_PWR_I2C_SDA,
|
||||
PINGRP_KB_ROW0,
|
||||
PINGRP_KB_ROW1,
|
||||
PINGRP_KB_ROW2,
|
||||
PINGRP_KB_ROW3,
|
||||
PINGRP_KB_ROW4,
|
||||
PINGRP_KB_ROW5,
|
||||
PINGRP_KB_ROW6,
|
||||
PINGRP_KB_ROW7,
|
||||
PINGRP_KB_ROW8,
|
||||
PINGRP_KB_ROW9,
|
||||
PINGRP_KB_ROW10,
|
||||
PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
|
||||
PINGRP_KB_COL1,
|
||||
PINGRP_KB_COL2,
|
||||
PINGRP_KB_COL3,
|
||||
PINGRP_KB_COL4,
|
||||
PINGRP_KB_COL5,
|
||||
PINGRP_KB_COL6,
|
||||
PINGRP_KB_COL7,
|
||||
PINGRP_CLK_32K_OUT,
|
||||
PINGRP_SYS_CLK_REQ,
|
||||
PINGRP_CORE_PWR_REQ,
|
||||
PINGRP_CPU_PWR_REQ,
|
||||
PINGRP_PWR_INT_N,
|
||||
PINGRP_CLK_32K_IN,
|
||||
PINGRP_OWR,
|
||||
PINGRP_DAP1_FS,
|
||||
PINGRP_DAP1_DIN,
|
||||
PINGRP_DAP1_DOUT,
|
||||
PINGRP_DAP1_SCLK,
|
||||
PINGRP_CLK1_REQ,
|
||||
PINGRP_CLK1_OUT,
|
||||
PINGRP_SPDIF_IN,
|
||||
PINGRP_SPDIF_OUT,
|
||||
PINGRP_DAP2_FS,
|
||||
PINGRP_DAP2_DIN,
|
||||
PINGRP_DAP2_DOUT,
|
||||
PINGRP_DAP2_SCLK,
|
||||
PINGRP_DVFS_PWM,
|
||||
PINGRP_GPIO_X1_AUD,
|
||||
PINGRP_GPIO_X3_AUD,
|
||||
PINGRP_DVFS_CLK,
|
||||
PINGRP_GPIO_X4_AUD,
|
||||
PINGRP_GPIO_X5_AUD,
|
||||
PINGRP_GPIO_X6_AUD,
|
||||
PINGRP_GPIO_X7_AUD,
|
||||
PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
|
||||
PINGRP_SDMMC3_CMD,
|
||||
PINGRP_SDMMC3_DAT0,
|
||||
PINGRP_SDMMC3_DAT1,
|
||||
PINGRP_SDMMC3_DAT2,
|
||||
PINGRP_SDMMC3_DAT3,
|
||||
PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
|
||||
PINGRP_SDMMC1_WP_N,
|
||||
PINGRP_SDMMC3_CD_N,
|
||||
PINGRP_GPIO_W2_AUD,
|
||||
PINGRP_GPIO_W3_AUD,
|
||||
PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
|
||||
PINGRP_USB_VBUS_EN1,
|
||||
PINGRP_SDMMC3_CLK_LB_IN,
|
||||
PINGRP_SDMMC3_CLK_LB_OUT,
|
||||
PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
|
||||
PMUX_PINGRP_ULPI_DATA0_PO1,
|
||||
PMUX_PINGRP_ULPI_DATA1_PO2,
|
||||
PMUX_PINGRP_ULPI_DATA2_PO3,
|
||||
PMUX_PINGRP_ULPI_DATA3_PO4,
|
||||
PMUX_PINGRP_ULPI_DATA4_PO5,
|
||||
PMUX_PINGRP_ULPI_DATA5_PO6,
|
||||
PMUX_PINGRP_ULPI_DATA6_PO7,
|
||||
PMUX_PINGRP_ULPI_DATA7_PO0,
|
||||
PMUX_PINGRP_ULPI_CLK_PY0,
|
||||
PMUX_PINGRP_ULPI_DIR_PY1,
|
||||
PMUX_PINGRP_ULPI_NXT_PY2,
|
||||
PMUX_PINGRP_ULPI_STP_PY3,
|
||||
PMUX_PINGRP_DAP3_FS_PP0,
|
||||
PMUX_PINGRP_DAP3_DIN_PP1,
|
||||
PMUX_PINGRP_DAP3_DOUT_PP2,
|
||||
PMUX_PINGRP_DAP3_SCLK_PP3,
|
||||
PMUX_PINGRP_PV0,
|
||||
PMUX_PINGRP_PV1,
|
||||
PMUX_PINGRP_SDMMC1_CLK_PZ0,
|
||||
PMUX_PINGRP_SDMMC1_CMD_PZ1,
|
||||
PMUX_PINGRP_SDMMC1_DAT3_PY4,
|
||||
PMUX_PINGRP_SDMMC1_DAT2_PY5,
|
||||
PMUX_PINGRP_SDMMC1_DAT1_PY6,
|
||||
PMUX_PINGRP_SDMMC1_DAT0_PY7,
|
||||
PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
|
||||
PMUX_PINGRP_CLK2_REQ_PCC5,
|
||||
PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
|
||||
PMUX_PINGRP_DDC_SCL_PV4,
|
||||
PMUX_PINGRP_DDC_SDA_PV5,
|
||||
PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
|
||||
PMUX_PINGRP_UART2_TXD_PC2,
|
||||
PMUX_PINGRP_UART2_RTS_N_PJ6,
|
||||
PMUX_PINGRP_UART2_CTS_N_PJ5,
|
||||
PMUX_PINGRP_UART3_TXD_PW6,
|
||||
PMUX_PINGRP_UART3_RXD_PW7,
|
||||
PMUX_PINGRP_UART3_CTS_N_PA1,
|
||||
PMUX_PINGRP_UART3_RTS_N_PC0,
|
||||
PMUX_PINGRP_PU0,
|
||||
PMUX_PINGRP_PU1,
|
||||
PMUX_PINGRP_PU2,
|
||||
PMUX_PINGRP_PU3,
|
||||
PMUX_PINGRP_PU4,
|
||||
PMUX_PINGRP_PU5,
|
||||
PMUX_PINGRP_PU6,
|
||||
PMUX_PINGRP_GEN1_I2C_SDA_PC5,
|
||||
PMUX_PINGRP_GEN1_I2C_SCL_PC4,
|
||||
PMUX_PINGRP_DAP4_FS_PP4,
|
||||
PMUX_PINGRP_DAP4_DIN_PP5,
|
||||
PMUX_PINGRP_DAP4_DOUT_PP6,
|
||||
PMUX_PINGRP_DAP4_SCLK_PP7,
|
||||
PMUX_PINGRP_CLK3_OUT_PEE0,
|
||||
PMUX_PINGRP_CLK3_REQ_PEE1,
|
||||
PMUX_PINGRP_GMI_WP_N_PC7,
|
||||
PMUX_PINGRP_GMI_IORDY_PI5,
|
||||
PMUX_PINGRP_GMI_WAIT_PI7,
|
||||
PMUX_PINGRP_GMI_ADV_N_PK0,
|
||||
PMUX_PINGRP_GMI_CLK_PK1,
|
||||
PMUX_PINGRP_GMI_CS0_N_PJ0,
|
||||
PMUX_PINGRP_GMI_CS1_N_PJ2,
|
||||
PMUX_PINGRP_GMI_CS2_N_PK3,
|
||||
PMUX_PINGRP_GMI_CS3_N_PK4,
|
||||
PMUX_PINGRP_GMI_CS4_N_PK2,
|
||||
PMUX_PINGRP_GMI_CS6_N_PI3,
|
||||
PMUX_PINGRP_GMI_CS7_N_PI6,
|
||||
PMUX_PINGRP_GMI_AD0_PG0,
|
||||
PMUX_PINGRP_GMI_AD1_PG1,
|
||||
PMUX_PINGRP_GMI_AD2_PG2,
|
||||
PMUX_PINGRP_GMI_AD3_PG3,
|
||||
PMUX_PINGRP_GMI_AD4_PG4,
|
||||
PMUX_PINGRP_GMI_AD5_PG5,
|
||||
PMUX_PINGRP_GMI_AD6_PG6,
|
||||
PMUX_PINGRP_GMI_AD7_PG7,
|
||||
PMUX_PINGRP_GMI_AD8_PH0,
|
||||
PMUX_PINGRP_GMI_AD9_PH1,
|
||||
PMUX_PINGRP_GMI_AD10_PH2,
|
||||
PMUX_PINGRP_GMI_AD11_PH3,
|
||||
PMUX_PINGRP_GMI_AD12_PH4,
|
||||
PMUX_PINGRP_GMI_AD13_PH5,
|
||||
PMUX_PINGRP_GMI_AD14_PH6,
|
||||
PMUX_PINGRP_GMI_AD15_PH7,
|
||||
PMUX_PINGRP_GMI_A16_PJ7,
|
||||
PMUX_PINGRP_GMI_A17_PB0,
|
||||
PMUX_PINGRP_GMI_A18_PB1,
|
||||
PMUX_PINGRP_GMI_A19_PK7,
|
||||
PMUX_PINGRP_GMI_WR_N_PI0,
|
||||
PMUX_PINGRP_GMI_OE_N_PI1,
|
||||
PMUX_PINGRP_GMI_DQS_P_PJ3,
|
||||
PMUX_PINGRP_GMI_RST_N_PI4,
|
||||
PMUX_PINGRP_GEN2_I2C_SCL_PT5,
|
||||
PMUX_PINGRP_GEN2_I2C_SDA_PT6,
|
||||
PMUX_PINGRP_SDMMC4_CLK_PCC4,
|
||||
PMUX_PINGRP_SDMMC4_CMD_PT7,
|
||||
PMUX_PINGRP_SDMMC4_DAT0_PAA0,
|
||||
PMUX_PINGRP_SDMMC4_DAT1_PAA1,
|
||||
PMUX_PINGRP_SDMMC4_DAT2_PAA2,
|
||||
PMUX_PINGRP_SDMMC4_DAT3_PAA3,
|
||||
PMUX_PINGRP_SDMMC4_DAT4_PAA4,
|
||||
PMUX_PINGRP_SDMMC4_DAT5_PAA5,
|
||||
PMUX_PINGRP_SDMMC4_DAT6_PAA6,
|
||||
PMUX_PINGRP_SDMMC4_DAT7_PAA7,
|
||||
PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
|
||||
PMUX_PINGRP_PCC1,
|
||||
PMUX_PINGRP_PBB0,
|
||||
PMUX_PINGRP_CAM_I2C_SCL_PBB1,
|
||||
PMUX_PINGRP_CAM_I2C_SDA_PBB2,
|
||||
PMUX_PINGRP_PBB3,
|
||||
PMUX_PINGRP_PBB4,
|
||||
PMUX_PINGRP_PBB5,
|
||||
PMUX_PINGRP_PBB6,
|
||||
PMUX_PINGRP_PBB7,
|
||||
PMUX_PINGRP_PCC2,
|
||||
PMUX_PINGRP_JTAG_RTCK,
|
||||
PMUX_PINGRP_PWR_I2C_SCL_PZ6,
|
||||
PMUX_PINGRP_PWR_I2C_SDA_PZ7,
|
||||
PMUX_PINGRP_KB_ROW0_PR0,
|
||||
PMUX_PINGRP_KB_ROW1_PR1,
|
||||
PMUX_PINGRP_KB_ROW2_PR2,
|
||||
PMUX_PINGRP_KB_ROW3_PR3,
|
||||
PMUX_PINGRP_KB_ROW4_PR4,
|
||||
PMUX_PINGRP_KB_ROW5_PR5,
|
||||
PMUX_PINGRP_KB_ROW6_PR6,
|
||||
PMUX_PINGRP_KB_ROW7_PR7,
|
||||
PMUX_PINGRP_KB_ROW8_PS0,
|
||||
PMUX_PINGRP_KB_ROW9_PS1,
|
||||
PMUX_PINGRP_KB_ROW10_PS2,
|
||||
PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
|
||||
PMUX_PINGRP_KB_COL1_PQ1,
|
||||
PMUX_PINGRP_KB_COL2_PQ2,
|
||||
PMUX_PINGRP_KB_COL3_PQ3,
|
||||
PMUX_PINGRP_KB_COL4_PQ4,
|
||||
PMUX_PINGRP_KB_COL5_PQ5,
|
||||
PMUX_PINGRP_KB_COL6_PQ6,
|
||||
PMUX_PINGRP_KB_COL7_PQ7,
|
||||
PMUX_PINGRP_CLK_32K_OUT_PA0,
|
||||
PMUX_PINGRP_SYS_CLK_REQ_PZ5,
|
||||
PMUX_PINGRP_CORE_PWR_REQ,
|
||||
PMUX_PINGRP_CPU_PWR_REQ,
|
||||
PMUX_PINGRP_PWR_INT_N,
|
||||
PMUX_PINGRP_CLK_32K_IN,
|
||||
PMUX_PINGRP_OWR,
|
||||
PMUX_PINGRP_DAP1_FS_PN0,
|
||||
PMUX_PINGRP_DAP1_DIN_PN1,
|
||||
PMUX_PINGRP_DAP1_DOUT_PN2,
|
||||
PMUX_PINGRP_DAP1_SCLK_PN3,
|
||||
PMUX_PINGRP_CLK1_REQ_PEE2,
|
||||
PMUX_PINGRP_CLK1_OUT_PW4,
|
||||
PMUX_PINGRP_SPDIF_IN_PK6,
|
||||
PMUX_PINGRP_SPDIF_OUT_PK5,
|
||||
PMUX_PINGRP_DAP2_FS_PA2,
|
||||
PMUX_PINGRP_DAP2_DIN_PA4,
|
||||
PMUX_PINGRP_DAP2_DOUT_PA5,
|
||||
PMUX_PINGRP_DAP2_SCLK_PA3,
|
||||
PMUX_PINGRP_DVFS_PWM_PX0,
|
||||
PMUX_PINGRP_GPIO_X1_AUD_PX1,
|
||||
PMUX_PINGRP_GPIO_X3_AUD_PX3,
|
||||
PMUX_PINGRP_DVFS_CLK_PX2,
|
||||
PMUX_PINGRP_GPIO_X4_AUD_PX4,
|
||||
PMUX_PINGRP_GPIO_X5_AUD_PX5,
|
||||
PMUX_PINGRP_GPIO_X6_AUD_PX6,
|
||||
PMUX_PINGRP_GPIO_X7_AUD_PX7,
|
||||
PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
|
||||
PMUX_PINGRP_SDMMC3_CMD_PA7,
|
||||
PMUX_PINGRP_SDMMC3_DAT0_PB7,
|
||||
PMUX_PINGRP_SDMMC3_DAT1_PB6,
|
||||
PMUX_PINGRP_SDMMC3_DAT2_PB5,
|
||||
PMUX_PINGRP_SDMMC3_DAT3_PB4,
|
||||
PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
|
||||
PMUX_PINGRP_SDMMC1_WP_N_PV3,
|
||||
PMUX_PINGRP_SDMMC3_CD_N_PV2,
|
||||
PMUX_PINGRP_GPIO_W2_AUD_PW2,
|
||||
PMUX_PINGRP_GPIO_W3_AUD_PW3,
|
||||
PMUX_PINGRP_USB_VBUS_EN0_PN4,
|
||||
PMUX_PINGRP_USB_VBUS_EN1_PN5,
|
||||
PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
|
||||
PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
|
||||
PMUX_PINGRP_GMI_CLK_LB,
|
||||
PMUX_PINGRP_RESET_OUT_N,
|
||||
PMUX_PINGRP_COUNT,
|
||||
};
|
||||
|
||||
enum pmux_drvgrp {
|
||||
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
|
||||
PDRIVE_PINGROUP_AO2,
|
||||
PDRIVE_PINGROUP_AT1,
|
||||
PDRIVE_PINGROUP_AT2,
|
||||
PDRIVE_PINGROUP_AT3,
|
||||
PDRIVE_PINGROUP_AT4,
|
||||
PDRIVE_PINGROUP_AT5,
|
||||
PDRIVE_PINGROUP_CDEV1,
|
||||
PDRIVE_PINGROUP_CDEV2,
|
||||
PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
|
||||
PDRIVE_PINGROUP_DAP2,
|
||||
PDRIVE_PINGROUP_DAP3,
|
||||
PDRIVE_PINGROUP_DAP4,
|
||||
PDRIVE_PINGROUP_DBG,
|
||||
PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
|
||||
PDRIVE_PINGROUP_SPI,
|
||||
PDRIVE_PINGROUP_UAA,
|
||||
PDRIVE_PINGROUP_UAB,
|
||||
PDRIVE_PINGROUP_UART2,
|
||||
PDRIVE_PINGROUP_UART3,
|
||||
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
|
||||
PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
|
||||
PDRIVE_PINGROUP_GMA,
|
||||
PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
|
||||
PDRIVE_PINGROUP_GMF,
|
||||
PDRIVE_PINGROUP_GMG,
|
||||
PDRIVE_PINGROUP_GMH,
|
||||
PDRIVE_PINGROUP_OWR,
|
||||
PDRIVE_PINGROUP_UAD,
|
||||
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
|
||||
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
|
||||
PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
|
||||
PDRIVE_PINGROUP_DAP5,
|
||||
PDRIVE_PINGROUP_VBUS,
|
||||
PDRIVE_PINGROUP_AO3,
|
||||
PDRIVE_PINGROUP_HVC,
|
||||
PDRIVE_PINGROUP_SDIO4,
|
||||
PDRIVE_PINGROUP_AO0,
|
||||
PMUX_DRVGRP_AO1,
|
||||
PMUX_DRVGRP_AO2,
|
||||
PMUX_DRVGRP_AT1,
|
||||
PMUX_DRVGRP_AT2,
|
||||
PMUX_DRVGRP_AT3,
|
||||
PMUX_DRVGRP_AT4,
|
||||
PMUX_DRVGRP_AT5,
|
||||
PMUX_DRVGRP_CDEV1,
|
||||
PMUX_DRVGRP_CDEV2,
|
||||
PMUX_DRVGRP_DAP1 = (0x28 / 4),
|
||||
PMUX_DRVGRP_DAP2,
|
||||
PMUX_DRVGRP_DAP3,
|
||||
PMUX_DRVGRP_DAP4,
|
||||
PMUX_DRVGRP_DBG,
|
||||
PMUX_DRVGRP_SDIO3 = (0x48 / 4),
|
||||
PMUX_DRVGRP_SPI,
|
||||
PMUX_DRVGRP_UAA,
|
||||
PMUX_DRVGRP_UAB,
|
||||
PMUX_DRVGRP_UART2,
|
||||
PMUX_DRVGRP_UART3,
|
||||
PMUX_DRVGRP_SDIO1 = (0x84 / 4),
|
||||
PMUX_DRVGRP_DDC = (0x94 / 4),
|
||||
PMUX_DRVGRP_GMA,
|
||||
PMUX_DRVGRP_GME = (0xa8 / 4),
|
||||
PMUX_DRVGRP_GMF,
|
||||
PMUX_DRVGRP_GMG,
|
||||
PMUX_DRVGRP_GMH,
|
||||
PMUX_DRVGRP_OWR,
|
||||
PMUX_DRVGRP_UDA,
|
||||
PMUX_DRVGRP_DEV3 = (0xc4 / 4),
|
||||
PMUX_DRVGRP_CEC = (0xd0 / 4),
|
||||
PMUX_DRVGRP_AT6 = (0x12c / 4),
|
||||
PMUX_DRVGRP_DAP5,
|
||||
PMUX_DRVGRP_USB_VBUS_EN,
|
||||
PMUX_DRVGRP_AO3,
|
||||
PMUX_DRVGRP_HV0,
|
||||
PMUX_DRVGRP_SDIO4,
|
||||
PMUX_DRVGRP_AO0,
|
||||
PMUX_DRVGRP_COUNT,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions which can be assigned to each of the pin groups. The values here
|
||||
* bear no relation to the values programmed into pinmux registers and are
|
||||
* purely a convenience. The translation is done through a table search.
|
||||
*/
|
||||
enum pmux_func {
|
||||
PMUX_FUNC_AHB_CLK,
|
||||
PMUX_FUNC_APB_CLK,
|
||||
PMUX_FUNC_AUDIO_SYNC,
|
||||
PMUX_FUNC_CRT,
|
||||
PMUX_FUNC_DAP1,
|
||||
PMUX_FUNC_DAP2,
|
||||
PMUX_FUNC_DAP3,
|
||||
PMUX_FUNC_DAP4,
|
||||
PMUX_FUNC_DAP5,
|
||||
PMUX_FUNC_DISPA,
|
||||
PMUX_FUNC_DISPB,
|
||||
PMUX_FUNC_EMC_TEST0_DLL,
|
||||
PMUX_FUNC_EMC_TEST1_DLL,
|
||||
PMUX_FUNC_GMI,
|
||||
PMUX_FUNC_GMI_INT,
|
||||
PMUX_FUNC_HDMI,
|
||||
PMUX_FUNC_I2C1,
|
||||
PMUX_FUNC_I2C2,
|
||||
PMUX_FUNC_I2C3,
|
||||
PMUX_FUNC_IDE,
|
||||
PMUX_FUNC_KBC,
|
||||
PMUX_FUNC_MIO,
|
||||
PMUX_FUNC_MIPI_HS,
|
||||
PMUX_FUNC_NAND,
|
||||
PMUX_FUNC_OSC,
|
||||
PMUX_FUNC_OWR,
|
||||
PMUX_FUNC_PCIE,
|
||||
PMUX_FUNC_PLLA_OUT,
|
||||
PMUX_FUNC_PLLC_OUT1,
|
||||
PMUX_FUNC_PLLM_OUT1,
|
||||
PMUX_FUNC_PLLP_OUT2,
|
||||
PMUX_FUNC_PLLP_OUT3,
|
||||
PMUX_FUNC_PLLP_OUT4,
|
||||
PMUX_FUNC_PWM,
|
||||
PMUX_FUNC_PWR_INTR,
|
||||
PMUX_FUNC_PWR_ON,
|
||||
PMUX_FUNC_RTCK,
|
||||
PMUX_FUNC_SDMMC1,
|
||||
PMUX_FUNC_SDMMC2,
|
||||
PMUX_FUNC_SDMMC3,
|
||||
PMUX_FUNC_SDMMC4,
|
||||
PMUX_FUNC_SFLASH,
|
||||
PMUX_FUNC_SPDIF,
|
||||
PMUX_FUNC_SPI1,
|
||||
PMUX_FUNC_SPI2,
|
||||
PMUX_FUNC_SPI2_ALT,
|
||||
PMUX_FUNC_SPI3,
|
||||
PMUX_FUNC_SPI4,
|
||||
PMUX_FUNC_TRACE,
|
||||
PMUX_FUNC_TWC,
|
||||
PMUX_FUNC_UARTA,
|
||||
PMUX_FUNC_UARTB,
|
||||
PMUX_FUNC_UARTC,
|
||||
PMUX_FUNC_UARTD,
|
||||
PMUX_FUNC_UARTE,
|
||||
PMUX_FUNC_ULPI,
|
||||
PMUX_FUNC_VI,
|
||||
PMUX_FUNC_VI_SENSOR_CLK,
|
||||
PMUX_FUNC_XIO,
|
||||
/* End of Tegra2 MUX selectors */
|
||||
PMUX_FUNC_BLINK,
|
||||
PMUX_FUNC_CEC,
|
||||
PMUX_FUNC_CLDVFS,
|
||||
PMUX_FUNC_CLK,
|
||||
PMUX_FUNC_CLK12,
|
||||
PMUX_FUNC_CPU,
|
||||
PMUX_FUNC_DAP,
|
||||
PMUX_FUNC_DAPSDMMC2,
|
||||
PMUX_FUNC_DDR,
|
||||
PMUX_FUNC_DAP1,
|
||||
PMUX_FUNC_DAP2,
|
||||
PMUX_FUNC_DEV3,
|
||||
PMUX_FUNC_DISPLAYA,
|
||||
PMUX_FUNC_DISPLAYA_ALT,
|
||||
PMUX_FUNC_DISPLAYB,
|
||||
PMUX_FUNC_DTV,
|
||||
PMUX_FUNC_VI_ALT1,
|
||||
PMUX_FUNC_VI_ALT2,
|
||||
PMUX_FUNC_VI_ALT3,
|
||||
PMUX_FUNC_EMC_DLL,
|
||||
PMUX_FUNC_EXTPERIPH1,
|
||||
PMUX_FUNC_EXTPERIPH2,
|
||||
PMUX_FUNC_EXTPERIPH3,
|
||||
PMUX_FUNC_GMI,
|
||||
PMUX_FUNC_GMI_ALT,
|
||||
PMUX_FUNC_HDA,
|
||||
PMUX_FUNC_HSI,
|
||||
PMUX_FUNC_I2C1,
|
||||
PMUX_FUNC_I2C2,
|
||||
PMUX_FUNC_I2C3,
|
||||
PMUX_FUNC_I2C4,
|
||||
PMUX_FUNC_I2C5,
|
||||
PMUX_FUNC_I2CPWR,
|
||||
PMUX_FUNC_I2S0,
|
||||
PMUX_FUNC_I2S1,
|
||||
PMUX_FUNC_I2S2,
|
||||
PMUX_FUNC_I2S3,
|
||||
PMUX_FUNC_I2S4,
|
||||
PMUX_FUNC_IRDA,
|
||||
PMUX_FUNC_KBC,
|
||||
PMUX_FUNC_NAND,
|
||||
PMUX_FUNC_NAND_ALT,
|
||||
PMUX_FUNC_POPSDIO4,
|
||||
PMUX_FUNC_POPSDMMC4,
|
||||
PMUX_FUNC_OWR,
|
||||
PMUX_FUNC_PMI,
|
||||
PMUX_FUNC_PWM0,
|
||||
PMUX_FUNC_PWM1,
|
||||
PMUX_FUNC_PWM2,
|
||||
PMUX_FUNC_PWM3,
|
||||
PMUX_FUNC_SATA,
|
||||
PMUX_FUNC_PWRON,
|
||||
PMUX_FUNC_RESET_OUT_N,
|
||||
PMUX_FUNC_RTCK,
|
||||
PMUX_FUNC_SDMMC1,
|
||||
PMUX_FUNC_SDMMC2,
|
||||
PMUX_FUNC_SDMMC3,
|
||||
PMUX_FUNC_SDMMC4,
|
||||
PMUX_FUNC_SOC,
|
||||
PMUX_FUNC_SPDIF,
|
||||
PMUX_FUNC_SPI1,
|
||||
PMUX_FUNC_SPI2,
|
||||
PMUX_FUNC_SPI3,
|
||||
PMUX_FUNC_SPI4,
|
||||
PMUX_FUNC_SPI5,
|
||||
PMUX_FUNC_SPI6,
|
||||
PMUX_FUNC_SYSCLK,
|
||||
PMUX_FUNC_TRACE,
|
||||
PMUX_FUNC_UARTA,
|
||||
PMUX_FUNC_UARTB,
|
||||
PMUX_FUNC_UARTC,
|
||||
PMUX_FUNC_UARTD,
|
||||
PMUX_FUNC_ULPI,
|
||||
PMUX_FUNC_USB,
|
||||
PMUX_FUNC_VGP1,
|
||||
PMUX_FUNC_VGP2,
|
||||
PMUX_FUNC_VGP3,
|
||||
PMUX_FUNC_VGP4,
|
||||
PMUX_FUNC_VGP5,
|
||||
PMUX_FUNC_VGP6,
|
||||
/* End of Tegra3 MUX selectors */
|
||||
PMUX_FUNC_USB,
|
||||
PMUX_FUNC_SOC,
|
||||
PMUX_FUNC_CPU,
|
||||
PMUX_FUNC_CLK,
|
||||
PMUX_FUNC_PWRON,
|
||||
PMUX_FUNC_PMI,
|
||||
PMUX_FUNC_CLDVFS,
|
||||
PMUX_FUNC_RESET_OUT_N,
|
||||
/* End of Tegra114 MUX selectors */
|
||||
|
||||
PMUX_FUNC_VI,
|
||||
PMUX_FUNC_VI_ALT1,
|
||||
PMUX_FUNC_VI_ALT3,
|
||||
PMUX_FUNC_COUNT,
|
||||
|
||||
PMUX_FUNC_INVALID = 0x4000,
|
||||
PMUX_FUNC_RSVD1 = 0x8000,
|
||||
PMUX_FUNC_RSVD2 = 0x8001,
|
||||
PMUX_FUNC_RSVD3 = 0x8002,
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PINGRP_##_pingrp, \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PINGRP_##_pingrp, \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
|
|
@ -43,7 +43,7 @@
|
|||
|
||||
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PINGRP_##_pingrp, \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
|
|
@ -55,7 +55,7 @@
|
|||
|
||||
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PINGRP_##_pingrp, \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
|
|
@ -67,7 +67,7 @@
|
|||
|
||||
#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PINGRP_##_pingrp, \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
|
|
@ -81,7 +81,7 @@
|
|||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
|
|
@ -93,142 +93,142 @@
|
|||
|
||||
static struct pmux_pingrp_config tegra114_pinmux_common[] = {
|
||||
/* EXTPERIPH1 pinmux */
|
||||
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2S0 pinmux */
|
||||
DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* I2S1 pinmux */
|
||||
DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* I2S3 pinmux */
|
||||
DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLDVFS pinmux */
|
||||
DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2C3 pinmux */
|
||||
I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* VI pinmux */
|
||||
VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
|
||||
/* VI_ALT1 pinmux */
|
||||
VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
|
||||
/* VGP4 pinmux */
|
||||
VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
|
||||
/* I2C2 pinmux */
|
||||
I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* UARTD pinmux */
|
||||
DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SPI4 pinmux */
|
||||
DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6, SPI4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7, SPI4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* PWM1 pinmux */
|
||||
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SOC pinmux */
|
||||
DEFAULT_PINMUX(GMI_CS1_N, SOC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N, SOC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* EXTPERIPH2 pinmux */
|
||||
DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
|
||||
|
||||
/* BLINK pinmux */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC pinmux */
|
||||
DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
/*Audio Codec*/
|
||||
DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
|
||||
|
||||
/* UARTA pinmux */
|
||||
DEFAULT_PINMUX(KB_ROW10, UARTA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2CPWR pinmux (I2C5) */
|
||||
I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* SYSCLK pinmux */
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* RTCK pinmux */
|
||||
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
|
||||
|
|
@ -249,117 +249,117 @@ static struct pmux_pingrp_config tegra114_pinmux_common[] = {
|
|||
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* EXTPERIPH3 pinmux */
|
||||
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2C1 pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* UARTB pinmux */
|
||||
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* IRDA pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* UARTC pinmux */
|
||||
DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* OWR pinmux */
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CEC pinmux */
|
||||
CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
|
||||
CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
|
||||
|
||||
/* I2C4 pinmux */
|
||||
DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
|
||||
DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
|
||||
DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
|
||||
DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
|
||||
|
||||
/* USB pinmux */
|
||||
USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* nct */
|
||||
DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT),
|
||||
};
|
||||
|
||||
static struct pmux_pingrp_config unused_pins_lowpower[] = {
|
||||
DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
/* Initially setting all used GPIO's to non-TRISTATE */
|
||||
static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
|
||||
DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(DAP3_FS, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(GPIO_PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PCC1, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PCC2, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N, GMI, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WP_N, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config dalmore_padctrl[] = {
|
||||
|
|
|
|||
Loading…
Reference in a new issue