Commit graph

971 commits

Author SHA1 Message Date
Bin Meng
ff1e18af9d x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()
fsp_init() call has a parameter nvs_buf which is used by FSP as the
MRC cache but currently is blindly set to NULL. Retreive the MRC
cache from SPI flash and pass it to fsp_init() call. After the call,
save FSP produced MRC cache to SPI flash too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
4b9f6a669e x86: Use struct mrc_region to describe a mrc region
Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.

Define a new struct mrc_region and use it instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
42913a1c7a x86: ivybridge: Use APIs provided in the mrccache lib
Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ed800961a0 x86: Add more common routines to manipulate mrc cache
This adds mrccache_reserve(), mrccache_get_region() and
mrccache_save() APIs to the mrccache codes. They are ported
from the ivybridge implementation, but with some changes.
For example, in the mrccache_reserve(), ivybridge version
only reserves the pure MRC data, which causes additional
malloc() when saving the cache as the save API needs some
meta data. Now we change it to save the whole MRC date plus
the meta data to elinimate the need for the malloc() later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
bfa95c538b x86: Add various minor tidy-ups in mrccache codes
Fix some nits, improve some comments and reorder some codes
a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
2fe66dbcbc x86: Do sanity test on the cache record in mrccache_update()
For the cache record to write in mrccache_update(), we should
perform a sanity test to see if it is a valid one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
f6220f1a86 x86: Move mrccache.[c|h] to a common place
mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
e2d76e95d3 x86: Add ENABLE_MRC_CACHE Kconfig option
Create a Kconfig option for enabling MRC cache.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
010921ae7f x86: fsp: Add a hdr sub-command to show header information
It would be helpful to have a command to show FSP header. So far
it only supports FSP header which conforms to FSP spec 1.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
62716ebb75 x86: fsp: Make hob command a sub-command to fsp
Introduce a new fsp command and make the existing hob command a
sub-command to fsp for future extension. Also move cmd_hob.c to
the dedicated fsp sub-directory in arch/x86/lib.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
b325cbb171 x86: fsp: Print GUID whenever applicable in the hob command output
When examining a HOB, it's useful to see which GUID this HOB
belongs to. Add GUID output in the hob command to aid this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
fd755f084e x86: fsp: Compact the output of hob command
Compact hob command output, especially by making hob type string a
little bit shorter so that we can leave room for future extension.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
721e992a8a x86: Add SMBIOS table support
System Management BIOS (SMBIOS) is a specification for how
motherboard and system vendors present management information
about their products in a standard format by extending the BIOS
interface on Intel architecture systems. As of today the latest
spec is 3.0 and can be downloaded from DMTF website. This commit
adds a simple and minimum required implementation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00
Bin Meng
59ec719df6 x86: Move install_e820_map() out of zimage.c
install_e820_map() has nothing to do with zimage related codes.
Move it to a dedicated place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Bin Meng
19038e1bb6 x86: Initialize GDT entry 1 to be the 32-bit CS as well
Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
2015-10-21 07:46:25 -06:00
Bin Meng
1f124eba11 x86: Allow disabling IGD on Intel Queensbay
Add a Kconfig option to disable the Integrated Graphics Device (IGD)
so that it does not show in the PCI configuration space as a VGA
disaplay controller. This gives a chance for U-Boot to run PCI/PCIe
based graphics card's VGA BIOS and use that for the graphics console.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Bin Meng
5bf935925b x86: ivybridge: Remove the dead codes that programs pci bridge
Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Bin Meng
196193a4d4 x86: fsp: Report correct number of E820 table entries
The logic to calculate the number of E820 table entries is wrong
when walking through the FSP HOB tables. Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-28 21:56:27 -07:00
Bin Meng
c6d4705f41 x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.

We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.

With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
5bf0f7f65d x86: galileo: Add PCIe root port IRQ routing
Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
554778c240 x86: quark: Initialize thermal sensor properly
Thermal sensor on Quark SoC needs to be properly initialized per
Quark firmware writer guide, otherwise when booting Linux kernel,
it triggers system shutdown because of wrong temperature in the
thermal sensor is detected by the kernel driver (see below):

[    5.119819] thermal_sys: Critical temperature reached(206 C),shutting down
[    5.128997] Failed to start orderly shutdown: forcing the issue
[    5.135495] Emergency Sync complete

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
693b5f6c71 x86: quark: Lock HMBOUND register before jumping to kernel
When Linux kernel boots, it hangs at:

[    0.829408] Intel Quark side-band driver registered

This happens when Quark kernel Isolated Memory Region (IMR) driver
tries to lock an IMR register to protect kernel's text and rodata
sections. However in order to have IMR function correctly, HMBOUND
register must be locked otherwise the system just hangs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
8e3683029e x86: quark: Convert to use clrbits, setbits, clrsetbits macros
Change existing codes to use clrbits, setbits, clrsetbits macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
d0b3e3bfbb x86: quark: Add clrbits, setbits, clrsetbits macros for message port access
On Intel Quark, lots of registers on the message port need be
programmed. Add handy clrbits, setbits, clrsetbits macros for
message port access.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
2afb62305e x86: quark: Add PCIe/USB static register programming after memory init
This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
5841c5b0a7 x86: Convert to use driver model eth on quark/galileo
Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
b06862b9d8 x86: quark: Add USB PHY initialization support
USB PHY needs to be properly initialized per Quark firmware writer
guide, otherwise the EHCI controller on Quark SoC won't work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
31b5aebd5e x86: Convert to use driver model pci on quark/galileo
Move to driver model pci for Intel quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
316fd3920f x86: Enable PCIe controller on quark/galileo
Quark SoC holds the PCIe controller in reset following a power on.
U-Boot needs to release the PCIe controller from reset. The PCIe
controller (D23:F0/F1) will not be visible in PCI configuration
space and any access to its PCI configuration registers will cause
system hang while it is held in reset.

Enable PCIe controller per Quark firmware writer guide.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
aa09505ba1 x86: quark: Avoid chicken and egg problem
If we convert to use driver model pci on quark, we will encounter
some chicken and egg problems like below:

- To enable PCIe root ports, we need program some registers on the
  message bus via pci bus. With driver model, the first time to
  access pci bus, the pci enumeration process will be triggered.
  But without first enabling PCIe root ports, pci enumeration
  just hangs when scanning PCIe root ports.
- Similar situation happens when trying to access GPIO from the
  PCIe enabling codes, as GPIO requires its block base address
  to be assigned via a pci configuration register in the bridge.

To avoid such dilemma, replace all pci calls in the quark codes
to use the local version which does not go through driver model.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
5750e5e29a x86: quark: Optimize MRC execution time
Intel Quark SoC has a low end x86 processor with only 400MHz
frequency. Currently it takes about 15 seconds for U-Boot to
boot to shell and the most time consuming part is with MRC,
which is about 12 seconds. MRC programs lots of registers on
the SoC internal message bus indirectly accessed via pci bus.

To speed up the boot, create an optimized version of pci config
read/write dword routines which directly operate on PCI I/O ports.
These two routines are inlined to provide better performance too.
Now it only takes about 3 seconds to finish MRC, which is really
fast (4 times faster than before).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
5bc60d5a44 x86: coreboot: Convert to use more dm drivers
Move to driver model for RTC, USB and ETH on coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Simon Glass
548fb8777d x86: panther: Add PCI and video configuration
Add a PCI node to the device tree. This allows SPI flash and SATA to work
correctly. Also configure the video to come up correctly even though there
is no keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-09-09 07:48:03 -06:00
Simon Glass
6e474eab44 exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices
Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2015-08-31 07:57:28 -06:00
Bin Meng
a1f1582b73 x86: crownbay: Support Topcliff integrated pci uart devices with driver model
In order to make a pci uart device node to be properly bound to its
driver, we need make sure its parent node has a compatible string
which matches a driver that scans all of its child device nodes in
the device tree.

Change all pci bridge nodes under root pci node to use "pci-bridge"
compatible driver, as well as corresponding <reg> properties to
indicate its devfn. At last, adding "u-boot,dm-pre-reloc" to each
of these nodes for driver model to initialize them before relocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:17 -07:00
Bin Meng
4dd02a752c x86: crownbay: Enable on-board SMSC superio keyboard controller
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.

In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:16 -07:00
Simon Glass
86645c8932 x86: minnowmax: Correct pad-offset value for host_en1
This should be 0x250, not 0x258. Fix it.

Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Simon Glass
cce7e0fa2b x86: minnowmax: Add access to GPIOs E0, E1, E2
These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Saket Sinha
bccdf1de75 x86: Add DSDT table for supporting ACPI on QEMU
The DSDT table contains a bytecode that is executed by a driver in the kernel.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Tested with QEMU '-M q35'
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:14 -07:00
Saket Sinha
e94019ede7 x86: Add ACPI table support to QEMU
This patch mainly adds ACPI support to QEMU.
Verified by booting Linux kernel on QEMU Q35.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Minor whitespace fixes and dropped mention of i440FX in commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Saket Sinha
867bcb63e7 x86: Generate a valid ACPI table
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT
ACPI table entries.

Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need
actually write the APCI table just like we did for PIRQ routing, MP table
and SFI tables. With ACPI table existence, linux kernel gets control of
power management, thermal management, configuration management and
monitoring in hardware.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tidied up whitespace and aligned some tabs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:13 -07:00
Bin Meng
c78dfb4fd2 x86: superio: Add keyboard controller support to smsc_lpc47m driver
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:12 -07:00
Bin Meng
fa6af7b4e0 x86: baytrail: Remove the fsp_init_phase_pci() call
It turns out that calling fsp_init_phase_pci() in arch_misc_init()
is subject to break pci device drivers as with driver model, when
the bus enumeration happens is not deterministic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:12 -07:00
Bin Meng
090290f97b x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()
With dm pci conversion, pci config read/write in unprotect_spi_flash()
silently fails as at that time dm pci is not ready and bus enumeration
is not done yet. Actually we don't need to do this in that early phase,
hence we delay this call to arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:12 -07:00
Bin Meng
48aa6c2614 x86: fsp: Add comments about U-Boot entering start.S twice
Add some comments in start.S for the fact that with FSP U-Boot
actually enters the code twice. Also change to use fsp_init()
and fsp_continue for accuracy.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:11 -07:00
Bin Meng
57b10f59b7 x86: fsp: Enlarge the size of malloc() pool before relocation
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Enlarge the size of malloc() pool before relocation since we have
plenty of memory now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:11 -07:00
Bin Meng
5fb0151697 x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:09 -07:00
Bin Meng
5c113ff79c x86: baytrail: Add microcode for BayTrail-I D0 stepping
This commit adds the microcode blob for BayTrail-I D0 stepping,
CPUID signature 30679h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:09 -07:00
Bin Meng
8744bef5a1 x86: kconfig: Hide "System tables" for coreboot
When booting as a coreboot payload, we don't need write any
configuration tables as coreboot does that for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:08 -07:00
Bin Meng
d2f56f46fe x86: kconfig: Hide "System tables" for EFI
Instead of hiding each menu entries under "System tables" for EFI,
hide the main menu completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
a25bc78e2f x86: coreboot: Allow >=4GiB memory bank size
Some platforms may have >=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
c17ca6b5cd x86: Remove calculate_relocation_address()
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
52b778603b x86: coreboot: Correctly report E820 types
coreboot has some extensions (type 6 & 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
89b870814c x86: coreboot: Increase memrange entry number to 32
Increase lib_sysinfo memrange entry number to 32 to sync with coreboot.
This allows a complete E820 table to be reported to the kernel, as on
some platforms (eg: Bayley Bay) having only 16 entires does not cover
all the memory ranges.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:06 -07:00
Simon Glass
ef910819c5 x86: minnowmax: Define and enable interrupt setup
Set up interrupts correctly so that Linux can use all devices. Use
savedefconfig to regenerate the defconfig file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:14 -06:00
Simon Glass
052e34b363 x86: Return -1 when reading a PCI config register fails
This can fail for internal reasons, so return a sensible value rather than
a random one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:13 -06:00
Simon Glass
ecf674b772 x86: Drop FSP error defines and use EFI instead
Now that we have an efi.h header we can use that for FSP error defines.
Drop the FSP ones.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:13 -06:00
Bin Meng
ecfeadabb7 x86: Set APs' req_seq to the reg number from device tree
Multiple APs are brought up simultaneously and they may get the same
seq num in the uclass_resolve_seq() during device_probe(). To avoid
this, set req_seq to the reg number in the device tree in advance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-14 09:50:12 -06:00
Simon Glass
7399515d25 x86: Show the un-relocated IP address in exceptions
When trying to figure out where an exception has occured, the relocated
address is not a lot of help. Its value depends on various factors. Show
the un-relocated IP as well. This can be looked up in System.map directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:12 -06:00
Simon Glass
f0c7d9c746 x86: Switch to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:10 -06:00
Simon Glass
2db9374561 x86: Move the GDT into global_data
Rather than keeping track of the Global Descriptor Table in its own memory
we may as well put it in global_data with everything else. As a first step,
stop using the separately allocated GDT.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 09:50:10 -06:00
Simon Glass
93afae5d05 x86: Remove init_gd() function
This is declared but no-longer exists. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
c8896ee481 x86: baytrail: Support running as an EFI payload
We should not fiddle with interrupts or the FSP when running as an EFI
payload. Detect this and skip this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
46f8efee70 x86: baytrail: Tidy up interrupt and FSP init
We should signal to the FSP that PCI enumeration is complete. Perform this
task in a suitable place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
7e4be120e8 x86: Allow pirq_init() to return an error
This function can fail. In this case we should return the error rather than
swallowing it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
412400abaa x86: Split out fsp_init_phase_pci() code into a new function
This code may be useful for boards that use driver model for PCI.

Note: It would be better to have driver model automatically call this
function somehow. However for now it is probably safer to have it under
board control.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Simon Glass
9e3ff9c2b4 x86: Tidy up the PIRQ routing code a little
This code could use a little tightening up. There is some repetition and
an odd use of fdtdec_get_int_array().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:21 -06:00
Bin Meng
da60fb7934 x86: fsp: Do not assert VPD_IMAGE_REV when DEBUG
When using different release version of Intel FSP, the VPD_IMAGE_REV
is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304).
Remove the asserting of this so that U-Boot does not hang in a debug
build.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Andrew Bradford
f3b84a3032 x86: baytrail: Configure FSP UPD from device tree
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Simon Glass
bbbe55f6f2 x86: Enable debug UART for Minnowmax
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.

Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.

So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-08-06 07:44:30 -06:00
Simon Glass
eeae510007 x86: qemu: Support operation as an EFI payload
Disable a few things which interfere with the EFI init. This allows QEMU to
to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
b4302582f3 x86: baytrail: Support operation as an EFI payload
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
8e36650875 x86: Add helper code for running from EFI
When U-Boot is running from EFI some of the x86 init is replaced with
EFI-specific init. For example, since DRAM has already been set up, we only
need to find it, not init it. Add these functions so that boards can easily
allow booting from EFI if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
e49cceac61 x86: Handle running as EFI payload
When U-Boot runs as an EFI payload it needs to avoid setting up the CPU
again. Also U-Boot currently does not handle interrupts for many devices, so
run with interrupts disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:08 -06:00
Simon Glass
42fde30500 x86: Add support for passing tables into U-Boot
The EFI stub provides information to U-Boot in a table. This includes the
memory map which is needed to decide where to relocate U-Boot. Collect this
information in the early init code and store it in global_data.

Fix up the BIST code at the same time since we don't have it when booting
from EFI and can assume it is 0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
96a8d409a7 efi: Add 64-bit payload support
Most EFI implementations use 64-bit. Add a way to build U-Boot as a 64-bit
EFI payload. The payload unpacks a (32-bit) U-Boot and starts it. This can
be enabled for x86 boards at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
6f92ed8f1a x86: Add a way to call 32-bit code from 64-bit mode
The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a
function to take care of it. It requires identity-mapped pages and that
the calling code is running below 4GB.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
7dfe8bdeef x86: Add an enum for some commonly-used GDT bits
Rather than add these as open-coded values, create an enum with the commonly
used flags.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
b997abd3f0 x86: Support building the EFI stub
Add support for building a 32/64-bit EFI stub for x86. This involves
building the startup and relocation code for either i386 or x86_64.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:07 -06:00
Simon Glass
476476e73b efi: Add support for loading U-Boot through an EFI stub
It is useful to be able to load U-Boot onto a board even if is it already
running EFI. This can allow access to the U-Boot command interface, flexible
booting options and easier development.

The easiest way to do this is to build U-Boot as a binary blob and have an
EFI stub copy it into RAM. Add support for this feature, targeting 32-bit
initially.

Also add a way to detect when U-Boot has been loaded via a stub. This goes
in common.h since it needs to be widely available so that we avoid redoing
initialisation that should be skipped.

Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
465a67cf52 x86: Add relocation and link script for a 64-bit EFI application
Add a linker script and relocation code for building 64-bit EFI
applications. This can be used for the EFI stub.

Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
a42bfe02d3 x86: Allow relocation code to build without text base
This code currently requires CONFIG_SYS_TEXT_BASE but this should be
unnecessary. As a first step, remove the build-time limitation and report an
error instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
d6c099c2a1 x86: dts: Add a device tree file for EFI
This contains just enough to bring up the serial UART.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Ben Stoltz
3e9aa32055 x86: Add EFI board code
Add support for the efi-x86 board, which supports running U-Boot as an
EFI 32-bit application.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Ben Stoltz
3dcdd17b43 x86: Add support for U-Boot as an EFI application
Add the required x86 glue code. This includes the initial start-up,
relocation and jumping to efi_main(). We also need to avoid fiddling with
interrupts.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:06 -06:00
Simon Glass
ed3b4d3736 x86: Add asm/elf.h for x86-specific ELF definitions
Bring in this file from Linux 4.1. It supports relocation features specific
to x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:05 -06:00
Simon Glass
981dca69f6 x86: Support skipping relocation for EFI
When running as an EFI application we must skip relocation. Add support for
this in the x86 relocation code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:05 -06:00
Ben Stoltz
3f1c046cea x86: Set up toolchain flags for running as EFI application
Adjust the toolchain flags to build U-Boot as a relocatable shared library,
as required by EFI.

Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:44:05 -06:00
Simon Glass
867a6ac86d efi: Add start-up library code
When running as an EFI application, U-Boot must request memory from EFI,
and provide access to the boot services U-Boot needs.

Add library code to perform these tasks. This includes efi_main() which is
the entry point from EFI. U-Boot is built as a shared library.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
8f3b9694b2 x86: Allow use of global_data with EFI
On x86 the global_data pointer is provided through a somewhat-bizarre and
x86-specific mechanism: the F segment register is set to a pointer to the
start of global_data, so that accesses can use this build-in register.

When running as an EFI application we don't want to mess with the Global
Descriptor Table (GDT) and there is little advantage (in terms of code size)
to doing so.

Allow global_data to be a simple variable in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
8aba36d896 x86: Tidy up a few minor issues with interrupts
Fix a typo, remove an unused field and make sure to use existing #define
constants instead of open-coded values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
8b097916fa x86: Add some missing global_data declarations in files that use gd
Some files use global_data but don't declare it. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
0bc74ab3e6 x86: Tidy up the 64-bit calling code
The GDT works but technically the length is incorrect. Fix this and add a
comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
0d9edd2dfb x86: Drop unused copy_fdt_to_ram()
This is now handled by generic U-Boot code so we do not need an x86 version.
It is no-longer called, so remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Simon Glass
83ec7de3bc x86: Tidy up global_data flags
These flags now overlap some global ones. Adjust the x86-specific flags to
avoid this. Since this requires a change to the start.S code, add a way for
tools to find the 32-bit cold reset entry point. Previously this was at a
fixed offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Simon Glass
b6c9a20556 x86: Use CR0 constants in CPU init
We should use these constants where possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Simon Glass
da3a95d60b x86: Add various minor tidy-ups to the 32-bit startup code
Fix a typo, improve some comments and add a little more detail in some
cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:40 -06:00
Bin Meng
fe3fbd3024 x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
9b911bed78 x86: Add Intel Bayley Bay board support
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
2774ff720d x86: Add microcode for BayTrail-I B0 stepping
This commit adds the microcode blob for BayTrail-I B0 stepping,
CPUID signature 30671h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
3e79a4ab26 x86: baytrail: Update UPD setting for FSP Gold4 release
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
a2eb65fcad x86: qemu: Add MP initialization
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:38 -06:00
Miao Yan
417576c2f1 x86: Add a 'pause' instruction in __udelay() for QEMU target
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.

This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:38 -06:00
Bin Meng
1ed6648be0 x86: Reserve PCIe ECAM address range in the E820 table
We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
9830d2ebb4 x86: qemu: Turn on PCIe ECAM address range decoding on Q35
Turn on PCIe ECAM address range decoding on Q35.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
a8ebf283e9 x86: qemu: Enable writing MP table
Enable writing MP table for QEMU boads (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
c77b8912d8 x86: Allow cpu-x86 driver to be probed for UP
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
e7cd070da6 x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
53832bb8d6 x86: mpspec: Move writing ISA interrupt entry after PCI
On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
abab912813 x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
a277194341 x86: Convert to use driver model pci on queensbay/crownbay
Move to driver model pci for Intel queensbay/crownbay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:24 -06:00
Bin Meng
6fc0e8a1fa x86: pci: Do not assign irq 0 to pci device
IRQ 0 is reserved and should not be assigned to pci device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
31a2dc6955 x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
93f8a31186 x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-28 10:36:22 -06:00
Bin Meng
8ba25eec86 x86: Change pci option rom area MTRR setting to cacheable
Turn on cache on the pci option rom area to improve the performance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
3ccd49cab4 x86: Simplify architecture defined exception handling in irq_llsr()
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.

With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:21 -06:00
Bin Meng
013cf483c9 x86: Display correct CS/EIP/EFLAGS when there is an error code
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:21 -06:00
Masahiro Yamada
b0c8f4a797 Kill unneeded #include <linux/kconfig.h>
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.

By the way, there are exceptions for the statement above; host
programs.  In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not.  So, some
files still include <linux/config.h> to work around build errors
on host tools.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-27 15:02:12 -04:00
Masahiro Yamada
5f7e310467 x86: delete unneeded declarations of disable_irq() and enable_irq()
These two declarations in arch/x86/include/asm/interrupt.h conflict
with ones in include/linux/compat.h, so x86 boards cannot include
<linux/compat.h>.

The comment /* arch/x86/lib/interrupts.c */ is bogus now, and we do
not see any definitions of disable_irq() and enable_irq() in there.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-22 07:30:31 -06:00
Simon Glass
b9da5086b8 dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Simon Glass
b71f9dca89 dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:19 -06:00
Simon Glass
945cae79e1 x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Bin Meng
a452002259 x86: Configure VESA parameters before loading Linux kernel
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
2015-07-14 18:03:19 -06:00
Bin Meng
9e3a7c9bac x86: Remove MARK_GRAPHICS_MEM_WRCOMB
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
786a08e0dd x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
df07d91956 x86: cmd_mtrr: Improve MTRR list information
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
92587b364b x86: queensbay: Change CPU_ADDR_BITS to 32
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
43dd22f5fc x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Jian Luo
1441d81a79 x86: bios: Allow pci config read/write to host bridge in int1a_handler
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Jian Luo
7b5c349890 x86: bios: Synchronize stack between real and protected mode
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
cdb6babec6 x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
07545d861c x86: Generate a valid MultiProcessor (MP) table
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.

Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
7f5df8d42d x86: Add MultiProcessor (MP) table APIs
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
a2d73fdba6 x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
3d23287828 x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
ba9091f55d x86: Clean up ioapic header file
Remove all the dead/unused macros from asm/ioapic.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
df81749db7 x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
8c38e4d0b8 x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
9c235436a3 x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Bin Meng
d402f922b2 x86: queensbay: Correct Topcliff device irqs
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.

This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
b0014b6423 x86: crownbay: Enable DM RTC support
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
990acd0d51 x86: crownbay: Add MP initialization
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
   overriding the value of OF_CONTROL. Old value: "y", new value: "y")
2015-07-14 18:03:16 -06:00
Bin Meng
63d54a6705 x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
  defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
  CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
  it is not apic related and only used by ivybridge
- Fix coding convention issues

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
61788e468e x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
6e6f4ce4f8 x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
946c2b5259 x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
Ivybridge is not ready for U-Boot MP initialization yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:16 -06:00
Bin Meng
4c71322b41 x86: kconfig: Fix minor nits in MAX_CPUS
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
063374d2f6 x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
be3f06bcc4 x86: dm: Clean up cpu drivers
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
  file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
  naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
  the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
  cpu_x86_bind()

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
aefaff8ed8 x86: fsp: Move FspInitEntry call to board_init_f()
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.

Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
002610f620 x86: fsp: Load GDT before calling FspInitEntry
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.

To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Bin Meng
343fb99064 x86: Add Kconfig options to be used by arch/x86/cpu/config.mk
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:15 -06:00
Joe Hershberger
c9bb942e2f Move default y configs out of arch/board Kconfig
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.

Remove the configs that behave this way from the archs.

A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:

SPIFLASH
DISPLAY_BOARDINFO

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-06-25 22:17:55 -04:00
Gabriel Huau
5318f18d2c x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:08 -06:00
Andrew Bradford
afbbd413a3 x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
5c564226fc x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
f2653e8dd9 x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
683b09d783 x86: qemu: Create separate i440fx and q35 device trees
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
65cdd9be3e x86: coreboot: Fix cosmetic issues
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Bin Meng
d04e30b839 x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSP
FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Bin Meng
4be2f42bbc x86: qemu: Adjust VGA initialization
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.

Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id & device id pair.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:40 -06:00
Bin Meng
0fcb7acf67 x86: qemu: Enable legacy IDE I/O ports decode
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
cc7debc719 x86: qemu: Turn on legacy segments decode
By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Andrew Bradford
1dc03c2639 x86: fsp_support: Correct high mem comment typo
High mem starts at 4 GiB.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
67b24970ce x86: Do sanity test on pirq table before writing
If pirq_routing_table points to NULL, that means U-Boot fails to
generate the table before in create_pirq_routing_table(), so we
test it against NULL before actually writing it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
05b98ec346 x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
9c7dea602e x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
9c4f541237 x86: qemu: Add graphics support
It turns out that QEMU x86 emulated graphic card has a built-in
option ROM which can be run perfectly with native mode by U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Bin Meng
6bde2dc5e2 x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video Kconfig
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them depend on VIDEO_VESA driver. Some cosmetic fixes are
applied to the Kconfig help text as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Bin Meng
99a309f323 x86: Make QEMU the default vendor
Now that we have QEMU support, make it the default vendor in the
'make menuconfig' screen.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Bin Meng
a65b25d148 x86: Support QEMU x86 targets
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
   https://patchwork.ozlabs.org/patch/479745/
2015-06-04 02:39:38 -06:00
Simon Glass
281239ad9d x86: Enable multi-core init for Minnowboard MAX
Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This
enables multi-core support in Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:52 -06:00
Simon Glass
ede9709316 x86: Add a CPU driver for baytrail
This driver supports multi-core init and sets up the CPU frequencies
correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:50 -06:00
Simon Glass
bcb0c61e1a x86: Allow CPUs to be set up after relocation
This permits init of additional CPU cores after relocation and when driver
model is ready.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:48 -06:00
Simon Glass
86196c65ac x86: Add functions to set and clear bits on MSRs
Since we do these sorts of operations a lot, it is useful to have a simpler
API, similar to clrsetbits_le32().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:46 -06:00
Simon Glass
45b5a37836 x86: Add multi-processor init
Most modern x86 CPUs include more than one CPU core. The OS normally requires
that these 'Application Processors' (APs) be brought up by the boot loader.
Add the required support to U-Boot to init additional APs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-30 16:13:38 -06:00
Simon Glass
6f41e0e7bc x86: Provide access to the IDT
Add a function to return the address of the Interrupt Descriptor Table.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
52845296be x86: Store the GDT pointer in global_data
When we start up additional CPUs we want them to use the same Global
Descriptor Table. Store the address of this in global_data so we can
reference it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
837a136fc7 x86: Add an mfence macro
Provide access to this x86 instruction from C code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
1a06d2a310 x86: Add defines for fixed MTRRs
Add MSR numbers for the fixed MTRRs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:34 -06:00
Simon Glass
b551173b73 x86: Add atomic operations
Add a subset of this header file from Linux 4.0 to support atomic operations
in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:33 -06:00
Simon Glass
6388e35725 x86: Add support for the Simple Firmware Interface (SFI)
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:33 -06:00
Simon Glass
9a7d700cca x86: Disable -Werror
This is annoying during development and serves no useful purpose since
warnings are clearly displayed now that we are using Kbuild. Remove this
option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
4051386107 x86: Remove unwanted MMC debugging
This printf() should not have made it into the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
410b10f1e3 x86: fsp: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
ebebf05976 x86: quark: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
5021c81faa x86: ivybridge: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:32 -06:00
Simon Glass
ff6a8f3c06 x86: Implement reset_cpu() correctly for modern CPUs
The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.

We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power cycle.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-29 21:02:31 -06:00
Simon Glass
87f4cd3a30 x86: link: Add PCH driver to support SPI Flash
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Gabriel Huau
8ddb8cfb1a x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
cc4c8aca1d x86: Correct the typo in write_tables()
It should be #ifdef instead of #if.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
3e4522279d x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/Kconfig
Since all x86 boards have been converted to use DM_SPI and
DM_SPI_FLASH, move them to arch/Kconfig x86 section.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
d99b901e74 x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmetics
Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
fix the indention of its help text.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
029194a3c4 x86: Kconfig: Move platform options forward
Move platform-specific options under in arch/x86/Kconfig forward right
after the board-specific options but before any architecture-specific
options. When it comes to the same Kconfig option, board-specific one
takes take the highest precedence, then platform-specific one, and
finally architecture-specific one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
65c4ac0a83 x86: Kconfig: Divide the target selection to vendor/model
Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/<vendor>/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
f82a7840f1 x86: quark: Turn on legacy segments decode
By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Bin Meng
283a08e52a x86: Check PIRQ routing table sanity in the F segment
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Gabriel Huau
8827227889 x86: minnowmax: add GPIO banks in the device tree
There are 6 banks:
    4 banks for CORE: available in S0 mode
    2 banks for SUS (Suspend): available in S0-S5 mode

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Gabriel Huau
4a34e4b86f x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
afbf1404c1 x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
b5b6b01960 x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).

We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
5e2400e8f8 x86: Write configuration tables in last_stage_init()
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
e3e7fa2cd1 x86: Add a function to assign IRQ numbers to PCI device
Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its interrupt working under PIC mode after OS boots up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
54c6001bba x86: Install a default e820 table in the __weak install_e820_map()
Create a default e820 table with 3 entries which is enough to boot
a Linux kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
24ff8e70e1 x86: Clean up arch/x86/include/asm/e820.h
There are lots of unused codes defined in e820.h, clean it up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
0a9bb489bf x86: Add alias for SPI node in the board dts
Since Intel ICH SPI driver has been converted to driver model, we need
add an alias for SPI node in the board dts files otherwise SPI flash
won't be detected due to 'invalid bus' error.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
19268834fb x86: Set serial port IRQ for SMSC LPC47M
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
9704f23b00 x86: queensbay: Avoid using PCH prefix
The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and Topcliff IOH chipset. For accuracy,
avoid using PCH prefix in the macro.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
5098d73e86 x86: Remove the old VGA driver
CONFIG_VIDEO_VGA is no longer needed thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Simon Glass
8156345dfe sandbox: Move CONFIG_SYS_VSNPRINTF to Kconfig
Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:37 -06:00
Simon Glass
ee2b24340f Kconfig: Move CONFIG_BOOTSTAGE to Kconfig
Move CONFIG_BOOT_STAGE and its associated options to Kconfig. Adjust
existing users and code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:37 -06:00
Masahiro Yamada
58d423b88e dm: select CONFIG_DM* options
As mentioned in the previous commit, adding default values in each
Kconfig causes problems because it does not co-exist with the
"depends on" syntax.  (Please note this is not a bug of Kconfig.)
We should not do so unless we have a special reason.  Actually,
for CONFIG_DM*, we have no good reason to do so.

Generally, CONFIG_DM is not a user-configurable option.  Once we
convert a driver into Driver Model, the board only works with Driver
Model, i.e. CONFIG_DM must be always enabled for that board.
So, using "select DM" is more suitable rather than allowing users to
modify it.  Another good thing is, Kconfig warns unmet dependencies
for "select" syntax, so we easily notice bugs.

Actually, CONFIG_DM and other related options have been added
without consistency: some into arch/*/Kconfig, some into
board/*/Kconfig, and some into configs/*_defconfig.

This commit prefers "select" and cleans up the following issues.

[1] Never use "CONFIG_DM=n" in defconfig files

It is really rare to add "CONFIG_FOO=n" to disable CONFIG options.
It is more common to use "# CONFIG_FOO is not set".  But here, we
do not even have to do it.
Less than half of OMAP3 boards have been converted to Driver Model.
Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is
weird.  Instead, add "select DM" only to appropriate boards, which
eventually eliminates "CONFIG_DM=n", etc.

[2] Delete redundant CONFIGs

Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again
in configs/sandbox_defconfig.
Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and
defines it also in omap3_beagle_defconfig and devkit8000_defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-18 11:11:30 -06:00
Simon Glass
90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
a274e9cac5 dm: x86: Add a uclass for an Low Pin Count (LPC) device
On x86 systems this device is commonly used to provide legacy port access.
It is sort-of a replacement for the old ISA bus.

Add a uclass for this, and allow it to have child devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
452f548753 dm: x86: Add a uclass for a Platform Controller Hub
Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.

The device can have children, so make it scan the device tree for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
ba4575626e dm: x86: spi: Convert ICH SPI driver to driver model
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
aad78d2732 dm: x86: pci: Convert chromebook_link to use driver model for pci
Move chromebook_link over to driver model for PCI.

This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)

This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
801f4f1bbc dm: x86: pci: Convert coreboot to use driver model for pci
Move coreboot-x86 over to driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
a219daeafe dm: x86: pci: Add a PCI driver for driver model
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
161d2e4e5b x86: Split up arch_cpu_init()
At present we do more in this function than we should. Split out the
post-driver-model part into a separate function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:41 -06:00
Simon Glass
31f57c2873 x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:41 -06:00
Simon Glass
51e9dad296 x86: Add support for panther (Asus Chromebox)
Support running U-Boot as a coreboot payload. Tested peripherals include:

- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash

USB3 does not work. This may be a problem with the USB3 PCI driver or
something in the USB3 stack and has not been investigated So far this is
disabled. The SD card slot also does not work.

For video, coreboot will need to run the OPROM to set this up.

With this board, bare support (running without coreboot) is not available
as yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:40 -06:00
Simon Glass
892ff8e972 x86: Support machines with >4GB of RAM
Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the memory size will not exceed the maximum.

This prevents gd->ram_size exceeding 4GB which causes problems for PCI
devices which use DMA.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-04-16 19:27:40 -06:00
Masahiro Yamada
326a682358 malloc_f: enable SYS_MALLOC_F by default if DM is on
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory.  Devices are scanned twice, before/after
relocation.  CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation.  As it is board-independent, handle it
globally.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
0a9e7ee5bd generic-board: select SYS_GENERIC_BOARD for some architectures
We have done with the generic board conversion for all the boards
of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86.

Let's select SYS_GENERIC_BOARD for those architectures, so we can
tell which architecture has finished the conversion at a glance.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Masahiro Yamada
0a12e6872e generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Bin Meng
e4ad6031a7 x86: quark: Enable on-chip ethernet controllers
Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this support with the existing U-Boot Designware MAC driver
so that the ethernet port on Intel Galileo board can be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-03-24 21:22:37 -06:00
Tom Rini
1c854dc5d4 arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIME
Using __DATE__ and __TIME__ results in an error due to -Werror=date-time
with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so
switch these over to U_BOOT_DATE / U_BOOT_TIME

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-03-24 21:22:37 -06:00
Bin Meng
312cc39e27 x86: quark: MRC codes clean up
This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 << n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis all over the codes
- Replace to use lower case hex numbers

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-03-24 21:22:37 -06:00
Rob Herring
7682a99826 remove unnecessary version.h includes
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
2015-03-24 10:50:50 -04:00
Simon Glass
b724bd7d63 dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig
Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 15:17:28 -07:00
Simon Glass
9a89d50d8e dm: x86: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:34 -07:00
Tom Rini
db7a7dee68 Merge branch 'master' of git://git.denx.de/u-boot-x86 2015-02-10 10:42:56 -05:00
Michal Simek
0267ba5d86 common: Move dram_init() declaration to common location
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-02-09 15:08:48 +01:00
Bin Meng
ba877efb80 x86: Use tab instead of space to indent in PCIE_ECAM_BASE
Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig
so it looks misaligned. Replace the space with tab to indent.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:46 -07:00
Bin Meng
6df7ffea13 x86: Add SD/MMC support to quark/galileo
Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
728b393f3b x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
d8b1d22512 x86: galileo: Add GPIO support
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
b162257d4f x86: quark: Initialize non-standard BARs
Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:44 -07:00
Bin Meng
20c34115d6 x86: quark: Call MRC in dram_init()
Now that we have added Quark MRC codes, call MRC in dram_init() so
that DRAM can be initialized on a Quark based board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:44 -07:00
Bin Meng
236b711e89 x86: quark: Enable the Memory Reference Code build
Turn on the Memory Reference code build in the quark Makefile.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Bin Meng
b829f12afa x86: quark: Add System Memory Controller support
The codes are actually doing the memory initialization stuff.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Bin Meng
38ad43e436 x86: quark: Add utility codes needed for MRC
Add various utility codes needed for Quark MRC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Bin Meng
0a391b1c79 x86: quark: Add Memory Reference Code (MRC) main routines
Add the main routines for Quark Memory Reference Code (MRC).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
ea94532461 x86: quark: Bypass TSC calibration
For some unknown reason, the TSC calibration via PIT does not work on
Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
to 400 per Quark datasheet in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
f56aeaa4ac x86: Allow overriding TSC_FREQ_IN_MHZ
We should allow the value of TSC_FREQ_IN_MHZ to be overridden by
the one in arch/cpu/<xxx>/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
ef46bea02b x86: Enable the Intel quark/galileo build
Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
afee3fb8c8 x86: Add basic Intel Galileo board support
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00
Bin Meng
828d9af5ec x86: Add basic Intel Quark processor support
Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd->ram_size is assigned.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00
Bin Meng
0fae4d24df x86: quark: Add Cache-As-RAM initialization
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00
Bin Meng
3c8ae536ec x86: Define macros for pci configuration space access
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
macros can be used for pci configuration space access.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:40 -07:00
Bin Meng
faa8323299 x86: quark: Add routines to access message bus registers
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:40 -07:00
Bin Meng
b994efbd2d x86: Add header files for Intel Quark SoC defines
device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:40 -07:00
Simon Glass
3a1a18ff18 x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:39 -07:00
Simon Glass
447f8b018e x86: Allow a UART to be set up before the FSP is ready
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:38 -07:00
Simon Glass
8ce24cd991 x86: Allow FSP Kconfig settings for all x86
While queensbay is the first chip with these settings, others will want to
use them too. Make them common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:38 -07:00
Simon Glass
f0809f9a38 x86: Remove unnecessary casts and fix comment typos
Tidy up the FSP support code a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:37 -07:00
Simon Glass
91785f70b9 x86: mmc: Move common FSP functions into a common file
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.

This creates a generic PCI MMC device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:36 -07:00
Simon Glass
7b02bf3c7d x86: Make CAR and DRAM FSP code common
For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:44 -07:00
Simon Glass
82196cf34f x86: Adjust the FSP types slightly
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
1021af4ded x86: Move common FSP code into a common location
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
bc17d8f4ac x86: video: Allow video ROM execution to fall back to the other method
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
2d934e5703 x86: Rename MMCONF_BASE_ADDRESS and make it common across x86
This setting will be used by more than just ivybridge so make it common.

Also rename it to PCIE_ECAM_BASE which is a more descriptive name.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
380ab5cc27 x86: ivybridge: Drop the Kconfig MRC cache information
This is now stored in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:46 -07:00
Simon Glass
069f5481ba x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:45 -07:00
Simon Glass
191c008a21 x86: Implement a cache for Memory Reference Code parameters
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.

Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
a9aff2f46a x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
b18c68d891 x86: Use ipchecksum from net/
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:44 -07:00
Bin Meng
fea1c47f54 x86: Fix various code format issues in start16.S
Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
3b621ccabd x86: Test mtrr support flag before accessing mtrr msr
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
4949166906 x86: Save mtrr support flag in global data
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
566d1754d3 x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.c
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Sebastien Ronsse
07570e7097 x86: Fix out of bounds irq handlers access
Using coreboot-x86_defconfig, the following error occurred prior to this modification:
CC	arch/x86/lib/interrupts
arch/x86/lib/interrupts.c: In function ‘do_irqinfo’:
arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations]
   if (irq_handlers[irq].handler != NULL) {
                        ^
arch/x86/lib/interrupts.c:133:2: note: containing loop
  for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) {
  ^
cc1: all warnings being treated as errors
scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed
make[1]: *** [arch/x86/lib/interrupts.o] Error 1
Makefile:1093: recipe for target 'arch/x86/lib' failed
make: *** [arch/x86/lib] Error 2

Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e
Signed-off-by: Sebastien Ronsse <sronsse@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Simon Glass
bdc88d4eb3 x86: Support ROMs on other archs
We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-23 17:24:15 -07:00
Bin Meng
cdcc17d73d x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:05 -08:00
Bin Meng
ade8127a79 x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Bin Meng
9d74f03460 x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
7698d36a10 x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
8cb20ccc34 x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
3ba6a0f4f6 x86: Allow a hardcoded TSC frequency provided by Kconfig
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.

Normally the bypass should be turned on in a simulation environment
like qemu.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
5c564b0d2f x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
b2439aecd3 x86: fsp: Drop get_hob_type() and get_hob_length()
These two are not worth having separate inline functions as they are
really simple, so drop them.

Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
cb3b2e62ca x86: Add an 'mtrr' command to list and adjust MTRRs
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:25:02 -08:00
Simon Glass
c72f74e278 x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.

For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
801d70ce02 x86: Disable CAR before relocation on platforms that need it
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
7b00896ade x86: ivybridge: Add a way to turn off the CAR
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
db55bd7dad x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
aaafcd6c3f x86: ivybridge: Request MTRRs for DRAM regions
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
9818a00eea x86: ivybridge: Set up an MTRR for the video frame buffer
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
aff2523f69 x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
3a5659f7cf x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
f4a6f0aed0 x86: Tidy up VESA mode numbers
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
818f602112 x86: Use cache, don't clear the display in video BIOS
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
d19ee5c27e x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is
not considered at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Simon Glass
6c911c4322 x86: Drop RAMTOP Kconfig
We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:58 -08:00
Simon Glass
bbd43d659c x86: Correct XIP_ROM_SIZE
This should default to the size of the ROM for faster execution before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Bin Meng
b21b208184 x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
1eb47efc49 x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
949dbc12db x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
8f9052fd98 pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
fa5530b85d x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
4722c035cf x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
120c41695b x86: Clean up the board dts files
This commits cleans up the board dts files.

- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
  serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
  dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
  skeleton.dtsi

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
9ca5a0ca0e x86: Rename coreboot.dsti to serial.dtsi
The name of coreboot.dtsi is misleading, as it actually describes
the legacy serial port device node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
57706e4bd6 x86: Remove alex.dts in arch/x86/dts
No board is using alex.dts, so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
255fd5caa5 x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
41702bac01 x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
aada6276c6 x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
adfe3b247a x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
8c5224c9f5 x86: Use consistent name XXX_ADDR for binary blob flash address
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
58f542de30 x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
240a79d95c x86: Enable the queensbay cpu directory build
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
b71eec3129 x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Simon Glass
0f61de8d9d x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:06 -07:00
Bin Meng
b2e02d2865 x86: Add basic support to queensbay platform and crownbay board
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
efbeeafe95 x86: Integrate Tunnel Creek processor microcode
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
b591ee3913 x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.

Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
cf29e3e303 x86: ivybridge: Update the microcode
There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
81f79ef792 x86: Move microcode updates into a separate directory
We might end up with a few of these, so put them in their own directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:05 -07:00
Masahiro Yamada
e6126a5872 x86: move arch-specific asmlinkage to <asm/linkage.h>
Commit 65dd74a674 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.

Commit ed0a2fbf14 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)

The generic asmlinkage is defined in <linux/linkage.h>.  If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-15 07:22:53 -07:00
Bin Meng
ba7b38a529 x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:06 -07:00
Bin Meng
bceb9f0fc8 x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
95a5a47466 x86: Add post failure codes for bist and car
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
8e04d4c537 x86: queensbay: Adapt FSP support codes
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 22:32:05 -07:00
Bin Meng
752a0b085b x86: Initial import from Intel FSP release for Queensbay platform
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.

For more details, check http://www.intel.com/fsp.

Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 22:32:05 -07:00
Bin Meng
a2927e09bc x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
568868dda9 x86: Add Intel Crown Bay board dts file
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
2795573a8c x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
fe0c33a5ac x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
64542f4616 x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:03 -07:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Daniel Schwierzeck
e19db555b4 Kbuild: introduce Makefile in arch/$ARCH/
Introduce a Makefile under arch/$ARCH/ and include it in the
top Makefile (similar to Linux kernel). This allows further
refactoringi like moving architecture-specific code out of global
makefiles, deprecating config variables (CPU, CPUDIR, SOC) or
deprecating arch/$ARCH/config.mk.

In contrary to Linux kernel, U-Boot defines the ARCH variable by
Kconfig, thus the arch Makefile can only included conditionally
after the top config.mk.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:45 -05:00
Simon Glass
f3e56fe369 x86: dts: Add video information to the device tree
This provides panel timing information needed by the video driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
0ca2426bea x86: Add support for running option ROMs natively
On x86 machines we can use an emulator to run option ROMS as with other
architectures. But with some additional effort (mostly due to the 16-bit
nature of option ROMs) we can run them natively. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:38:57 -07:00
Simon Glass
22465fc46c x86: Add vesa mode configuration options
Add Kconfig options to allow selection of a vesa mode on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:15 -07:00
Simon Glass
e34aef1de3 x86: Add GDT descriptors for option ROMs
Option ROMs require a few additional descriptors. Add these, and remove the
enum since we now have to access several descriptors from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
24774278c9 x86: ivybridge: Add northbridge init functions
Add init for the northbridge, another part of the platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
d1ef1132bb x86: Drop some msr functions that we don't support
These are not available in U-Boot as yet, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
0c9075e9ad x86: Add LAPIC setup code
Add code to set up the Local Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:11 -07:00
Simon Glass
b636dd1079 x86: Drop old CONFIG_INTEL_CORE_ARCH code
This is no-longer used, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:03 -07:00
Bin Meng
1dae2e0eb6 x86: Refactor interrupt_init()
Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
a549f7497b x86: Remove cpu_init_r() for x86
Since cpu_init_interrupts() was moved out of cpu_init_r(), it is
useless to keep cpu_init_r() for x86, thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
4372a9eca5 x86: Call cpu_init_interrupts() from interrupt_init()
Currently cpu_init_interrupts() is called from cpu_init_r() to
setup the interrupt and exception of the cpu core, but at that
time the i8259 has not been initialized to mask all the irqs
and remap the master i8259 interrupt vector base, so the whole
system is at risk of being interrupted, and if interrupted,
wrong interrupt/exception message is shown.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
18739e2ccc x86: Add Intel speedstep and turbo mode code
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
a6d4c45306 x86: ivybridge: Set up XHCI USB
Add init for XHCI so that high-speed USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
9baeca4b89 x86: ivybridge: Set up EHCI USB
Add init for EHCI so that USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
4896f4acc8 x86: dts: Add SATA settings for link
Add the requires settings to enable SATA on link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
3ac839352d x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
05efc3961c x86: dts: Add LPC settings for link
Add some settings required to set up the LPC correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
b021e05535 x86: dts: Move PCI peripherals into a pci node
These peripherals should not be at the top level, since they exist inside
the PCI bus. We don't have a full device tree node for pci yet, but we
should at least put it at the right level.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
72cd085aae x86: ivybridge: Add additional LPC init
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
8c74a57318 x86: ivybridge: Add PCH init
Add required init for the Intel Platform Controller Hub in ivybridge.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
3e0332c0b9 x86: Add a simple header file for ACPI
We don't use many features yet, so this only has a few declarations.
It will be expanded as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
4e7a6acac7 x86: ivybridge: Add support for BD82x6x PCH
Add basic setup for the PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
a0bd851ece x86: Set up edge triggering on interrupt 9
Add this additional init in case it is needed by the OS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:00 -07:00
Simon Glass
e94ea6f656 x86: pci: Add handlers before and after a PCI hose scan
Some boards will want to do some setup before and after a PCI hose
is scanned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:00 -07:00
Simon Glass
a2f5d091cc x86: Add ioapic.h header
Add definitions for the I/O Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:33:59 -07:00
Simon Glass
a6a957849a x86: Factor out common values in the link script
Define the reset base in config.mk so that it does not need to be calculated
twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values
to fit with this new approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
091c494353 x86: Ensure that all relocation data is included in the image
Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
512e581c86 x86: Panic if there is no relocation data
This normally indicates a problem which will prevent relocation from
functioning, resulting in a hang. Panic in this case to make it easier
to debug.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
65990d5680 x86: Remove board_early_init_r()
This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
2f6d42b9df x86: Add ivybridge directory to Makefile
It is now required to add subdirectories in the x86 cpu Makefile. Add this
to fix a build breakage for chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:33:56 -07:00
Tom Rini
746667f1e5 Merge git://git.denx.de/u-boot-x86
Conflicts:
	arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:00:00 -05:00
Masahiro Yamada
37c9940a09 x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
165ecd26f0 kbuild: Descend into SOC directory from CPU directory
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Simon Glass
fe5b9b447c x86: Rename chromebook-x86 to coreboot
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.

So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it would be possible to remove the vendor for
now, that would be short-sighted.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:16 +01:00
Simon Glass
65dd74a674 x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
3eafce0527 x86: ivybridge: Add LAPIC support
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
a49e3c7f09 x86: Make show_boot_progress() common
This function can probably be used on all x86 boards, so move it into the
common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
437c2b7cd0 x86: chromebook_link: Enable GPIO support
Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
1b4f25ff8e x86: ivybridge: Add support for early GPIO init
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.

In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
8e0df066ff x86: ivybridge: Add early init for PCH devices
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
9c678e152a x86: dts: Add microcode updates for ivybridge CPU
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.

Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
77f9b1fb62 x86: ivybridge: Perform Intel microcode update on boot
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
94060ff278 x86: ivybridge: Check BIST value on boot
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
f5fbbe9579 x86: ivybridge: Perform initial CPU setup
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
eddbad224b x86: Add msr read/write functions that use a structure
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
3f70a6f577 x86: Add clr/setbits functions
These are available on other architectures. Make them available on x86 also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
378a8634ad x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
2b6051541b x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6fb3b72e87 x86: pci: Allow configuration before relocation
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6e5b12b614 x86: ivybridge: Enable PCI in early init
Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
7430f10864 x86: Support use of PCI before relocation
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:12 +01:00
Simon Glass
d188b18f65 x86: Refactor PCI to permit alternate init
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
70a09c6c3d x86: chromebook_link: Implement CAR support (cache as RAM)
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
d1cd045982 x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
fce7b27683 x86: Build a .rom file which can be flashed to an x86 machine
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.

Create a u-boot.rom output file for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
8ef07571a0 x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
5c1b685e46 x86: Allow timer calibration to work on ivybridge
Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.

For this CPU we know the frequency, so add another special case for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Masahiro Yamada
a5eb04db1a x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:12 +01:00
Simon Glass
727c1a9871 x86: Replace fill_processor_name() with cpu_get_name()
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
003504b6fe x86: Remove unnecessary find_fdt(), prepare_fdt() functions
These are no-longer needed so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
21b9b14b49 x86: Add processor functions to halt and get stack pointer
Add a function to get the stack pointer and another to halt the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
6cba6b9209 x86: Fix a warning with gcc 4.4.4
This warning appears even though it seems that the compiler could work it
out. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
258b1357c6 x86: Save TSC frequency in the global data
Return the saved TSC frequency in get_tbclk_mhz().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
80de049561 x86: Add quick TSC calibration via PIT
Use the same way that Linux does for quick TSC calibration via PIT
when calibration via MSR fails.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
076bb44b0e x86: Do TSC MSR calibration only for known/supported CPUs
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00