Simon Glass a9aff2f46a x86: dts: Add SPI flash MRC details for chromebook_link ... Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>		2015-01-24 06:13:45 -07:00
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cpu	x86: Use ipchecksum from net/	2015-01-24 06:13:44 -07:00
dts	x86: dts: Add SPI flash MRC details for chromebook_link	2015-01-24 06:13:45 -07:00
include/asm	x86: Use ipchecksum from net/	2015-01-24 06:13:44 -07:00
lib	x86: Test mtrr support flag before accessing mtrr msr	2015-01-23 17:24:55 -07:00
config.mk	x86: Remove REALMODE_BASE which is no longer used	2014-11-21 07:24:08 +01:00
Kconfig	x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig	2015-01-13 07:25:03 -08:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00