Commit graph

15700 commits

Author SHA1 Message Date
Patrick Delaunay
d46c22b3fd power: stpmu1: rename files to stpmic1
Prepare file modification for kernel alignment and
rename driver to stpmic1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
17f1f9b176 stm32mp1: Replace OTP read by SHADOW read
Replace STM32_BSEC_OTP() by STM32_BSEC_SHADOW() to
increase read performance.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
815bc8bc94 stm32mp1: bsec: shadow all the upper OTP (no secure) during boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
bfe1f08f88 stm32mp1: bsec: use device tree new compatible
Update bsec driver to use the device tree provided by Kernel.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
59a54e37a6 stm32mp1: basic boot: SPL enable access to GPIOZ bank
SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank
(open security).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
8983ba2751 stm32mp1: align serial number on bootrom
Always use upper case for serial number.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
6c09eb9e7e stm32mp1: add some syscon drivers for syscfg and etpzc
Add SYSCON driver for syscfg and etpzc and reorder in alphabetics order

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
9a2ba2838b stm32mp1: support forced boot mode
The boot mode can be forced by key press
or by TAMP register, requested in kernel by syscon-reboot-mode

tamp: tamp@5c00a000 {
	compatible = "simple-bus", "syscon", "simple-mfd";
	reg = <0x5c00a000 0x400>;

	reboot-mode {
		compatible = "syscon-reboot-mode";
		offset = <0x150>; /* reg20 */
		mask = <0xff>;
		mode-normal = <0>;
		mode-fastboot = <0x1>;
		mode-recovery = <0x2>;
		mode-stm32cubeprogrammer = <0x3>;
		mode-ums_mmc0 = <0x10>;
		mode-ums_mmc1 = <0x11>;
		mode-ums_mmc2 = <0x12>;
	};
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
105a5ad614 stm32mp1: spl: hang with trace when DDR init failed
When DDR initialization failed, print error message
and stop the SPL execution.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
b496eec65d stm32mp1: cosmetic: add comment on psci_migrate_info_type return value
Add explaination for the return value of psci_migrate_info_type:
  2 = Trusted OS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
45ccdb6fc7 stm32mp1: cosmetic cleanup Kconfig
Cosmetic cleanup in mach-stm32mp Kconfig
- remove duplicated SPL_DRIVERS_MISC_SUPPORT
- update help for TARGET_STM32MP1
- set value for NR_DRAM_BANKS
- remove one comment as DEBUG_UART is deactivated by default
- include board Kconfig at the end of the file

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
006ea18910 stm32mp1: spl: add spl_display_print
SPL displays the board model from device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
35d568f090 stm32mp1: update print_cpuinfo()
Display CPU part number and package information.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
7f63c1e687 stm32mp1: update boot mode management
- export the function get_bootmode() and reused it in spl code
- manage uart instance by alias (prepare v4.19 binding)
- solve issue on nand instance
- restore console for uart boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
b4ae34b66b stm32mp1: add runtime information in environment
Set board name with the first dts compatible found in DT
code under CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

The result with DEVICE_TREE=stm32mp157c-ev1 is:
    STM32MP> env print
    	board=stm32mp1
    	board_name=stm32mp157c-ev1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
d461f10036 stm32mp1: display board information
Implement checkboard() function to display
- the boot chain used: basic or trusted
- the board compatible in device tree
- the board identifier and revision, saved in OTP59 for ST boards

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
d859c61139 stm32mp1: bsec: access with SMC for trusted boot
As BSEC is secure aware, all register access need to be done
by TF-A for TRUSTED boot chain, when U-Boot is executed in
normal world.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
abf2678f0f stm32mp1: add trusted boot with TF-A
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
  BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32

The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power

The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Faiz Abbas
fddfd9c7b0 ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
2019-04-12 08:05:56 -04:00
Faiz Abbas
2499a04617 ARM: dts: dra7: Change pbias voltage to 3.3V
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.

Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.

[1] http://www.ti.com/lit/pdf/sprui30

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12 08:05:56 -04:00
Tom Rini
9c4b0131d1 ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option.  Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
2019-04-12 08:05:55 -04:00
Andreas Dannenberg
3e9b9c1ccd armv7R: K3: am654: Trigger panic on DDR init failures
When initializing DDR from R5 SPL trigger U-Boot's panic facility
rather than simply returning from the board init function as there
is little point continuing code execution. Further, as panic implies
a board reset, so using it might potentially allow to recover from
this error in certain cases such as when the init failure was caused
by a temporary glitch of some sorts.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12 08:05:52 -04:00
Lokesh Vutla
a9a84480f4 arm: k3: Add support for updating msmc dt node
Certain parts of msmc sram can be used by DMSC or can be
marked as L3 cache. Since the available size can vary, changing
DT every time the size varies might be painful. So, query this
information using TISCI cmd and fixup the DT for kernel.
Fixing up DT does the following:
- Create a sram node if not available
- update the reg property with available size
- update ranges property
- loop through available sub nodes and delete it if:
	- mentioned size is out if available range
	- subnode represents l3 cache or dmsc usage.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12 08:05:51 -04:00
Lokesh Vutla
6ce424a920 arm: k3: Add a wrapper to get tisci handle
Create a wrapper to get the ti sci handle.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12 08:05:51 -04:00
Adam Ford
f7c1d53605 ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATA
With the memory mapping giving us some more avialable RAM, this
updates the da850-evm-u-boot.dtsi to include the serial port, SPI
and Flash nodes along with some dependent nodes in the SPL dtb.
This also removes the platform data initialization code for the
serial port and SPI Flash.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-12 08:05:49 -04:00
Sjoerd Simons
4512380420 am335x, guardian: Add support for the bosch guardian board
Add support for the Bosch Guardian board.

CPU  : AM335X-GP rev 2.1
Model: Bosch AM335x Guardian
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Felix Brack <fb@ltec.ch>
2019-04-12 08:05:48 -04:00
Sjoerd Simons
f50939647c Add support for the MT41K128M16JT125K memory modules
Add configuration for the MT41K128M16JT125K memory modules as used on the
Bosch Guardian device.

Based on a patch by:
    Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com>

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
[checkpatch.pl cleanup by Martyn Welch]
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2019-04-12 08:05:48 -04:00
Murali Karicheri
32d858fc4f ARM: dts: k2g-ice: add dt node for netcp
This patch adds dt node for DP83867 phy used on K2G ICE board and
also enable netcp device nodes for the board.

EVM hardware spec recommends to add 0.25 nsec delay in the tx
direction and 2.25 nsec delay in the rx direction for internal
delay in the clock path to be on the safer side.

The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode
1. Unfortunately, the phy data manual disallows this. Add
ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to
enable workaround suggested for this incorrect strap setting. This
ensures proper operation of this PHY.

The dts bindings are kept in sync with that from 4.14.y linux
kernel. This required the pinmux device related bindings to be
commented out to allow for compilation.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:47 -04:00
Murali Karicheri
b186f4b1a2 ARM: dts: k2g-evm: remove unused phy-mode property from phy node
This patch removes the unused phy-mode property from the phy dt node. On
K2G, currently link-interface determines if phy is used or not and is
already set to use rgmii. So this is not needed. Besides phy-mode should
be added to slave interface configuration of the cpsw driver, not in the
phy node.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:46 -04:00
Murali Karicheri
f748ec9d32 ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:46 -04:00
Murali Karicheri
c7206e9789 ARM: k2g-ice: Add pinmux support for rgmii interface
This add pinmux configuration for rgmii interface so that network
driver can be supported on K2G ICE boards. The pinmux configurations
for this are generated using the pinmux tool at
https://dev.ti.com/pinmux/app.html#/default

As this required some BUFFER_CLASS definitions, same is re-used
from the linux defnitions in include/dt-bindings/pinctrl/keystone.h

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12 08:05:45 -04:00
Neil Armstrong
51e4e3e5d0 x86: dts: switch spi-flash to jedec, spi-nor compatible
The x86 code and DT uses "spi-flash" to detect a flash node, switch to
"jedec,spi-nor" in the DTS files and in fdtdec by switching the
GENERIC_SPI_FLASH value to to jedec,spi-nor.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Neil Armstrong
ffd4c7c2ec dts: switch spi-flash to jedec, spi-nor compatible
There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot
dts files. This compatible has been added in sf_probe, let use it.

This patch switches to jedec,spi-nor when spi-flash is used in the DTS
and DTSI files, and removed spi-flash when jedec,spi-nor is already
present.

The x86 dts are switched in a separate commit since it depends on a change
in fdtdec.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Chris Packham
937cb9d0a6 ARM: mvebu: sync db-88f6820-amc.dts with Linux v5.0
Sync armada-385-db-88f6820-amc.dts with Linux. Retain the
u-boot,dm-pre-reloc and nand differences.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:20:20 +02:00
Chris Packham
205c75e88c ARM: mvebu: rename armada-385-amc.dts to armada-385-db-88f6820-amc.dts
This board was added to u-boot first but the Linux maintainers requested
a more descriptive name. Rename the file to match the Linux usage and
update the board defconfig.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:20:10 +02:00
Leigh Brown
93b3e81212 ARM: kirkwood: remove obsolete call to icache_enable
Commit 93b283d49f ("ARM: CPU: arm926ejs: Consolidate cache routines to
common file") changed cache setup for Kirkwood such that icache_enable()
is now called from enable_caches() which is called from initr_caches()
which is in the list of functions in init_sequence_r[] prior to
arch_misc_init().  This means the call to icache_enable() in
arch_misc_init() is no longer required, so remove it.

Signed-off-by: Leigh Brown <leigh@solinno.co.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
4db944ab44 arm: mvebu: Add DB-XC3-24G4XG board
The DB-XC3-24G4XG is a switch development board from Marvell. It can
either use and external CPU card such as the db-88f6820-amc or the
internal CPU that is integrated into the switch.

Add support for running U-Boot on the internal CPU and enable the USB,
SPI and NAND peripherals. For now this needs the bin_hdr from the
Marvell U-Boot for this board.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
689f9cf6aa arm: mvebu: NAND clock support for MSYS devices
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
0d0df46ee7 arm: mvebu: Add Marvell's integrated CPUs
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Stefan Roese
237b629e4c arm: mvebu: Fix Kconfig dependency warnings
We now have MEVBU boards without SPL support (e.g. db-xc3-24g4xg).
Because of this, a new compile time warning from Kconfig is show:

WARNING: unmet direct dependencies detected for SPL_OF_CONTROL
  Depends on [n]: SUPPORT_OF_CONTROL [=y] && SPL [=n] && OF_CONTROL [=y]
  Selected by [y]:
  - ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y]

WARNING: unmet direct dependencies detected for SPL_DM
  Depends on [n]: DM [=y] && SPL [=n]
  Selected by [y]:
  - ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y]
...

This patch fixes this issue and removes these warnings.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
2019-04-12 07:04:18 +02:00
Stefan Roese
0a590243d1 arm: mvebu: AXP: Enhance PCIe port capability configuration
This patch enables the PCIe port specific link capabilities configuration
for Armada XP. The weak function board_sat_r_get() was used to return
a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This
is now changed with this patch to return a bit per PCIe port (4 bits
in this case, bit 0 for PCIe port 0, etc).

The theadorable board uses this new feature to configure PCIe port 0
as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards
using this function are not changed in the configuration and still
configure all ports as PCIe Gen2.

This patch also removes the parameter "pex_mode" from
board_serdes_cfg_get() as this parameter was not used in any of the
implementations.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
2019-04-12 07:04:18 +02:00
Baruch Siach
4b11e5f6b3 ARM: mvebu: define board_ahci_enable() for A38x
This allows the ahci_mvebu driver to do A38x platform specific
configuration at initialization.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
fa8d96f625 ARM: kirkwood: remove kw_config_adr_windows
Now that kirkwood is using the mvebu mbus this function is no longer
needed.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
8ef078b4be ARM: kirkwood: switch to using mvebu mbus
The mvebu mbus code already had most of the support required for
kirkwood. The only difference is that unlike the other mvebu targets
kirkwood doesn't have a bridge control block so the code related to
managing that needs to be compiled out.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
35f1ee6474 ARM: kirkwood: remove KW_DEFADR_PCI_IO_REMAP
KW_DEFADR_PCI_IO_REMAP has the same value as KW_DEFADR_PCI_IO and is
only used to set up a 1:1 mapping. Remove it and update the mapping to
use KW_DEFADR_PCI_IO.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
d131ac4845 ARM: kirkwood: rename KW_CPU_WIN_BASE to MVEBU_CPU_WIN_BASE
This will allow the kirkwood platforms to use more common code with the
other mvebu SoCs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
7ceefcbaca arm: mvebu: x530: Enable watchdog in SPL and U-Boot
Enable the hardware watchdog to guard against system lock ups when
running in the SPL or U-Boot. Stop the watchdog just before booting so
that the OS can re-enable it if needed.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Chris Packham
3c265bbe4d arm: sync armada-xp dts files from Linux 5.0
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't
got the new NAND driver the updating binding has not been included.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12 07:04:18 +02:00
Christian Gmeiner
6539700d93 dm: sound: make all functions static inline
Fixes following compile problem:
➜  u-boot-mainline git:(master) ✗ make sandbox_defconfig all NO_SDL=1
scripts/kconfig/conf  --syncconfig Kconfig
  CHK     include/config.h
  CFG     u-boot.cfg
  GEN     include/autoconf.mk
  GEN     include/autoconf.mk.dep
  CHK     include/config/uboot.release
  CHK     include/generated/version_autogenerated.h
  CHK     include/generated/timestamp_autogenerated.h
  UPD     include/generated/timestamp_autogenerated.h
  CHK     include/generated/generic-asm-offsets.h
  HOSTCC  tools/mkenvimage.o
  HOSTLD  tools/mkenvimage
  HOSTCC  tools/fit_image.o
  HOSTCC  tools/image-host.o
  HOSTCC  tools/dumpimage.o
  HOSTLD  tools/dumpimage
  HOSTCC  tools/mkimage.o
  HOSTLD  tools/mkimage
  HOSTLD  tools/fit_info
  HOSTLD  tools/fit_check_sign
  CC      cmd/version.o
  GZIP    cmd/config_data.gz
  CHK     cmd/config_data_gz.h
  CHK     cmd/config_data_size.h
  CHK     cmd/license_data_gz.h
  CHK     cmd/license_data_size.h
  LD      cmd/built-in.o
  CC      common/main.o
  LD      common/built-in.o
  CC      drivers/fastboot/fb_getvar.o
  LD      drivers/fastboot/built-in.o
  LD      drivers/video/built-in.o
ld.bfd: drivers/video/sandbox_sdl.o: in function `sandbox_sdl_sound_play':
/home/christian/projects/u-boot-mainline/./arch/sandbox/include/asm/sdl.h:110: multiple definition of `sandbox_sdl_sound_play'; drivers/video/video-uclass.o:/home/christian/projects/u-boot-mainline/./arch/sandbox/include/asm/sdl.h:110: first defined here
ld.bfd: drivers/video/sandbox_sdl.o: in function `sandbox_sdl_sound_init':
/home/christian/projects/u-boot-mainline/./arch/sandbox/include/asm/sdl.h:120: multiple definition of `sandbox_sdl_sound_init'; drivers/video/video-uclass.o:/home/christian/projects/u-boot-mainline/./arch/sandbox/include/asm/sdl.h:120: first defined here
make[3]: *** [scripts/Makefile.build:355: drivers/video/built-in.o] Fehler 1
make[2]: *** [scripts/Makefile.build:432: drivers/video] Fehler 2
make[1]: *** [Makefile:1531: drivers] Fehler 2
make: *** [Makefile:485: __build_one_by_one] Fehler 2

Fixes: f2b25c9bf8 ("dm: sound: Complete migration to driver model")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-04-11 20:10:50 -06:00
Thierry Reding
553a1a26e8 sandbox: Properly print physical addresses
Use the %pap printf specifier to print physical addresses. The physical
address is passed by reference and hence avoids the need to play tricks
with the preprocessor to use the correct specifier.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11 20:10:05 -06:00
Thierry Reding
0c425ae4b7 sandbox: Use correct phys_{addr, size}_t for PHYS_64BIT=y
If 64-bit physical addresses support is enabled, make sure the sandox
defines the correct types for phys_addr_t and phys_size_t.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11 20:10:05 -06:00
Patrick Delaunay
a442e61e24 syscon: update syscon_regmap_lookup_by_phandle
Change the function syscon_regmap_lookup_by_phandle()
introduced by commit 6c3af1f24e ("syscon: dm: Add a
new method to get a regmap from DTS") to have
Linux-compatible syscon API.

Same modification than commit e151a1c288 ("syscon: add
Linux-compatible syscon API") solves issue when the node
identified by the phandle has several compatibles and is
already bound to a dedicated driver.

See Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon
interface from platform devices").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11 20:10:05 -06:00
Grygorii Strashko
736b6c3f87 arm64: dts: ti: k3-am65: add mcu navss nodes
Add DT node for MCU NAVSS its components to get DMA working on AM654
SoC.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11 20:07:12 -04:00
Vignesh R
91dba55ca6 soc: keystone: Merge into ti specific directory
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11 20:07:12 -04:00
Grygorii Strashko
fd6b40b1ba firmware: ti_sci: Add support for NAVSS resource management
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.

This patch adds support for requesting and configuring such resources
from TI-SCI firmware.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11 20:07:12 -04:00
Tom Rini
f95fdf237d Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various rmobile fixes
2019-04-11 14:29:22 -04:00
Lukasz Majewski
9eba5e4160 DTS: imx53: Add imx53-kp-u-boot.dtsi file with u-boot specific property
This file adds the "u-boot,i2c-transaction-bytes" to mc34708 PMIC.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-11 15:21:33 +02:00
Neil Armstrong
91fe071cd0 ARM: dts: Import libretech-ac DT from Linux 5.0
Import Linux 5.0 DT from 1c163f4c7b3f ("Linux 5.0") for the
meson-gxl-s805x-libretech-ac board and the corresponding changes
in meson-gxl.dtsi.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:50:46 +02:00
Julien Masson
f41d723b9f ARM: meson: display Amlogic SoC Information
The Amlogic SoCs have a registers containing the die revision
and packaging type to determine the SoC family and package marketing
name like S905X for the GXL SoC Family.

This code is taken from the Linux meson-gx-socinfo driver and adapted
to U-Boot printing.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: also updated new p200/p201 defconfigs]
2019-04-10 16:48:31 +02:00
Mohammad Rasim
56c74b6ce2 ARM: dts: meson: add u-boot.dtsi for p200 and p201
This adds *-u-boot.dtsi files for p200 and p201 boards
These are just copies of arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:48:31 +02:00
Mohammad Rasim
92e5f31b04 ARM: dts: meson: add p200 and p201 boards
This adds the device trees for p200 and p201 boards.
Synced from kernel 5.0.0
Commit: a667cb7a94d4 ("Merge branch 'akpm' (patches from Andrew)")

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:48:31 +02:00
Mohammad Rasim
4778afcbe7 ARM: board: meson: rename odroid-c2 to p200
This renames the odroid-c2 to p200 and set it as the default GXBB board
Other boards (odroid-c2 and nanopi-k2) will inherit from p200

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-10 16:48:31 +02:00
Andre Przywara
067e0b9684 sunxi: Allow booting from 128KB SD/eMMC offset
On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can
actually load the SPL also from sector 256 (128KB) of an SD card or eMMC
chip. For more details, see [1].
In this case the boot source indicator (written at offset 0x28 of SRAM A1)
has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC.

Add those new values to the existing boot source check to allow booting
the SPL from those "high" disk offsets as well. For this to work, the
value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted,
for instance to 0x140 (right after the high SPL). Doing this dynamically
sounds desirable, but looks nasty to implement.

[1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9d0f9e8374 arm: sunxi: Enable DRAM ODT by default on H3/H5
Most of the boards we support with H3/H5 enable DRAM on-die termination,
which is consistent with the high DRAM clocks that are used.

Make it the default (like it's done for other similar platforms) instead
of defining it in each defconfig.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
882b71e47d arm: sunxi: Set the default DRAM ZQ value to 3881979 on H3/H5
Most H3/H5 boards we support have the DRAM ZQ value set to 3881979,
which is also consistent with the default set for the R40.

Make this value the default on H3/H5 instead of 123.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9c2b0ddc41 arm: sunxi: Allow per-platform DRAM ZQ configuration on sun8i
A few sun8i platforms define specific default DRAM ZQ values, but they
are not taken in account because of MACH_SUN8I being used for the 123
default first.

Replace MACH_SUN8I with the list of platforms that don't have specific
DRAM ZQ values, to avoid overwriting the default for those that do.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Michael Trimarchi
ddd6930215 sunxi: dram_sun8i: Fix A33 memory initialization
While the exact problem is not known, based on discussion between
Philipp Tomsich and André Przywara it is guessed that exit self-refresh
timing is not set with correct value. There may be implicit enter or
exit Self-Refresh anywhere as part of some training phase.

In ZynqMP register guide [1], which is close to the various
Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL
tXS is bits [6:0]: Self refresh exit delay. So it could be safely
increased and it only affects the time after the self-refresh “exit”,
which happens only after (re-)initialisation.

There was no document for cpu in question so based on oscilloscope
readings [2][3] and observed result by comparing allwinner architecture.
So set it same as  Allwinner H5 silicon.

Before this patch, failure rate of was 7%.

This was tested on A33 allwinner cpu, dual rank connection connected
with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3
1.5V

And also this is tested in A33-OLinuXino dev board.

[1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html
[2] https://ibb.co/R70zmyS
[3] https://ibb.co/HVVCGQ8

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:32:59 +05:30
Jagan Teki
1692c73ccb sun50i: a64: Add Oceanic 5205 5inMFD initial support
Oceanic 5205 5inMFD is a 5 inch Multi function display baseboard
designed to mount SoPine SOM.

Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- SD Slot
- SPI-NOR flash
- EMAC, RTL8211E
- MCP2515 CAN
- 4-lane, MIPI-DSI panel
- Goodix 911 CTP
- USB Host
- 12V DC power supply

Linux commit details about the sun50i-a64-oceanic-5205-5inmfd.dts sync:
"arm64: allwinner: a64: Add Oceanic 5205 5inMFD initial support"
(sha1: 00f7980a3bd53d12abc34f68146a8eed0e894248)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-10 15:25:38 +05:30
Marek Vasut
81abfa68f1 ARM: dts: rmobile: Enable USB on E2 Alt
The E2 Alt board has two USB ports, add missing DT nodes to make the
USB available.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
317d13ac63 ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0
Synchronize R-Car Gen3 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
3abd800eb9 ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.0
Synchronize R-Car Gen2 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
b414ab70cd ARM: dts: rmobile: Import R8A77965 M3NULCB DTs
Import R8A77965 M3N ULCB device trees from Linux 5.0 ,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
c6435c317a pinctrl: renesas: Add R8A77965 pin control tables
Add pin control tables for R8A77965 from Linux 5.0 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
933143997b clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
ce417a2f23 ARM: rmobile: Add dedicated R8A77965 SoC support
Add dedicated entry for R8A77965 M3N SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
bdafee778d ARM: rmobile: Enable multi-DTB fit LZO compression
Enable LZO compression of the multi-DTB fitImages, since the U-Boot
with multiple DTs enabled is becoming quite large and the DTs can
be well compressed. The LZO compression saves almost 200 kiB on the
Salvator-X(S) and ULCB targets.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
4fa8375ffe ARM: renesas: Save boot parameters passed in by ATF
The ATF can pass additional information via the first four registers,
x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer
to a device tree with platform information. Save these registers for
future use.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:09 +02:00
Tom Rini
5a451f11c8 First set of u-boot-atmel features and fixes for 2019.07 cycle
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcrEcDAAoJEB6zHgIOrC/I1dgH/3mHQNW8bqiNCJYcoVQdheHb
 e06TqbWHNlOG/NilYybvdeF+LjeCqhX4PzyL/sdcyBf3D/tK4cVvHpZrQyjb2s6K
 5IZSKJ+cZznmq6Hv7b//d30Azhx8bi8luxs60kkj+PF0xI1EyU3JteUqAs4Ooxd7
 z+HdcRFuAaps6sy0+szB3fTw9HTGrhFvQuHasDGb2uahhpwGzu/P0RchIDksOdzH
 3L4EOvgq8MZCiZ3ZtFWMWzQoCjcKf5Fuux41qar8gG/LrkWRfKG+LfWfZtTiTsjf
 vC9bYWmdKtkSLFj1PWgLBfGxev5zwPUbqI2EP4OlagfNs3os5pVFCYV5NZ6ovdE=
 =kMXf
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2019.07-a' of git://git.denx.de/u-boot-atmel

First set of u-boot-atmel features and fixes for 2019.07 cycle
2019-04-09 12:10:40 -04:00
Stefan Roese
a71e2f933b arm: at91: Add gardena-gateway-at91sam support
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
d4c8873f93 arm: at91: at91sam9x5.dtsi: Add watchdog handle
This makes it possible to reference the watchdog DT node via "&watchdog"
from board dts files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
da8a771241 arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds
This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
256c2ff0cc arm: at91: Enable watchdog support
This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09 09:28:50 +03:00
Stefan Roese
ce4d04af99 arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled
This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Stefan Roese
e6a2769360 arm: at91: Makefile: Compile lowlevel_init only when really necessary
Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09 09:28:50 +03:00
Ilko Iliev
d9bd42900c board: pm9g45: Migrate to CONFIG_DM
Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2019-04-09 09:28:50 +03:00
Alexander Dahl
7dee1848d7 ARM: at91: sama5d2: Wrap cpu detection to fix macb driver
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?

That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:

	#ifndef cpu_is_sama5d2
	#define cpu_is_sama5d2() 0
	#endif

That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.

The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:

	=> dhcp
	ethernet@f8008000: PHY present at 1
	ethernet@f8008000: Starting autonegotiation...
	ethernet@f8008000: Autonegotiation complete
	ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
	BOOTP broadcast 1
	BOOTP broadcast 2
	BOOTP broadcast 3
	BOOTP broadcast 4
	BOOTP broadcast 5
	BOOTP broadcast 6
	BOOTP broadcast 7
	BOOTP broadcast 8
	BOOTP broadcast 9
	BOOTP broadcast 10
	BOOTP broadcast 11
	BOOTP broadcast 12
	BOOTP broadcast 13
	BOOTP broadcast 14
	BOOTP broadcast 15
	BOOTP broadcast 16
	BOOTP broadcast 17

	Retry time exceeded; starting again

Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!

The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.

Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-04-09 09:28:50 +03:00
Tom Rini
ffb269ab30 Merge git://git.denx.de/u-boot-riscv
- RISC-V arch support SMP.
- Support Andestech's PLIC and PLMT.
- qemu, fu54e, ae350 boards enable SMP by default.
- Fix CONFIG_DEFAULT_DEVICE_TREE failure.
2019-04-08 22:32:11 -04:00
Jagan Teki
85c3d46322 arm: sunxi: Enable DM_MMC on required SoCs
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html

Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-08 16:35:15 -04:00
Tom Rini
c48b07a9fd - i.MX8QXP-MEK ethernet fix
-----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXKtM/A4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXIuwAJwPGkXMY2V1JWjtWrxV3Ctey8rkvACeML/qP1Ee
 m/WnldHMc++lLZRMVvw=
 =aYD0
 -----END PGP SIGNATURE-----

Merge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-staging

- i.MX8QXP-MEK ethernet fix
2019-04-08 10:11:29 -04:00
Andrejs Cainikovs
e82fa10b3e dts: imx8qxp-mek: Add PHY post reset delay
PHY cannot be detected unless we wait about 150 ms.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-08 15:24:39 +02:00
Stefan Roese
ccd063e981 watchdog: Move watchdog_dev to data section (BSS may not be cleared)
This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2019-04-08 09:21:39 -04:00
Rick Chen
48b90d9db5 riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure
It occurs since commit 27cb7300ff
("Ensure device tree DTS is compiled").

More details can refer to
89c2b5c020
ARM: fix arch/arm/dts/Makefile

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:46:00 +08:00
Rick Chen
a1ce531ab2 riscv: dts: ae350 support SMP
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
dda00ae4ef riscv: ax25: Andes specific cache shall only support in M-mode
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
8848474c5e riscv: ax25: Add platform-specific Kconfig options
Add ax25 RISC-V platform-specific Kconfig options,
to include CPU and timer drivers. Also disable
ATCPIT100 SoC timer and replace by PLMT.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
a1f24875c3 riscv: Add a SYSCON driver for Andestech's PLMT
The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Rick Chen
0d389468e2 riscv: Add a SYSCON driver for Andestech's PLIC
The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Lukas Auer
8ac39e2974 riscv: hang if relocation of secondary harts fails
Print an error message and hang if smp_call_function() returns an error,
indicating that relocation of the secondary harts has failed.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
e043240252 riscv: do not rely on hart ID passed by previous boot stage
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.

Suggested-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
f28ad250e6 riscv: boot images passed to bootm on all harts
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
3dea63c844 riscv: add support for multi-hart systems
On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
1446b26f76 riscv: save hart ID in register tp instead of s0
The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
2503ccc55f riscv: delay initialization of caches and debug UART
Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
f152febb2a riscv: implement IPI platform functions using SBI
The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
34a0626fc3 riscv: import the supervisor binary interface header file
Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-04-08 09:44:25 +08:00
Lukas Auer
fa33f08fd6 riscv: add infrastructure for calling functions on other harts
Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:25 +08:00
Tom Rini
0e62d5b2ab Fixes for 2019.04
- fix bashism for MX8
 	- fix ethernet for MX53
 	- fix docs for i.MX8
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlynLM8PHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et38/QL/Rc3p1pF6Dr9zKzxA0rcMoBo9MzzTrUP6XrN
 8syDBJNo2u93Msv78xHTQMCcfxRR3bkTYiWPEzWphC4Qk2IZIe2sETxu2BqsmWRI
 qzK5+L7oU3qJYqY8mZTUKPhmNxDu7E6yGXI1cWboWSR+/DMTxrUHZU5gjQyaQ/WN
 Diko1+lyaygZyPv0FzBdx7Vv+agQusGXGu4XbRkOXhrE6ytMv2ZjCzUtMYRIUg8H
 057DtJfwgU+zfimUoeuiltAwywh9UGxmlR4kb6rF5VZWX0Xn/XoVbMR6qRQXaFIz
 PzlNu3FEpOmvBQ5W5xySHS0CzbeTisIopJehZbkCc+XaEr80GplN995rGWGIN5av
 nlYS7rWHyIcVxoQNT61JTfVC1blFu6+tiokINWFI8as0fMrEAU4okzT4oBaGxdun
 CVcZDo9ytxKWLqtpD0MIQW4r4kJ27yWe3s4ot+v/+jb+XwkatX2J6oaiKviFFhuc
 BwniIb9lsi3ESIOaQXjpJ+qAw9gWYA==
 =//jr
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imx

Fixes for 2019.04

	- fix bashism for MX8
	- fix ethernet for MX53
	- fix docs for i.MX8
2019-04-05 09:09:56 -04:00
Lukasz Majewski
da60b4301c DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)
After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b79106

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-02 13:44:18 +02:00
Tom Rini
da06f9a185 Merge branch 'master' of git://git.denx.de/u-boot-sh
Minor fixes for the Alt board and PHY use on Gen2.
2019-04-01 23:30:00 -04:00
Marek Vasut
e3b086cf04 ARM: dts: rmobile: Activate I2C7 on Alt
Activate I2C7 on Alt to allow access to the PMIC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-30 08:28:25 +01:00
Philipp Tomsich
a2893baa47 Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"
Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.

This reverts commit 0d968ceb1f.
2019-03-29 09:21:13 +01:00
Tom Rini
d32519ac8a Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various fixes for bugs found by u-boot test.py
2019-03-26 23:19:11 -04:00
Patrick Delaunay
abe66b1b5d Convert CONFIG_ENV_SPI_* to Kconfig
This converts the following to Kconfig:
  CONFIG_ENV_SPI_BUS
  CONFIG_ENV_SPI_CS
  CONFIG_ENV_SPI_MAX_HZ
  CONFIG_ENV_SPI_MODE

Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:36:59 -04:00
Patrick Delaunay
ac31d0d873 exynos: replace CONFIG_ENV_SPI_BASE by CONFIG_SYS_SPI_BASE
Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:35:52 -04:00
Marek Vasut
c49d0ac38a ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator
An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc
pin that the usual toggling of regulator to power the card off and on
is insufficient. When the card is calibrated into UHS SDR104 mode, it
will remain in that mode across the power cycle and subsequent attempt
to communicate with the card will fail.

The test with this card is to insert it into an SDHI slot and perform
"mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail.

Fix this problem by increasing the off-on delay from 0 to 20 mS.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Masahiro Yamada
344db3f330 mips: add missing dtb-y to arch/mips/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

I am going to revert that commit, so device tree must be explicitly
listed in Makefile.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-03-22 12:15:12 -04:00
Masahiro Yamada
680207a1c5 powerpc: fix arch/powerpc/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

I am going to revert that commit, so wrong code must be fixed.

CONFIG_MCR3000 is not defined anywhere. CONFIG_TARGET_MCR3000 is the
correct one.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-03-22 12:15:10 -04:00
Masahiro Yamada
89c2b5c020 ARM: fix arch/arm/dts/Makefile
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

As a result, a lot of wrong code have been merged unnoticed.

I am going to revert that commit, and lots of hidden issues have
come to light:

[1] Typos

  armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts

  use the extension ".dts" instead of ".dtb"

[2] DTB is associated to undefined CONFIG option

  For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
  associates its device tree to CONFIG_MX6SL, which is undefined.

[3] Lots of entries are missing

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
[trini: add imx6ul pico dtbs]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-03-22 12:15:09 -04:00
Alexander Graf
ef331e3685 armv8: Disable exception vectors in SPL by default
Commit 1416e2d225 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.

Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.

So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-22 12:15:03 -04:00
Keerthy
6dad56d733 arm: lib: bootm: Push the Starting kernel print to the end
Push the Starting kernel print to the end just before the
dm_remove_devices call.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-22 08:35:50 -04:00
Tom Rini
a00d15757d Merge git://git.denx.de/u-boot-marvell
- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)
2019-03-19 19:58:48 -04:00
Tom Rini
810ae23fbc Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2019-03-19 07:13:23 -04:00
Chris Packham
599f7aa541 ARM: kirkwood: disable dcache for Kirkwood boards
Prior to commit 93b283d49f ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.

Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
825dd50f59 ARM: mvebu: use correct name for pcie controller
When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.

Reported-by: Влад Мао <vlaomao@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
5860532264 ARM: kirkwood: add spi0 alias for dreamplug
The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.

Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Ley Foon Tan
ff0005b56a ARM: dts: socfpga: Add missing altr,sysmgr-syscon for EMAC
Syscon register is required in dts to select correct
PHY interface.

Fix error below:

Net:   Failed to get syscon: -2

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-03-16 13:30:03 +01:00
Tom Rini
8303467e80 Merge git://git.denx.de/u-boot-fsl-qoriq
- DPAA2 fixes and DDR errata workaround for LS1021A
2019-03-15 11:58:17 -04:00
Alison Wang
158097052a armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Tom Rini
9659eb46af Merge branch 'master' of git://git.denx.de/u-boot-samsung 2019-03-14 11:37:11 -04:00
Adam Ford
8d0370905c arm: dts: imx6qdl-u-boot: Enable spba-bus@2000000 simple bus
spba-bus has a few nodes under it including the UART1 and
some ESPI buses.  In order to use them in SPL, the
u-boot,dm-spl flag needs to be added to the spba-bus@2000000
container.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
75cd09cb18 imx8qxp: Fix the reported CPU frequency
Currently the CPU frequency is incorrectly reported:

CPU:   NXP i.MX8QXP RevB A35 at 147228 MHz

Fix this problem by using a direct call to the SCU firmware to
retrieve the Cortex A35 CPU frequency.

With this change applied the CPU frequency is displayed correctly:

CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz

Tested-by: Marcelo Macedo <marcelo.macedo@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
2019-03-13 09:14:35 +01:00
Fabio Estevam
737d8bd820 pico-imx6ul: Convert to DM MMC
Select CONFIG_DM_MMC=y in order to support MMC driver model.

This allows the MMC board related code to be removed.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2019-03-13 09:14:35 +01:00
Fabio Estevam
e5c2244fc8 pico-imx6ul: Import dts files from kernel
Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2019-03-13 09:14:35 +01:00
Tom Rini
6a08213d52 Merge git://git.denx.de/u-boot-x86
- ACPI changes and fixes to Intel Tangier/Edison
- i8254 beeper fixes
2019-03-11 11:24:20 -04:00
Bin Meng
3592965aff x86: crownbay: Enable the beeper sound driver
Use the i8254 sound driver to support creating simple beeps.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
8edaf34cfe x86: coreboot: Add the missing pc speaker node in the device tree
This is currently missing and without it the i8254 beeper driver
won't work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
9b2c8c3066 x86: Add a dtsi file for the pc speaker
The pc speaker driven by the i8254 is generic enough to deserve
a single dtsi file to be included by boards that use it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
7d0a53a40c x86: Make sure i8254 is setup correctly before generating beeps
The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Krzysztof Kozlowski
be26c4af3a arm: dts: exynos: Adjust whitespace around status property
Just add spaces around '=' sign for clarity.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:36 +09:00
Krzysztof Kozlowski
ae781d56fe arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 family
Add startup time to LDO regulators of S2MPS11 PMIC on Odroid XU3/XU4/HC1
family of boards to be sure the voltage is proper before relying on the
regulator.

The datasheet for all the S2MPS1x family is inconsistent here and does
not specify unambiguously the value of ramp delay for LDO.  It mentions
30 mV/us in one timing diagram but then omits it completely in LDO
regulator characteristics table (it is specified for bucks).

However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12
mV/us or 24 mV/us.

Without the ramp delay value the consumers do not wait for voltage
settle after changing it.  Although the proper value of ramp delay for
LDOs is unknown, it seems safer to use at least some value from
reference kernel than to leave it unset.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Krzysztof Kozlowski
b5d3faa9f9 arm: dts: exynos: Add supply for ADC block to Odroid XU3 family
The ADC block requires VDD supply to be on so provide one.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Tom Rini
19c8c9c103 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
2019-03-10 10:16:07 -04:00
Andy Shevchenko
d9b59fc9ae x86: edison: Add the rest of UARTs present on board
Intel Edison has three UART ports, i.e.
 port 0 - Bluetooth
 port 1 - auxiliary, available for general purpose use
 port 2 - debugging, usually console output is here

Enable all of them for future use.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
ab83e5c1a2 x86: edison: Use proper number of serial interface
The console is actually serial #2. When we would like to enable other ports,
this would be not okay to mess up with the ordering.

Thus, fix the number of default console interface to be 2.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
edf18a83f8 x86: acpi: Not every platform has serial console a first device
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad78e ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
c652dd1557 x86: acpi: Add DMA descriptors for I2C1 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Note, I2C6, which is available to user, has no DMA request lines connected.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
1d2825aa30 x86: acpi: Add DMA descriptors for SPI5 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Marek Vasut
7544ad0303 ARM: socfpga: Disable D cache in SPL
The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 17:59:13 +01:00
Dinh Nguyen
532a54e652 ARM: socfpga: fix data and tag latency values for pl310 cache controller
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-03-09 17:59:13 +01:00
Eugeniu Rosca
3a4511ce4a ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N
v2019.01 commit cbff9f80ce ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.

Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
 - f529bc551b ("ARM: dts: rmobile: Extract USB nodes on M3N")
 - 830b94f768 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")

Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
 - not needed if no U-boot-specific changes are needed in those nodes.
 - potentially dangerous/error-prone, since the duplicated properties
   override the properties originally defined in <soc>.dtsi. One
   possible consequence is that <soc>.dtsi is getting an update from
   Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
   the obsolete property values from <soc>-u-boot.dtsi will take
   precedence masking some of the <soc>.dtsi updates, potentially
   leading to all kind of obscure issues.

Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).

What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.

$> dtdiff before-r8a77965-salvator-x-u-boot.dtb \
           after-r8a77965-salvator-x-u-boot.dtb
 --- /dev/fd/63  2019-03-09 12:57:40.877963983 +0100
 +++ /dev/fd/62  2019-03-09 12:57:40.877963983 +0100
 @@ -1471,7 +1471,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x51 0xc 0x1>;
        clocks = <0x6 0x1 0x13a>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa5 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x4d>;
 @@ -1492,7 +1492,7 @@

      sd@ee120000 {
        clocks = <0x6 0x1 0x139>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa6 0x4>;
        max-frequency = <0xbebc200>;
        power-domains = <0x1 0x20>;
 @@ -1504,7 +1504,7 @@
      sd@ee140000 {
        bus-width = <0x8>;
        clocks = <0x6 0x1 0x138>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        fixed-emmc-driver-type = <0x1>;
        interrupts = <0x0 0xa7 0x4>;
        max-frequency = <0xbebc200>;
 @@ -1526,7 +1526,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x5a 0xf 0x1>;
        clocks = <0x6 0x1 0x137>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa8 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x56>;
 @@ -1868,14 +1868,14 @@

      usb-phy@ee0a0200 {
        #phy-cells = <0x0>;
 -      clocks = <0x6 0x1 0x2be>;
 +      clocks = <0x6 0x1 0x2bf>;
        compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy";
        phandle = <0x47>;
        pinctrl-0 = <0x4c>;
        pinctrl-names = "default";
        power-domains = <0x1 0x20>;
        reg = <0x0 0xee0a0200 0x0 0x700>;
 -      resets = <0x6 0x2be>;
 +      resets = <0x6 0x2bf>;
        status = "okay";
      };

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-03-09 17:57:04 +01:00
Marek Vasut
fc3ed156f9 ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPI
U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until
we can do better using the new SPI NOR framework.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-09 17:57:04 +01:00
Tom Rini
85887300ae Merge git://git.denx.de/u-boot-fsl-qoriq
- Enable DHCP as boot-source in distro boot for NXP layerscape
  platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet
2019-03-04 13:05:53 -05:00
Laurentiu Tudor
7122f79141 armv8: fsl-layerscape: avoid DT fixup warning
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:

WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.

Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:14 +05:30
Laurentiu Tudor
e82d9ee73a armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:09 +05:30
Rajesh Bhagat
32413125b3 configs: fsl: move DDR specific defines to Kconfig
Moves below DDR specific defines to Kconfig:

CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 20:56:01 +05:30
Heinrich Schuchardt
70eb82539b powerpc: enabled building with CONFIG_DM=y
Moving to the driver model requires CONFIG_DM to be enabled. Currently
several boards like kmeter1_defconfig produce a build error when CONFIG_DM
is enabled:

In file included from include/common.h:35,
                 from ./arch/powerpc/include/asm/fsl_lbc.h:10,
                 from include/mpc83xx.h:10,
                 from ./arch/powerpc/include/asm/ppc.h:27,
                 from ./arch/powerpc/include/asm/u-boot.h:18,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/dm/device.h:13,
                 from include/linux/mtd/mtd.h:26,
                 from drivers/mtd/mtdconcat.c:25:
include/image.h: In function ‘image_check_target_arch’:
include/image.h:846:3: error: #error "please define IH_ARCH_DEFAULT in
                       your arch asm/u-boot.h"
 # error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h"
   ^~~~~
include/image.h:848:31: error: ‘IH_ARCH_DEFAULT’ undeclared (first use in
                        this function); did you mean ‘IH_ARCH_COUNT’?
  return image_check_arch(hdr, IH_ARCH_DEFAULT);

The error can be avoided by moving the definition of IH_ARCH_DEFAULT before

     #include <asm/ppc.h>

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-02 18:11:20 +05:30
Tom Rini
cfba74d0be Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA cache/gpio fixes
2019-02-28 18:57:32 -05:00
Tom Rini
35b05146f6 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28 18:57:17 -05:00
Tom Rini
da206916a1 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Various Bananapi fixes
2019-02-28 14:22:50 -05:00
Marek Vasut
86dc480d73 ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2019-02-28 14:21:46 -05:00
Anup Patel
98a66ffa3a riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
because bootm will update initrd location in DTB only if
CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
this option then bootm assumes DTB already has initrd details
which is not the case most of the time.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27 09:12:34 +08:00
Anup Patel
3fda0262c3 riscv: Add SiFive FU540 board support
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
b630d57d0a clk: Add fixed-factor clock driver
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 09:12:33 +08:00
Anup Patel
26f4fd1cb4 riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.

To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
1fa625b8e4 riscv: Add place-holder asm/arch/clk.h for driver compilation
Some of the drivers (such as Cadence MACB ethernet driver) expect
asm/arch/clk.h to be provided by arch support so we add place-holder
asm/arch-generic/clk.h for RISC-V generic CPU.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27 09:12:33 +08:00
Anup Patel
70b8562dcf riscv: Add asm/dma-mapping.h for DMA mappings
This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27 09:12:33 +08:00
Anup Patel
fdff1f96a6 riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
7c8d210b91 riscv: Enable create symlink using kconfig
We select CREATE_ARCH_SYMLINK for RISC-V so that we can have
include/asm/arch linked to include/asm/arch-xyz.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Marek Vasut
30b62ca086 ARM: rmobile: Imply SoC per board
Imply all SoCs supported by a given board. This allows building single
U-Boot binary for boards which can have multiple SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
669367f6a4 ARM: rmobile: Imply pinctrl drivers per SoC
Imply preferred pin control driver per SoC, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
46467ceaf4 ARM: rmobile: Imply clock drivers per SoC
Imply preferred clock driver per SoC, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
4a9743f73c ARM: socfpga: Clear PL310 early in SPL
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.

The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.

This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.

The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25 16:07:36 +01:00
Marek Vasut
2c0b300bc3 ARM: socfpga: Configure PL310 latencies
Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2019-02-25 16:07:36 +01:00
Marek Vasut
b275c9aba6 ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
2019-02-25 16:07:36 +01:00
Tom Rini
888f9aa5ca Merge branch 'master' of git://git.denx.de/u-boot-tegra 2019-02-20 12:28:57 -05:00
Tom Rini
0c41e59a37 Merge git://git.denx.de/u-boot-x86
- Add support for sound.

Albeit the big changeset, changes are pretty limited to x86 only and a
few new sound drivers used by x86 so I think it would be good to have
this in the next release.
2019-02-20 12:28:40 -05:00
Tom Rini
176b32cd4f Merge git://git.denx.de/u-boot-fsl-qoriq
- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
2019-02-20 12:26:05 -05:00
Tristan Bastian
8105816cbb ARM: tegra: enable ums on nyan boards
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef.
But the nyan devices never received that functionality.

Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Tristan Bastian
74a7d9af3f nyan-big: change spi delay
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button.
With this patch keyboard is working by only pressing [power] button.

Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Simon Glass
e2c901c99e x86: Add sound support for samus
Enable sound on samus using the broadwell I2S and an RT5677 audio codec.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-20 15:27:11 +08:00
Simon Glass
3f3411ebf8 x86: broadwell: Add support for serial I/O devices
Add support for initing the I2C device and ADSP on broadwell. These are
needed for sound to work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
c692f82240 x86: broadwell: Don't bother probing the PCH for pinctrl
At present the pinctrl probes the PCH but since it only uses it to obtain
a PCI address, this is no necessary. Avoiding this fixes one of the two
co-dependent loops in broadwell.

This driver really should be a proper pinctrl driver, but for now it
remains a syscon device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
23e8bd7e49 x86: broadwell: Add support for the ADSP
The Application Digital Signal Processor is used for sound processing with
broadwell. Add a driver to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
79a5be820d sound: x86: Add beeping support in i8254
Adjust the code to allow beeping at different frequencies, using a
calculated value for timer 2.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
6744c0d652 sound: x86: link: Add sound support
Add sound support for link, using the HDA codec implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
ecc7973d1c sandbox: sound: Silence sound for testing
When testing the sound system we don't need the hear the beeps. The
testing works by checking the data that would be emitted. Add a
device-tree property to silence the sound, and enable it for testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
2850266965 sound: Add uclass operations for beeping
Some audio codecs such as Intel HDA do not need to use digital data to
play sounds, but instead have a way to emit beeps. Add this interface as
an option. If the beep interface is not supported, then the sound uclass
falls back to the I2S interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
67b0cda76a x86: ivybridge: Add a way to get the HDA config setting
Add a way check to whether HD audio is enabled. Use ioctl() to avoid
adding too many unusual operations to PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
b45c833c71 sandbox: pch: Add a test for the PCH uclass
This uclass currently has no tests. Add a sandbox driver and some simple
tests to provide basic coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Use "sandbox,pch" for the compatible string, for consistency]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:26:36 +08:00
Simon Glass
c882163b09 x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:30 +08:00
Simon Glass
3a44bfdf08 x86: Adjust I/O macros to work on 64-bit machines
At present these macros give warnings on 64-bit machines and do not
correctly do 32-bit accesses. Update them to use linux types.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:29 +08:00
Simon Glass
c6d84a30fe sandbox: Add a note about the growing state_info struct
This struct is getting larger and in some cases is being used for things
which would be better put into a driver. For example hwspinlock is not
used outside of sandbox_hwspinlock.c.

Add a note to encourage people to put things elsewhere.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:29 +08:00
Derald D. Woods
36a75344d7 ARM: omap3: evm: Update DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties
- Enable SPL_OF_CONTROL

This commit is based on the following series:

https://patchwork.ozlabs.org/project/uboot/list/?series=92472
https://patchwork.ozlabs.org/project/uboot/list/?series=92462

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-19 16:58:24 -05:00
Tom Rini
e0cc7df9fd omap3_beagle: Update for DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties.
- Remove a few SPL features to free up more SRAM space.
- Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to
  worry about X-Loader at this point anymore.
- A few related updates to SPL options as part of switching to DM SPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19 16:58:23 -05:00
Adam Ford
0cd9465c0b ARM: omap3_logic: Enable SPL booting device tree
With the generic omap3-u-boot.dtsi file available, this patch
increased the memory of the various incarnations of the omap3_logic
board, and points their respective u-boot.dtsi files to the newly
created generic one, and removes the PLATDATA from the board file.

These are all done at once because the're all utilizing the same
omap3logic.c board file.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-19 16:58:23 -05:00
Adam Ford
ed59a76db0 ARM: DTS: omap3-u-boot.dtsi
Create generic omap3-u-boot.dtsi file that omap3 based boards
can include to generate device tree in SPL for booting MLO.

Credit should go to Tom Rini.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19 16:58:23 -05:00
Hannes Schmelzer
eaba7df704 board/BuR/brxre1: convert do DM
This commit converts the brxre1 board to DM,
for this we have todo following things:

- add a devicetree-file for this board
- drop all obsolete settings from board header-file
- use dm_i2c_xxx calls for read/write to the resetcontroller
- request gpios before operate them

Serues-cc: trini@konsulko.com
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-19 08:55:43 -05:00
Peng Ma
f11e492aea armv8: ls1043a: move SCSI_AHCI and SCSI to arm/Kconfig
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface
support.
this changed is to fixed the ls1043ardb compile warning as fallows:

===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the
v2019.07 release. Failure to update by the deadline may
result in board removal.See doc/driver-model/MIGRATION.txt
for more info.
====================================================

Signed-off-by: Peng Ma <peng.ma@nxp.com>
[PK: reword the patch subject]
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
5c08d96f3a armv8: layerscape: move CONFIG_LAYERSCAPE to Kconfig
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
bbf5b25282 armv8: layerscape: move TZASC and TZPC configs to Kconfig
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30