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riscv: save hart ID in register tp instead of s0

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The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Lukas Auer 2019-03-17 19:28:36 +01:00 committed by Andes
parent 2503ccc55f
commit 1446b26f76
1 changed files with 2 additions and 2 deletions
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4
arch/riscv/cpu/start.S
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@ -36,7 +36,7 @@
.globl _start
_start:
/* save hart id and dtb pointer */
mv s0, a0
mv tp, a0
mv s1, a1
la t0, trap_entry
@ -64,7 +64,7 @@ call_board_init_f_0:
jal board_init_f_init_reserve
/* save the boot hart id to global_data */
SREG s0, GD_BOOT_HART(gp)
SREG tp, GD_BOOT_HART(gp)
/* Enable cache */
jal icache_enable