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https://github.com/AsahiLinux/u-boot
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x86: broadwell: Add support for the ADSP
The Application Digital Signal Processor is used for sound processing with broadwell. Add a driver to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
9d4d5db64d
commit
23e8bd7e49
5 changed files with 208 additions and 0 deletions
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@ -2,6 +2,7 @@
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#
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# Copyright (c) 2016 Google, Inc
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obj-y += adsp.o
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obj-y += cpu.o
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obj-y += iobp.o
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obj-y += lpc.o
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156
arch/x86/cpu/broadwell/adsp.c
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156
arch/x86/cpu/broadwell/adsp.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Application Digital Signal Processor
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*
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot file of the same name
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*/
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#define LOG_CATEGORY UCLASS_SYSCON
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/cpu.h>
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#include <asm/intel_regs.h>
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#include <asm/arch/adsp.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/rcb.h>
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enum pci_type_t {
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LYNX_POINT,
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WILDCAT_POINT,
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};
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struct broadwell_adsp_priv {
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bool adsp_d3_pg_enable;
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bool adsp_sram_pg_enable;
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bool sio_acpi_mode;
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};
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static int broadwell_adsp_probe(struct udevice *dev)
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{
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struct broadwell_adsp_priv *priv = dev_get_priv(dev);
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enum pci_type_t type;
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u32 bar0, bar1;
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u32 tmp32;
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/* Find BAR0 and BAR1 */
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bar0 = dm_pci_read_bar32(dev, 0);
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if (!bar0)
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return -EINVAL;
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bar1 = dm_pci_read_bar32(dev, 1);
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if (!bar1)
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return -EINVAL;
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/*
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* Set LTR value in DSP shim LTR control register to 3ms
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* SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
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*/
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type = dev_get_driver_data(dev);
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tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
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writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32);
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/* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
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dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
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/* Program ADSP IOBP VDLDAT1 to 0x040100 */
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pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
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/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
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dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32);
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if (type == WILDCAT_POINT) {
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if (priv->adsp_d3_pg_enable) {
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tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
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if (priv->adsp_sram_pg_enable)
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tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
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else
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tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
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} else {
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tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
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}
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} else {
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if (priv->adsp_d3_pg_enable) {
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tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
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if (priv->adsp_sram_pg_enable)
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tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
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else
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tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
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} else {
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tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
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}
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}
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dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
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/* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
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setbits_le32(RCB_REG(0x3350), 1 << 10);
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/* Set DSP IOBP PMCTL 0x1e0=0x3f */
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pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
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if (priv->sio_acpi_mode) {
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/* Configure for ACPI mode */
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log_info("ADSP: Enable ACPI Mode IRQ3\n");
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/* Set interrupt de-assert/assert opcode override to IRQ3 */
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pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
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/* Enable IRQ3 in RCBA */
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setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
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/* Set ACPI Interrupt Enable Bit */
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pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
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ADSP_PCICFGCTL_ACPIIE);
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/* Put ADSP in D3hot */
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clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
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} else {
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log_info("ADSP: Enable PCI Mode IRQ23\n");
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/* Configure for PCI mode */
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dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
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/* Clear ACPI Interrupt Enable Bit */
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pch_iobp_update(ADSP_IOBP_PCICFGCTL,
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~(ADSP_PCICFGCTL_SPCBAD |
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ADSP_PCICFGCTL_ACPIIE), 0);
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}
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return 0;
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}
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static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev)
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{
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struct broadwell_adsp_priv *priv = dev_get_priv(dev);
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priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable");
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priv->adsp_sram_pg_enable = dev_read_bool(dev,
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"intel,adsp-sram-pg-enable");
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priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode");
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return 0;
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}
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static const struct udevice_id broadwell_adsp_ids[] = {
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{ .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT },
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{ }
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};
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U_BOOT_DRIVER(broadwell_adsp_drv) = {
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.name = "adsp",
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.id = UCLASS_SYSCON,
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.ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata,
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.of_match = broadwell_adsp_ids,
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.bind = dm_scan_fdt_dev,
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.probe = broadwell_adsp_probe,
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};
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static struct pci_device_id broadwell_adsp_supported[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) },
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{ },
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};
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U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported);
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46
arch/x86/include/asm/arch-broadwell/adsp.h
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46
arch/x86/include/asm/arch-broadwell/adsp.h
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Application Digital Signal Processor
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*
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot file of the same name
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*/
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#ifndef __ASM_ARCH_BROADWELL_ADSP_H
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#define __ASM_ARCH_BROADWELL_ADSP_H
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#define ADSP_PCI_IRQ 23
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#define ADSP_ACPI_IRQ 3
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#define ADSP_ACPI_IRQEN BIT(3)
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#define ADSP_SHIM_BASE_LPT 0xe7000
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#define ADSP_SHIM_BASE_WPT 0xfb000
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#define ADSP_SHIM_LTRC 0xe0
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#define ADSP_SHIM_LTRC_VALUE 0x3003
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#define ADSP_SHIM_IMC 0x28
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#define ADSP_SHIM_IPCD 0x40
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#define ADSP_PCI_VDRTCTL0 0xa0
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#define ADSP_VDRTCTL0_D3PGD_LPT BIT(1)
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#define ADSP_VDRTCTL0_D3PGD_WPT BIT(0)
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#define ADSP_VDRTCTL0_D3SRAMPGD_LPT BIT(2)
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#define ADSP_VDRTCTL0_D3SRAMPGD_WPT BIT(1)
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#define ADSP_PCI_VDRTCTL1 0xa4
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#define ADSP_PCI_VDRTCTL2 0xa8
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#define ADSP_VDRTCTL2_VALUE 0x00000fff
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#define ADSP_IOBP_VDLDAT1 0xd7000624
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#define ADSP_VDLDAT1_VALUE 0x00040100
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#define ADSP_IOBP_VDLDAT2 0xd7000628
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#define ADSP_IOBP_ACPI_IRQ3 0xd9d8
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#define ADSP_IOBP_ACPI_IRQ3I 0xd8d9
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#define ADSP_IOBP_ACPI_IRQ4 0xdbda
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#define ADSP_IOBP_PMCTL 0xd70001e0
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#define ADSP_PMCTL_VALUE 0x3f
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#define ADSP_IOBP_PCICFGCTL 0xd7000500
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#define ADSP_PCICFGCTL_PCICD BIT(0)
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#define ADSP_PCICFGCTL_ACPIIE BIT(1)
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#define ADSP_PCICFGCTL_SPCBAD BIT(7)
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#endif /* __ASM_ARCH_BROADWELL_ADSP_H */
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#define SATA_DTLE_EDGE_SHIFT 16
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/* Power Management */
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#define PCH_PCS 0x84
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#define PCH_PCS_PS_D3HOT 3
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#define GEN_PMCON_1 0xa0
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#define SMI_LOCK (1 << 4)
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#define GEN_PMCON_2 0xa2
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#ifndef __asm_arch_rcba_h
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#define __asm_arch_rcba_h
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#define ACPIIRQEN 0x31e0 /* 32bit */
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#define PMSYNC_CONFIG 0x33c4 /* 32bit */
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#define PMSYNC_CONFIG2 0x33cc /* 32bit */
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