It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.
The underlying drivers should be responsible for the cache operation.
Remove these codes completely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.
Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.
Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings
Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds support for RGMII protocol
NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch add support of LS1088AQDS platform.
The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: York Sun <york.sun@nxp.com>
WIP: disable NAND for LS1088ARDB
According current code base, CONFIG_LS1012A should be
CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
wrongly called to disable all dwc3 USB nodes on LS1012A, which
cause Linux USB function stop working at all.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
kASLR support in kernel requires a random number to be passed via
chosen/kaslr-seed propert. sec_firmware generates this random seed
which can then be passed in the device tree node.
sec_firmware reserves JR3 for it's own usage. Node for JR3 is
removed from device-tree.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct
function call into drivers/mtd/nand/fsmc_nand.c. However, this
function is not guarded by CONFIG_NAND_FSMC, which results to a build
failure if CONFIG_NAND_FSMC is disabled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.
Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
For DEVICE_NON_SHARED the newly assigned value of attr
is overwritten due to a missing break.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
It does not make sense first to dereference c and then
to check if it is NULL.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.
As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig. Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
decision for each stage and under control of $(SPL_TPL_)TIMER
instead of having the two-level configuration with TIMER and
$(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway. By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.
Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.
Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_CMD_PCI
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
There is a need to include psu_init also in mini u-boot configuration
that's why handle psu_init via Kconfig property.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
For some mini platforms there could be a need to include psu_init.
That's why move it to board file instead of spl only file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes ifdef around mmio read and write rotuines
and make them a single routine by checking the current el.
This patch helps to remove ifdef around invoke_smc as well.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
TCM on ZynqMP needs to be intialized in a sequence
and this patch provides a global routine to perform
this as per requirement.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch provides an option to include OCM and TCM memory
into MMU table with corresponding memory attributes.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed.
The definitions in <image.h> are used.
According to this modification, the comparison between os arch and cpu
arch is done in C programming instead of ASM programming.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.
This change is also coherent with the structure in kernel.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
As mx6sabreauto supports SPL now, all variants can boot using the same
defconfig.
This patch:
- Removes non-SPL targets.
- Renames target to mx6sabreauto_defconfig.
- Renames folder and board files to mx6sabreauto.
- Updates MAINTAINERS, Makefile and Kconfig accordingly.
- Removes .cfg files.
- Adds a README with instructions to build and flash SPL and u-boot.img.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Add support for mx6q, mx6dl and mx6qp sabreauto boards in SPL.
Retrieved the mx6q DCD table from:
board/freescale/mx6qsabreauto/imximage.cfg
Retrieved the mx6dl DCD table from:
board/freescale/mx6qsabreauto/mx6dl.cfg
Retrieved the mx6qp DCD table from:
board/freescale/mx6qsabreauto/mx6qp.cfg
Flashed SPL and u-boot.img to an SD card and could successfully boot it
on mx6q, mx6qp and mx6dl sabreauto boards.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Currently the following build error is seen when a board using MMC SPL
is built and the MXS nand driver is also selected:
arch/arm/cpu/armv7/built-in.o: In function `arch_cpu_init':
arch/arm/cpu/armv7/mx6/soc.c:432: undefined reference to 'mxs_dma_init'
On mx6 the only user of mxs_dma_init() is the mxs nand driver, so
move it there.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
i.MX 6UL and 6ULL have different boot device capabilities and
use therefor use a different boot device selection table than
other i.MX 6 devices. Particularly, the value which has been
used so far (b0001) is assigned to QSPI boot for these two
devices.
There is no common reserved value for all i.MX 6devices. Use
b0010 for i.MX 6UL and 6ULL via compile time ifdef.
Reported-by: Joël Esponde <joel.esponde@honeywell.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Joël Esponde <joel.esponde@honeywell.com>
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
The 'mode' parameter is actually a flag to determine whether to display
a list of devices found during the scan. Rename it to reflect this, add a
function comment and adjust callers to use a boolean.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present CONFIG_CMD_SATA enables the 'sata' command which also brings
in SATA support. Some boards may wish to enable SATA without the command.
Add a separate CONFIG to permit this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This actually works on snapdragon.. not sure why we weren't using it.
Fixes reboot/poweroff when using UEFI.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define routines of mmio write and read functionalities
for zynqmp platform.
Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.
Also make invoke_smc as global so that it can be reused in
multile places where ever possible.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Silicon v1 didn't support SD boot mode with level shifter.
Because system can't boot any error message is not shown
that's why comment is just a record if someone tries to debug it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The boot_device argument to spl_boot_mode was massively added without
actually modifying the existing functions.
This commit actually makes use of the handed value, which is the same.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When enabling both SDHCI controllers, spl_mmc.c would actually choose
device sdhci0 even if booted from sdhci1 (boot_device). This is because
spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in
order to return index 1 instead of 0.
The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c
So the key to properly enabling both controllers as boot sources is
defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's
include/configs/*.h.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
It turns out this change was not intended to be merged and as such,
revert it.
This reverts commit cdde7de036.
Reported-by: Manfred Schlaegl <manfred.schlaegl@ginzinger.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Using u-boot-2017.05 on i.MX6UL we ran into following problem:
Initially U-Boot could be started normally.
If we added one random command in configuration, the newly generated
image hung at startup (last output was DRAM: 256 MiB).
We tracked this down to a data abort within relocation (relocated_code).
relocated_code in arch/arm/lib/relocate.S copies 8 bytes per loop
iteration until the source pointer is equal to __image_copy_end.
In a good case __image_copy_end was aligned to 8 bytes, so the loop
stopped as suggested, but in an errornous case __image_copy_end was
not aligned to 8 bytes, so the loop ran out of bounds and caused a
data abort exception.
This patches solves the issue by aligning __image_copy_end to 8 byte
using the linker script related to arm.
I don't know if it's the correct way to solve this, so some review would
be very appreciated.
Currently we set the entry address in the psci_cpu_on function.
However R40 has a different register for this. This resulted in
an #ifdef / #else block in psci_cpu_on, which we avoided having
in the first place.
Move this part into a separate function, defined differently for
the R40 as opposed to the other single cluster platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This option allows skipping the call to lowlevel() while still performing
CP15 init. Support this on ARM720T so it can be used with Tegra.
Signed-off-by: Simon Glass <sjg@chromium.org>
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Mark explicitly bss sections to not be loaded at
run time.
The similar patch was done in past by:
"Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections"
(sha1: 64134f0112)
The problem is related to latest toolchain added to Xilinx
v2017.1 design tools where jtag loader is trying to access
ununitialized memory.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for calling poweroff in case of psci is wired.
Based on the same solution as is used for reset.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Move all logic in to fwcall.c as other ARMs implement poweroff
via PMIC]
Signed-off-by: Tom Rini <trini@konsulko.com>
These declarations should not be in common. Remove those that are not
needed and move the others to an arch-specific location.
Signed-off-by: Simon Glass <sjg@chromium.org>
The declarations should not be in common.h. Move them to the arch-specific
headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than have a long and if check in the Makefile, mark the default
lowlevel_init function as weak (as we do on armv8) so that SoCs can
override it if needed, and it will still be discarded if unused.
Provide a weak s_init as well to allow for this to link and be
discarded.
Signed-off-by: Tom Rini <trini@konsulko.com>
Loading PPA in SPL puts the rest of U-Boot (including RAM version
loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded,
PSCI is available.
Signed-off-by: York Sun <york.sun@nxp.com>
When U-Boot boots from EL2, skip some lowlevel init code requiring
EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These
initialization tasks are carried out before U-Boot runs. This applies
to the RAM version image used for SPL boot if PPA is loaded first.
Signed-off-by: York Sun <york.sun@nxp.com>
Add CONFIG_NAND_BOOT config flag to organise
NAND_BOOT specific code in config flag like
-nand-boot specfic errata errata_rcw_src()
-CONFIG_SYS_NAND_U_BOOT_DST,etc
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
These two functions have an of_ prefix which conflicts with naming used
in of_addr. Rename them:
fdt_read_number
fdt_support_bus_default_count_cells
Signed-off-by: Simon Glass <sjg@chromium.org>
Introduce the imx_set_perclk() function to make it possible to set the
PER clocks.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
imx_get_perclk() used the AHB clock as the clock source for all PER
clocks, but the USB PLL output can also be a PER clock source if the
corresponding PER CLK MUX bit is set in CCM.MCR.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Add the initial support for pico-imx7d board based on Wig Cheng's
source code.
Add support for eMMC, USB gadget, I2C, PMIC and Ethernet.
For more information about this board, please visit:
http://www.technexion.org/products/pico/pico-som/pico-imx7-emmc
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SPL FIT is able to pick the suitable fdt file for u-boot,
so add that function through board_fit_config_name_match.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The SMPEN bit is located in the cpuectlr_el1 register and not the
cpuactlr_el1 register. Adjust the comment accordingly and also fix
a spelling error.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
CC: York Sun <york.sun@nxp.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Cortex-M archs support option memory protection unit (MPU). MPU is used
to set the memory types, attributes, access permissions for different regions,
cache policies of the device.
e.g. using MPU it is possible to configure memory region as device memory
or strongly ordered, memory attributes like execute never, cache policies
like write-back or write-through.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Data cache memory needs to be disabled before handing over control to
linux kernel. This patch populates the cleanup_before_linux stub.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Add functionality to flush & invalidate all the dcache using the
prototype declared in common header file.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add dummy functions for the not-enabled case]
Signed-off-by: Tom Rini <trini@konsulko.com>
At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.
Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
With 3f66149d9f we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup. On ARM however we largely relied on this call. Rather
than introduce a large number of changes to ft_cpu_fixup /
ft_board_fixup we recognize that this is a common enough call that we
should be doing it in a central location. Do it early enough that we
can do any further updates in ft_cpu_fixup / ft_board_fixup.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS)
Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX)
Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX)
Cc: Simon Glass <sjg@chromium.org>
Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Fixes: 3f66149d9f ("Remove extra fdt_fixup_ethernet() call")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 /
CONFIG_MX53 being in Kconfig. Do so now.
Signed-off-by: Tom Rini <trini@konsulko.com>
PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:
[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream
ID and corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for secure
boto header.
- Error messages during SPL boot are limited to error code numbers
instead of strings to reduce the size of SPL image.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The header address of PPA defined in Kconfig.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB
and convert it to Kconfig.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.
Signed-off-by: Simon Glass <sjg@chromium.org>
Logic PD has an i.MX6Q system on module (SOM) with a development kit. The
SOM has a built-in microSD socket, DDR and NAND flash. The development kit
has an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
This have been verified to boot the i.MX6Q version over either SD
on the development kit or NAND built into the SOM. Items in the dtsi file
are specific to the SOM itself. Items in the dts file are in the baseboard.
Future versions of the SOM will come out supporting the same basebord and
potentially future base boards will come out supporting the same SOM.
Signed-off-by: Adam Ford <aford173@gmail.com>
The num/denom is a float value, but in the calculation it is convert
to integer 0, and wrong result.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
spl_mmc.c calls mmc_initialize(). This symbol is provided in
drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled.
The sunxi Kconfig case is an oddball because it redefines
SPL_MMC_SUPPORT.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
[trini: Update arch/arm/cpu/armv8/zynqmp/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
With d53ecad92f some unused interrupt related code was removed.
However all of these options are currently unused. Rather than migrate
some of these options to Kconfig we just remove the code in question.
The only related code changes here are that in some cases we use
CONFIG_STACKSIZE in non-IRQ related context. In these cases we rename
and move the value local to the code in question.
Fixes: d53ecad92f ("Merge branch 'master' of git://git.denx.de/u-boot-sunxi")
Signed-off-by: Tom Rini <trini@konsulko.com>
By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Some Freescale boards used an extra version of the constant to hold the
Generic Timer frequency. This can easily be covered by the now unified
COUNTER_FREQUENCY constant, so remove this extra variable from those
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided
instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup.
Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.
So Avoid RCWSR28 register hard-coding.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Erratum A009635 is valid only for LS2080A SoC and its
personality. Add SoC svr check.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Select missing BOARD_LATE_INIT from configs/ to
respective targets on arch area for Engicam imx6 boards.
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Move Freescale/NXP Vybrid to a standard arch/board approach, similar
to what has been done to i.MX 6 earlier in commit 89ebc82137 ("ARM:
mx6: move to a standard arch/board approach").
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
According to the MX7D fuse map the following speed grades are available:
800 MHz
500 MHz
1000 MHz
1200 MHz
So simply return the real frequency that corresponds to the speed grade.
With this change we see on boot:
CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
According to the MX7D fuse map the speed grade of the parts, which
return '1' is 500MHz instead of 850MHz, so fix it accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.
U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09)
Trying to boot from MMC1
U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100)
CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 40C
Reset cause: POR
Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board
DRAM: 256 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Video: 800x480x18
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Boot from MMC:
-------------
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1
U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 33C
Reset cause: POR
Model: Engicam Is.IoT MX6UL Starterkit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
isiotmx6ul>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF
size for HAB support boot on mx7ulp.
Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build
secure uboot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@nxp.com>
Cc: Alison Wang <b18965@freescale.com>
Implement the i2c clock enable and get function for mx7ulp. These
functions are required by imx_lpi2c driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.
Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.
Reuse some code in imx-common.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set
clock source, divider, clock rate and parent source.
Users need to include pcc.h to use the APIs to for peripherals clock. Each
peripheral clock is defined in enum pcc_clk type.
SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD
enablement and settings, and all SCG clock initialization. User need use enum
scg_clk to access each clock source.
In clock.c, we initialize necessary clocks at u-boot s_init and implement the
clock functions used by driver modules to operate clocks dynamically.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add a new driver under ULP directory to support its IOMUXC
controllers. The ULP has two IOMUXC, the IOMUXC0 is used
for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as
the default IOMUX in this driver. Any pins in IOMUXC0 needs
to configure with IOMUX_CONFIG_MPORTS in its mux_mode field.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
i.MX7ULP is a new series SoC which has different architecture
from previous i.MX platforms. Create a new cpu folder for it,
and add it to Kconfig.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.
The number of reference clock ticks that correspond to 10ms is normally
defined in the SysTick Calibration register's TENMS field. However, on some
devices this is wrong, so this driver allows the clock rate to be defined
using CONFIG_SYS_HZ_CLOCK.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
The workaround for ARM errata 725233 had been lost since
commit 45bf05854b (armv7: adapt omap3 to the new cache
maintenance framework). Bring it back in order to avoid
very difficult to reproduce, but actually encountered in
the wild CPU deadlocks when running software rendered
X11 desktop on OMAP3530 hardware.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Migrate to Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Read DMA operations causes CRC error on armv8 chassis 2 platforms
due to the erratum A-010635.
In order to support sata on these platforms, ECC needs to be disabled.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun <york.sun@nxp.com>
Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.
Signed-off-by: York Sun <york.sun@nxp.com>
Early MMU improves performance especially on emulators. However, the
early MMU is left enabled after the first stage of SPL boot. Instead
of flushing D-cache and dealing with re-enabling MMU for the second
stage U-Boot, disabling it for SPL build simplifies the process. The
performance penalty is unnoticeable on the real hardware. As of now,
SPL boot is not supported by existing emulators. So this should have
no impact on emulators.
Signed-off-by: York Sun <york.sun@nxp.com>
This patch follows the break-before-make process when making changes
to MMU table. MMU is disabled before changing TTBR to avoid any
potential race condition.
Signed-off-by: York Sun <york.sun@nxp.com>
Update mapping with actual DDR size. Non-existing memory should not
be mapped as "normal" memory to avoid speculative access.
Signed-off-by: York Sun <york.sun@nxp.com>
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.
Signed-off-by: York Sun <york.sun@nxp.com>
This moves all of the current ARM errata from various header files and in to
Kconfig. This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config. We now just select these once at the higher level in Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is
not completed. Finish this work by the tool.
During this move, let's rename it to CONFIG_MTD_NOR_FLASH.
Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH"
than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will
make the code more readable. Besides, negative meaning symbols do
not fit in obj-$(CONFIG_...) style Makefiles.
This commit was created as follows:
[1] Edit "default n" to "default y" in the config entry in
common/Kconfig.
[2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH"
[3] Rename the instances in defconfigs by the following:
find . -path './configs/*_defconfig' | xargs sed -i \
-e '/CONFIG_SYS_NO_FLASH=y/d' \
-e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/'
[4] Change the conditionals by the following:
find . -name '*.[ch]' | xargs sed -i \
-e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \
-e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \
-e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \
-e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/'
[5] Modify the following manually
- Rename the rest of instances
- Remove the description from README
- Create the new Kconfig entry in drivers/mtd/Kconfig
- Remove the old Kconfig entry from common/Kconfig
- Remove the garbage comments from include/configs/*.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This feature seems to be sometimes misunderstood. The intention is:
[1] Bring the slaves into the U-Boot proper image, not SPL (unless
you have a special reason to do otherwise).
[2] The operation must be done in a board (SoC) specific manner
since how to wake the slaves from the Boot ROM is SoC specific.
[3] The slaves must enter U-Boot proper after U-Boot relocates
itself because the "cpu-release-addr" property points to the
relocated memory area.
[2] is already explained in the help. We can make [1] even clearer
by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing,
so I am adding it to the list. Instead, "before the master CPU
jumps to the kernel" is a matter of course, so removed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested
in [1] during discussion of chiliSOM support patches.
[1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This option should not really be user selectable. Note that on PowerPC
we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
conditional on that.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
Move all of the status LED feature to drivers/led/Kconfig.
The LED status definitions were moved from the board configuration
files to the defconfig files.
TBD: Move all of the definitions in the include/status_led.h to the
relevant board's defconfig files.
Tested boards: CL-SOM-AM57x, CM-T335
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
commit: 65f83802b7 "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.
Since the above patch, you have to setup the fcr register.
For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...
This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.
Detected this issue with automated tbot tests on am335x
based shc board.
The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)
Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to
Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if
rev1.1 silicon used, need to fixup the MSI node to match it.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.
The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.
If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.
Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.
The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions. This patch enable it in the
sata axicc register.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.
This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Clear the content to zero and the ECC error bit of OCRAM1/2.
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.
Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only
occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined().
It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because
the spin-table code can't currently work in SPL, and the spin-table file
isn't even compiled in SPL.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Move (and rename) the following CONFIG options to Kconfig:
CONFIG_DAVINCI_MMC (renamed to CONFIG_MMC_DAVINCI)
CONFIG_OMAP_HSMMC (renamed to CONFIG_MMC_OMAP_HS)
CONFIG_MXC_MMC (renamed to CONFIG_MMC_MXC)
CONFIG_MXS_MMC (renamed to CONFIG_MMC_MXS)
CONFIG_TEGRA_MMC (renamed to CONFIG_MMC_SDHCI_TEGRA)
CONFIG_SUNXI_MMC (renamed to CONFIG_MMC_SUNXI)
They are the same option names as used in Linux.
This commit was created as follows:
[1] Rename the options with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_DAVINCI_MMC/CONFIG_MMC_DAVINCI/g
s/CONFIG_OMAP_HSMMC/CONFIG_MMC_OMAP_HS/g
s/CONFIG_MXC_MMC/CONFIG_MMC_MXC/g
s/CONFIG_MXS_MMC/CONFIG_MMC_MXS/g
s/CONFIG_TEGRA_MMC/CONFIG_MMC_SDHCI_TEGRA/g
s/CONFIG_SUNXI_MMC/CONFIG_MMC_SUNXI/g
'
[2] Commit the changes
[3] Create entries in driver/mmc/Kconfig.
(copied from Linux)
[4] Move the options with the following command
tools/moveconfig.py -y -r HEAD \
MMC_DAVINCI MMC_OMAP_HS MMC_MXC MMC_MXS MMC_SDHCI_TEGRA MMC_SUNXI
[5] Sort and align drivers/mmc/Makefile for readability
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a string description for SYS_VENDOR to allow configuring boards from
other vendors than just "xilinx".
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickly gets messy with this approach,
so let's just drop that intermediate macro and let the #include actually
insert the code directly.
This converts the callers and the callees, but doesn't change anything
at this point.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point, just refactoring to simplify
upcoming patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For boards that call s_init() when the SPL runs, we are expected to
setup an early stack before calling this C function.
Implement the proper AArch64 version of this based on the ARMv7 code.
This allows sunxi boards to setup the basic peripherals even with a
64-bit SPL.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Shuffle the macros around a little to remove the following warning
when building for i.MX28:
arch/arm/cpu/arm926ejs/mxs/spl_boot.c:44:26: warning: ‘iomux_boot’ defined but not used [-Wunused-const-variable=]
static const iomux_cfg_t iomux_boot[] = {
^~~~~~~~~~
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Use CONFIG_DM_ETH and remove board_eth_init code
from board files.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add CX9020 board based on mx53loco.
Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse
serial_mxc with DTE and prepare for device tree migration of other
functions and imx53 devices.
The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.
Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The mux for the lcd clock is not glitchless,
so need to first gate the clock before changing the mux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."
So fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
liteBoard is a development board which uses liteSOM as its base.
Hardware specification:
* liteSOM (i.MX6UL, DRAM, eMMC)
* Ethernet PHY (id 0)
* USB host (usb_otg1)
* MicroSD slot (uSDHC1)
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
It's not necessary to define the processor in the defconfig file.
The preferred method to select the SoC is via Kconfig file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This adds board support for the Toradex module family Colibri iMX6.
The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both
with a version for commercial and industrial temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
This adds board support for the Toradex module family Apalis iMX6.
The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with
commercial and industrial temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.
ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and
ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here
in Kconfig too.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
solve issue when bootstage is used with armV7 generic timer
first call of timer_get_boot_us() use the function get_timer()
before timer initialization (arch.timer_rate_hz = 0)
=> div by 0
Commit-notes
When I activate bootstage on ARMV7 architecture with platform
using the generic armv7 timer defined in file
./arch/arm/cpu/armv7m/timer.c
I have a issue because gd->arch.timer_rate_hz = 0
For me the get_timer() function should not used before timer_init
(which initialize gd->arch.timer_rate_hz) at least for the ARMV7
timer.
But in the init sequence, the first bootstage fucntion is called
before timer_init and this function use the timer function.
For me it is a error in the generic init sequence :
mark_bootstage is called before timer_init.
static init_fnc_t init_sequence_f[] = {
....
arch_cpu_init_dm,
mark_bootstage, /* need timer, go after init dm */
...
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
.......
To solve the issue for all the paltform, we can move timer_init()
call just before mark_bootstage() in this array...
It should be ok for ARMV7 but I don't sure for other platform
impacted
- the other ARM platform or ARMV7 wich don't use generic timer
- MIPS BLACKFIN NDS32 or SPARC
and I don't sure of impact for other function called
(board_early_init_f for example....)
=> This patch solve issue only in timer armv7
get_boot_us() can be called everytime without div by 0 issue
(gd->arch.timer_rate_hz is not used)
END
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Using alternative bootmode field to support automatic secondary boot
modes. It is purely software setting where SW modes are using free
bootmode combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch extends the imx6 clock code to enable or disable the EIM
slow clock, which in necessary when one wants to use EIM interface t
o read/write from external memory (e.g. NOR).
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
This patch adds initial support for Samtec VIN|ING 2000 board.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
UDOO Neo Board is a development board from Seco that has three models:
- UDOO Neo Basic
- UDOO Neo Basic Kick Starter
- UDOO Neo Extended
- UDOO Neo Full
All versions are based on the i.MX6 SoloX processor.
For more details about the UDOO Neo board, please refer to:
http://www.udoo.org/udoo-neo/
This work is based on a previous commit of Francesco Montefoschi
<francesco.monte@gmail.com>:
877b71184a
Only tested on the UDOO Neo Full board.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.
Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.
Signed-off-by: Eric Nelson <eric@nelint.com>
Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.
This routine will be used in a subsequent patch set adding a virtual
"mx6memcal" board, but could also be useful when gathering statistics
during an initial production run.
Signed-off-by: Eric Nelson <eric@nelint.com>
The DDR calibration routines have scattered support for bus
widths other than 64-bits:
-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.
Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.
This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.
Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Before disable cache, need to first flush cache.
There maybe dirty data in D-Cache before disable D-Cache.
After disable D-Cache, the first store instructions in
psci_v7_flush_dcache_all will directly store registers
{r4-r5, r7, r9-r11, lr} to memory.
If there is dirty data before disable D-Cache,
psci_v7_flush_dcache_all will flush data to memory,
and may overwrite the memory that hold the registers
{r4-r5, r7, r9-r11, lr}.
So before disable cache, first flush D-Cache.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Tom Rini <trini@konsulko.com>
As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: remove "inline" from declaration of initiator_type]
Reviewed-by: York Sun <york.sun@nxp.com>
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TZASC
Hence, skip initializing TZASC for Ls2080A based on SVR
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.
Signed-off-by: Cédric Schieli <cschieli@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
Detect the board very early and avoid reading eeprom multiple times.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is similar to Commit 93e6253d11 ("ARM: OMAP4/5: Centralize
early clock initialization") that was done for OMAP4+, reflecting the same
for AM33xx and AM43xx SoCs to centralize clock initialization.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add setup_early_clocks that calls setup_clocks_for_console for
ti81xx]
Signed-off-by: Tom Rini <trini@konsulko.com>
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround
implementing of erratum reusable for more SoCs.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Early system initialization is being done before initf_dm is being called
in U-Boot. Then system will fail to boot if any of the DM enabled driver
is being called in this system initialization code. So, rearrange the
code a bit so that DM enabled drivers can be called during early system
initialization. This is inspired by commit e850ed82bc ("ARM: OMAP4+: Allow
arch specific code to use early DM")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Highlights this time around:
- x86 efi_loader support
- hello world efi test case
- network device name is now representative
- terminal output reports modes correctly
- fix psci reset for ls1043/ls1046
- fix efi_add_runtime_mmio definition for x86
- efi_loader support for ls2080
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2016-11-17
Highlights this time around:
- x86 efi_loader support
- hello world efi test case
- network device name is now representative
- terminal output reports modes correctly
- fix psci reset for ls1043/ls1046
- fix efi_add_runtime_mmio definition for x86
- efi_loader support for ls2080
When implementing efi loader support, we can expose runtime services
for payloads. One such service is CPU reset.
This patch implements RTS CPU reset support for layerscape systems.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
The efi loader code has its own memory map, so it needs to be aware where
the spin tables are located, to ensure that no code writes into those
regions.
Signed-off-by: Alexander Graf <agraf@suse.de>
The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement
for reset. Don't enable generic PSCI reset code on them.
Signed-off-by: Alexander Graf <agraf@suse.de>
According to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:
'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Need to gate ENET clock when switching to a new clock parent, because
the mux is not glitchless.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Do not setup use_alt bit which copy alternative boot mode to
boot mode. The reason is that this bit is cleared after POR
but not after any software reset which will cause
that after SW reset bootrom will look for different boot image.
This patch setups alternative boot mode selection (purely SW
handling) and extends code to read this alternative boot mode first and
use it if it is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Zynq/ZynqMP boot.bin file contains a region for register initialization
data. Filling in proper values in this table can reduce boot time
(e.g. about 50ms faster on QSPI boot) and also reduce the size of
the SPL binary.
The table is a simple text file with register+data on each line. Other
lines are simply skipped. The file can be passed to mkimage using the
"-R" parameter.
It is recommended to add reg init file to board folder.
For example:
CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for EFI apps on aarch64. This includes start-up and relocation
code plus a link script.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: add kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For 64-bit ARM systems we provide just a timer_read_counter()
implementation and rely on the generic non-uclass get_ticks() function
in lib/time.c to call the former.
However this function is actually not 64-bit safe, as it assumes a
"long" to be 32-bit. Beside the fact that the resulting uint64_t
isn't bigger than "long" on 64-bit architectures and thus combining two
counters makes no sense, we get all kind of weird results when we try
to OR in the high value shifted by _32_ bits.
So let's avoid that function at all and provide a straight forward
get_ticks() implementation for ARMv8, which also is in line with ARMv7.
This fixes occasional immediate time-out expiration issues I see on the
Pine64 board. The root cause of this needs to be investigated, but this
fix looks like the right thing anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
CONFIG_SUNXI -> CONFIG_ARCH_SUNXI
and removed CONFIG_SUNIX from config_whitelist.txt
Cc: Simon Glass <sjg@chromium.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add DM_GPIO, DM_MMC support for u-boot and disable for SPL.
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
i.CoreM6 DualLite/Solo modules are system on module solutions
manufactured by Engicam with following characteristics:
CPU NXP i.MX6 DL, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
-----------------------------------------------
U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1
U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)
CPU: Freescale i.MX6SOLO rev1.3 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM: 256 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
Booting using the fdt blob at 0x18000000
Using Device Tree in place at 18000000, end 1800a787
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
Boot Log for i.CoreM6 Quad/Dual Starter Kit:
--------------------------------------------
U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1
U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)
CPU: Freescale i.MX6Q rev1.2 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
icorem6qdl>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Compiler attributes are more commonly __foo style tags rather than big
upper case eye sores like EFI_RUNTIME_TEXT.
Simon Glass felt quite strongly about this, so this patch converts our
existing defines over to more eye friendly ones.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have generic PSCI reset and shutdown support in place, we can
advertise those as EFI Run Time Services, allowing efi applications and
OSs to reset and shut down systems.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.
On these systems, we do not need to implement system reset manually,
but can instead rely on higher level firmware to deal with it.
The exclude list seems excessive right now, but NXP is working on
providing an in-tree PSCI implementation, so that all NXP systems
can eventually use PSCI as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: fix meson]
Reviewed-by: Simon Glass <sjg@chromium.org>
Using PSCI you can not only reset the system, you can also shut it down!
This patch exposes a function to do exactly that to whatever code wants
to make use of it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
All systems that are running on armv8 are running bare metal with firmware
that implements PSCI running in EL3. That means we don't really need to expose
the hypercall variants of them.
This patch leaves the code in, but makes the code explicit enough to have the
compiler optimize it out. With this we don't need to worry about hvc vs smc
calling convention when calling psci helper functions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jon Master reports that QEMU refuses to load a U-Boot image built
with CONFIG_ARMV7_NONSEC, but without CONFIG_ARMV7_PSCI since
commit 5a3aae68c7 ("ARM: armv7: guard memory reserve for PSCI
with #ifdef CONFIG_ARMV7_PSCI").
It looks like only PSCI that needs the Secure stack, so move
the #ifdef to guard the whole of .secure_stack allocation in order
not to create the empty section.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Jon Masters <jcm@redhat.com>
Link: http://patchwork.ozlabs.org/patch/664025/
Add silicon ID code for AM437x silicon. This can be used to print
the cpu info using CONFIG_DISPLAY_CPUINFO.
Also printing "CPU :" along with cpu name in order to be consistent
with other OMAP platforms.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
To create the soc environment variable we concatenate two strings
on the stack. So far, strcat has been used for the first string as
well as for the second string. Since the variable on the stack is
not initialized, the first strcat may not start using the first
entry in the character array. This then could lead to an buffer
overflow on the stack.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.
Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.
Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.
Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0 lookup.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
When enabled sec firmware framework, but lack of definition of
the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME
and SEC_FIRMWARE_TARGET_EL, there will be some build errors,
so give a default definition.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The SPL and U-Boot proper may use different initial stack
locations, which are configured via CONFIG_SPL_STACK and
CONFIG_SYS_INIT_SP_ADDR defines. The lowlevel_init.S
code needs to handle this in the same way as crt0.S
Without this fix, setting the U-Boot stack location to some
place, which is not safely accessible by the SPL (such as
the DRAM), causes a very early SPL deadlock.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and tidy up existing uses. Also add a function
comment to the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move DDR3, DDR4 and related config options to Kconfig and clean up
existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some config options should not have prompt. They are selected by choosing
target.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
SYSCLK is used as a reference clock for USB. When the USB controller
is used, SYSCLK must meet the additional requirement of 100 MHz.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.
Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: York Sun <york.sun@nxp.com>
The exact SoC revsion number can be recognized from U-Boot log.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This format can be flashed directly at address 0 of
the NAND FLASH, as it contains all necessary headers.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means
BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot
Device Selection this is NOR/OneNAND and not Reserved.
Use 0x10 which leads to b0001, which is a Reserved boot device.
With that the SoC reliably falls back to the serial loader.
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
Add i.MX6ULL EVK board support:
Add device tree file, which is copied from NXP Linux.
Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
The uart iomux settings are still keeped in board file.
Boot Log:
U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
CPU: Freescale i.MX6ULL rev1.0 at 396MHz
CPU: Commercial temperature grade (0C to 95C) at 15C
Reset cause: POR
Model: Freescale i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM: 512 MiB
MMC: initialized IMX pinctrl driver
FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop
MISC0 bit[6:4]) setting to 2b'110.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Update Clock settings and CCM register map for i.MX6ULL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Update misc SOC related settings for i.MX6ULL, such as FEC mac address,
cpu speed grading and mmdc channel mask clearing.
Also update s_init to skip pfd reset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here,
because this piece code is only for i.MX6UL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Rom already initialized clock at 396M and 132M for arm core and ahb,
so skip setting them again in U-Boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL.
If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high
security enabled models. Allow AM33xx devices to be built with
HS Device Type Support.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
The option SPL_SPI_SUPPORT is used to enable support in SPL for loading
images from SPI flash, it should not be used to determine the build type
of the SPL image itself. The ability to read images from SPI flash does
not imply the SPL will be booted from SPI flash.
Unconditionally build SPI flash compatible SPL images.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes.
For AM33xx devices additional image types are needed for
various SPL boot modes as the ROM checks for the name of
the boot mode in the file it loads.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.
This is similar to what has already been done in
9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are contiguous and start at the
start address given. If the start address is zero, the intention
is that the region will be automatically placed at the end of the
available external DRAM space.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Instead of using CONFIG_* name space, rename these two macros to
SYS_FSL_* space.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this option to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this config to Kconfig option and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Calvin Johnson <calvin.johnson@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this option to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
It should be enough to call low(5us)->high pulse for all cases
to provide proper reset. There is no need to call high->low->high.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SPL needs to have bigger stack size because of USB.
Simple malloc needs to be disabled because dfu code requires different
allocation functions. There is no space in OCM that's why random place
in DDR is used.
BOOTD must be disabled because it is causing compilation error.
All variables are disabled and used only variables valid for DFU because
they are simple huge. Including automatic variables added by
CONFIG_ENV_VARS_UBOOT_CONFIG.
Hardcode addresses for u-boot, atf, kernel and dtb
just for SPL DFU code.
Enable SPL DFU for zcu100.
Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There are a few options which use lower case. We should use upper case for
all CONFIG options.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly. Clearing BSS and calling board_init_r() will be done in
crt0_64.S.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The EPU Finite State Machie (FSM) is used in both the last stage of
system suspend and the earliest stage of system resume.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move this option to Kconfig and set its default value to 4; this
increases the number of supported CPUs for some boards.
It consumes 1KB memory per CPU for PSCI stack, but it should not
be a big deal, given the amount of memory used for the modern OSes.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select. Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_ARMV7_NONSEC is enabled, the linker script requires
CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
There is no reason to duplicate code for DRA7xx platforms as there
can be Rail grouping. The maximum voltage detection algorithm can still
be run on other platforms with no Rail grouping and does not harm as
it gives the same result.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
gpio_en field is introduced to detect if pmic is controlled by GPIO.
Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms
and remove the #ifndefs.
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Linux stopped the use of keyword 'boolean' in Kconfig.
Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
We create 2 sets of page tables: One for normal operation, one for
emergency (used while modifying the former).
Because the page tables grow dynamically, we have code that checks
for overflow. Unfortunately we didn't adjust the available space
variable while creating the emergency tables, so potentially someone
might run into an overflow there (not seen in real world yet though!).
Fix it by properly adjusting the size as well as the base offset in
emergency page table creation.
Reported-by: York Sun <york.sun@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
These config targets were added well before the Kconfig migration began
as a way to demonstrate how to make these platforms work with cut down
features. At this point in time they no longer serve a good purpose so
remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system. Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.
Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253e6 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.
I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable. However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.
CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.
Fixes: 95ebc253e6 ("types.h: move and redefine resource_size_t")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Ravi Babu <ravibabu@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Sandy Patterson <apatterson@sightlogix.com>
Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reported-by: Sandy Patterson <apatterson@sightlogix.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.
Signed-off-by: York Sun <york.sun@nxp.com>
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
A couple of commits have modified the am33xx/am437x ddr2/ddr3
initialization path to fix certain issues, but have had the side effect
of causing L3 noc errors during initialization. The two commits are:
69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
fc46ba "arm: am437x: Enable hardware leveling for EMIF"
The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
platforms. This delays initialization and refresh until a later stage.
The 500us timer can be programmed for platforms that require it
and for platforms that don't require it. It is currently hardcoded
for 400MHz systems. For systems with a higher memory frequency
this needs to be a larger value, and for systems with a lower
memory frequency this can be a lower value. This can be
considered a separate issue and corrected in a later commit.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit 17c2987 introduces an undesired dependency on CONFIG_SPL_LOAD_FIT
when building U-Boot for AM57xx and DRA7xx high-security (HS) devices that
causes the build to break when that option is not active. Fix this issue
by only building the u-boot_HS.img target when building U-Boot into an
actual FIT image.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit e29878f introduces an undesired dependency on CONFIG_SPL_LOAD_FIT
when building U-Boot for AM43xx high-security (HS) devices that causes the
build to break when that option is not active. Fix this issue by only
building the u-boot_HS.img target when building U-Boot into an actual
FIT image.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
identify_nand_chip hangs forever in loop when NAND is not present.
As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout
to let function fail gracefully allowing caller to know NAND is
not present. On NAND equipped board, reset succeeds on first read,
so 1000 loops seems to be safe timeout.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Use the secure firmware framework to integrate FSL PPA into U-Boot.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the 'target exception level'
that is determined by the respective secure firmware.
So far, the framework support only FIT format image, and need to define
the name of which config node should be used in 'configurations' and
the name of property for the raw secure firmware image in that config.
The FIT image should be stored in Byte accessing memory, such as NOR
Flash, or else it should be copied to main memory to use this framework.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.
Define the function mmu_setup() for fsl-layerscape to cover the weak
one.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Drop platform code to create static MMU tables. Use common framework
to create MMU tables on the run. Tested on LS2080ARDB with secure and
non-secure ram scenarios.
Signed-off-by: York Sun <york.sun@nxp.com>
Use existing Kconfig symbols to let the user configure whether to
build a U-Boot with non-secure mode support or not. This also allows
to enable virtualization extension easily.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This can be useful if the same U-Boot binary is used for boards
available with a i.MX 7Solo and i.MX 7Dual.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.
Signed-off-by: York Sun <york.sun@nxp.com>
When page tables are created, allow later table to be created on
previous block entry. Splitting block feature is already working
with current code. This patch only rearranges the code order and
adds one condition to call split_block().
Signed-off-by: York Sun <york.sun@nxp.com>
Make setup_pgtages() and get_tcr() available for platform code to
customize MMU tables.
Remove unintentional call of create_table().
Signed-off-by: York Sun <york.sun@nxp.com>
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
Now that we have a secure data section for storing variables, there
should be no need for platform code to get the stack address.
Make psci_get_cpu_stack_top a local function, as it should only be
used in armv7/psci.S and only by psci_stack_setup.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have a secure data section and space to store per-CPU target
PC address, switch to it instead of storing the target PC on the stack.
Also save clobbered r4-r7 registers on the stack and restore them on
return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have a data section, add helper functions to save and fetch
per-CPU target PC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The secure monitor may need to store global or static values within the
secure section of memory, such as target PC or CPU power status.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi and i.mx7 both define the __secure modifier to put functions in
the secure section. Move this to a common place.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
As the PSCI implementation grows, we might exceed the size of the secure
memory that holds the firmware.
Add a configurable CONFIG_ARMV7_SECURE_MAX_SIZE so platforms can define
how much secure memory is available. The linker then checks the size of
the whole secure section against this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
psci_text_end was used to calculate the PSCI stack address following the
secure monitor text. Now that we have an explicit secure stack section,
this is no longer used.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have a secure stack section that guarantees usable memory,
allocate the PSCI stacks in that section.
Also add a diagram detailing how the stacks are placed in memory.
Reserved space for the target PC remains unchanged. This should be
moved to global variables within a secure data section in the future.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Until now we've been using memory beyond psci_text_end as stack space
for the secure monitor or PSCI implementation, even if space was not
allocated for it.
This was partially fixed in ("ARM: allocate extra space for PSCI stack
in secure section during link phase"). However, calculating stack space
from psci_text_end in one place, while allocating the space in another
is error prone.
This patch adds a separate empty secure stack section, with space for
CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also
__secure_stack_start and __secure_stack_end symbols. The linker script
handles calculating the correct VMAs for the stack section. For
platforms that relocate/copy the secure monitor before using it, the
space is not allocated in the executable, saving space.
For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page
of stack space for 4 CPUs is allocated, matching the previous behavior.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Targets that define CONFIG_ARMV7_SECURE_BASE will copy the secure section
to another address before execution.
Since the secure section in the u-boot image is only storage, there's
no reason to page align it and increase the binary image size.
Page align the secure section only when CONFIG_ARMV7_SECURE_BASE is not
defined. And instead of just aligning the __secure_start symbol, align
the whole .__secure_start section. This also makes the section empty,
so we need to add KEEP() to the input entry to prevent the section from
being garbage collected.
Also use ld constant "COMMONPAGESIZE" instead of hardcoded page size.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch finishes the rewrite of sunxi specific PSCI parts into C
code.
The assembly-only stack setup code has been factored out into a common
function for ARMv7. The GIC setup code can be renamed as psci_arch_init.
And we can use an empty stub function for psci_text_end.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Every platform has the same stack setup code in assembly as part of
psci_arch_init.
Move this out into a common separate function, psci_stack_setup, for
all platforms. This will allow us to move the remaining parts of
psci_arch_init into C code, or drop it entirely.
Also provide a stub no-op psci_arch_init for platforms that don't need
their own specific setup code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
At present armv7 will unhappily invalidate a cache region and print an
error message. Make it skip the operation instead, as it does with other
cache operations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Errata i727 is applicable on all OMAP5 and DRA7 variants but enabled only
on OMAP5 ES1.0. So, enable it on all platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's[1].
[1]: https://github.com/EmcraftSystems/u-boot
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
Modify the SPL build procedure for AM437x high-security (HS) device
variants to create a secure u-boot_HS.img FIT blob that contains U-Boot
and DTB artifacts signed (and optionally encrypted) with a TI-specific
process based on the CONFIG_TI_SECURE_DEVICE config option and the
externally-provided image signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS)
device variants to create a secure u-boot_HS.img FIT blob that contains
U-Boot and DTB artifacts signed with a TI-specific process based on the
CONFIG_TI_SECURE_DEVICE config option and the externally-provided image
signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds commands so that when a secure device is in use and the SPL is
built to load a FIT image (with combined U-Boot binary and various
DTBs), these components that get fed into the FIT are all processed to
be signed/encrypted/etc. as per the operations performed by the
secure-binary-image.sh script of the TI SECDEV package. Furthermore,
perform minor comments cleanup to make better use of the available
space.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adds an API that verifies a signature attached to an image (binary
blob). This API is basically a entry to a secure ROM service provided by
the device and accessed via an SMC call, using a particular calling
convention.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a generic C-callable API for making secure ROM calls on OMAP and
OMAP-compatible devices. This API provides the important function of
flushing the ROM call arguments to memory from the cache, so that the
secure world will have a coherent view of those arguments. Then is
simply calls the omap_smc_sec routine.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible high-security (HS) device variants. While at it, also
perform minor cleanup/alignment without any change in functionality.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds missing flush_dcache_range and invalidate_dcache_range dummy
(empty) placeholder functions to the #else portion of the #ifndef
CONFIG_SYS_DCACHE_OFF, where full implementations of these functions
are defined.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are two enable methods supported by ARM64 Linux; psci and
spin-table. The latter is simpler and helpful for quick SoC bring
up. My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.
Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:
- We must hard-code CPU_RELEASE_ADDR so that it matches the
"cpu-release-addr" property in the DT that comes from the
kernel tree.
- The Documentation/arm64/booting.txt in Linux requires that
the release address must be zero-initialized, but it is not
cared by the common code in U-Boot. We must do it in a board
function.
- There is no systematic way to protect the spin-table code from
the kernel. We are supposed to do it in a board specific manner,
but it is difficult to predict where the spin-table code will be
located after the relocation. So, it also makes difficult to
hard-code /memreserve/ in the DT of the kernel.
So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Upon further review this breaks most other platforms as we need to check
what core we're running on before touching it at all.
This reverts commit d73718f323.
Signed-off-by: Tom Rini <trini@konsulko.com>
Custom Board based on MX6 Dual, 1GB RAM and eMMC.
There are two variants of the board with and without
PCIe (ZC5202 and ZC5601).
Signed-off-by: Stefano Babic <sbabic@denx.de>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.
So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
The handling of the "usage counter" is incorrect, and the clock should
only be disabled when transitioning from 1 to 0.
Reported-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
The Kona Peripheral Slave CCU has 4 policy mask registers, not 8.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
gic_kick_secondary_cpus can directly return to the caller of
smp_kick_all_cpus. We do not have to use x29 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
