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arm: psci: make psci usable on single core socs
PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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5 changed files with 31 additions and 30 deletions
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@ -7,25 +7,19 @@
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#include <common.h>
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#include <asm/psci.h>
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#include <asm/system.h>
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#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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#include <asm/armv8/sec_firmware.h>
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#endif
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#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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int psci_update_dt(void *fdt)
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{
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#ifdef CONFIG_MP
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#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
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#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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/*
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* If the PSCI in SEC Firmware didn't work, avoid to update the
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* device node of PSCI. But still return 0 instead of an error
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* number to support detecting PSCI dynamically and then switching
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* the SMP boot method between PSCI and spin-table.
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*/
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if (sec_firmware_support_psci_version() == 0xffffffff)
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if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
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return 0;
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#endif
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fdt_psci(fdt);
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#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
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@ -34,7 +28,6 @@ int psci_update_dt(void *fdt)
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__secure_end - __secure_start);
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#endif
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#endif
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#endif
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return 0;
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}
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#endif
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@ -15,18 +15,14 @@
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#include <asm/arch/soc.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/speed.h>
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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#include <efi_loader.h>
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#include <fm_eth.h>
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#include <fsl-mc/fsl_mc.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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#include <asm/armv8/sec_firmware.h>
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#endif
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#ifdef CONFIG_SYS_FSL_DDR
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#include <fsl_ddr.h>
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#endif
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@ -475,13 +471,19 @@ int cpu_eth_init(bd_t *bis)
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return error;
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}
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static inline int check_psci(void)
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{
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unsigned int psci_ver;
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psci_ver = sec_firmware_support_psci_version();
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if (psci_ver == PSCI_INVALID_VER)
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return 1;
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return 0;
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}
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int arch_early_init_r(void)
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{
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#ifdef CONFIG_MP
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int rv = 1;
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u32 psci_ver = 0xffffffff;
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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u32 svr_dev_id;
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/*
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@ -495,18 +497,13 @@ int arch_early_init_r(void)
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#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
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erratum_a009942_check_cpo();
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#endif
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#ifdef CONFIG_MP
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#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
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defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
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/* Check the psci version to determine if the psci is supported */
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psci_ver = sec_firmware_support_psci_version();
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#endif
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if (psci_ver == 0xffffffff) {
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rv = fsl_layerscape_wake_seconday_cores();
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if (rv)
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if (check_psci()) {
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debug("PSCI: PSCI does not exist.\n");
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/* if PSCI does not exist, boot secondary cores here */
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if (fsl_layerscape_wake_seconday_cores())
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printf("Did not wake secondary cores\n");
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}
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#endif
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#ifdef CONFIG_SYS_HAS_SERDES
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fsl_serdes_init();
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@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void)
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if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
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return _sec_firmware_support_psci_version();
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return 0xffffffff;
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return PSCI_INVALID_VER;
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}
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#endif
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@ -31,7 +31,11 @@ extern u64 __spin_table[];
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extern u64 __real_cntfrq;
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extern u64 *secondary_boot_code;
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extern size_t __secondary_boot_code_size;
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#ifdef CONFIG_MP
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int fsl_layerscape_wake_seconday_cores(void);
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#else
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static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
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#endif
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void *get_spin_tbl_addr(void);
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phys_addr_t determine_mp_bootpg(void);
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void secondary_boot_func(void);
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@ -7,12 +7,19 @@
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#ifndef __SEC_FIRMWARE_H_
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#define __SEC_FIRMWARE_H_
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#define PSCI_INVALID_VER 0xffffffff
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int sec_firmware_init(const void *, u32 *, u32 *);
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int _sec_firmware_entry(const void *, u32 *, u32 *);
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bool sec_firmware_is_valid(const void *);
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#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
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unsigned int sec_firmware_support_psci_version(void);
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unsigned int _sec_firmware_support_psci_version(void);
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#else
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static inline unsigned int sec_firmware_support_psci_version(void)
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{
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return PSCI_INVALID_VER;
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}
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#endif
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#endif /* __SEC_FIRMWARE_H_ */
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