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https://github.com/AsahiLinux/u-boot
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fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
York Sun
Tom Rini
parent
a105503851
commit
d26e34c4c4
138 changed files with 262 additions and 237 deletions
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@ -770,6 +770,7 @@ config TARGET_LS1021AQDS
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select ARCH_LS1021A
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select ARCH_SUPPORT_PSCI
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select LS1_DEEP_SLEEP
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select SYS_FSL_DDR
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config TARGET_LS1021ATWR
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bool "Support ls1021atwr"
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@ -3,8 +3,10 @@ config ARCH_LS1021A
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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@ -49,47 +51,6 @@ config SYS_FSL_SRDS_2
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_DDR
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bool "Freescale DDR driver"
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help
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Select Freescale General DDR driver, shared between most Freescale
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PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
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based Layerscape SoCs (such as ls2080a).
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config SYS_FSL_DDR_BE
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bool
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default y
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help
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Access DDR registers in big-endian.
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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config SYS_FSL_DDRC_GEN4
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bool
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config SYS_FSL_DDR3
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bool "Freescale DDR3 controller"
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depends on !SYS_FSL_DDR4
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_ARM_GEN3
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help
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Enable Freescale DDR3 controller on ARM-based SoCs.
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config SYS_FSL_DDR4
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bool "Freescale DDR4 controller"
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_GEN4
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help
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Enable Freescale DDR4 controller.
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1021A
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@ -8,28 +8,33 @@ config ARCH_LS1012A
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config ARCH_LS1043A
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bool
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select FSL_LSCH2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_DDR4
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config ARCH_LS1046A
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bool
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select FSL_LSCH2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR4
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SRDS_2
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config ARCH_LS2080A
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bool
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select FSL_LSCH3
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select SYS_FSL_DDR4
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_DP_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_2
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@ -71,9 +76,6 @@ config FSL_PPA_ARMV8_PSCI
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implemented under the common ARMv8 PSCI framework.
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endmenu
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config SYS_FSL_MMDC
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bool
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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@ -129,49 +131,4 @@ config SYS_FSL_SRDS_2
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_DDR
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bool "Freescale DDR driver"
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help
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Select Freescale General DDR driver, shared between most Freescale
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PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
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based Layerscape SoCs (such as ls2080a).
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config SYS_FSL_DDR_BE
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bool
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help
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Access DDR registers in big-endian.
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config SYS_FSL_DDR_LE
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bool
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help
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Access DDR registers in little-endian.
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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config SYS_FSL_DDRC_GEN4
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bool
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config SYS_FSL_DDR3
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bool "Freescale DDR3 controller"
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depends on !SYS_FSL_DDR4
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_ARM_GEN3
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help
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Enable Freescale DDR3 controller on ARM-based SoCs.
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config SYS_FSL_DDR4
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bool "Freescale DDR4 controller"
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_GEN4
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help
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Enable Freescale DDR4 controller.
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endmenu
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@ -175,11 +175,11 @@
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#define CONFIG_SYS_FSL_ERRATUM_A009942
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#define CONFIG_SYS_FSL_ERRATUM_A009660
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_ARCH_LS1012A)
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#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
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#elif defined(CONFIG_ARCH_LS1012A)
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#elif defined(CONFIG_ARCH_LS1046A)
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_NUM_FMAN 1
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@ -30,9 +30,13 @@ config MPC83xx
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config MPC85xx
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bool "MPC85xx"
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select CREATE_ARCH_SYMLINK
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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config MPC86xx
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bool "MPC86xx"
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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config 8xx
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bool "MPC8xx"
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@ -38,6 +38,9 @@ config TARGET_MPC832XEMDS
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config TARGET_MPC8349EMDS
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bool "Support MPC8349EMDS"
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select SYS_FSL_DDR
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_DDR_BE
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config TARGET_MPC8349ITX
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bool "Support MPC8349ITX"
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@ -68,6 +68,8 @@ config TARGET_P5040DS
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config TARGET_MPC8536DS
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bool "Support MPC8536DS"
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select ARCH_MPC8536
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# Use DDR3 controller with DDR2 DIMMs on this board
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select SYS_FSL_DDRC_GEN3
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config TARGET_MPC8540ADS
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bool "Support MPC8540ADS"
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@ -104,6 +106,8 @@ config TARGET_MPC8569MDS
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config TARGET_MPC8572DS
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bool "Support MPC8572DS"
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select ARCH_MPC8572
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# Use DDR3 controller with DDR2 DIMMs on this board
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select SYS_FSL_DDRC_GEN3
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config TARGET_P1010RDB_PA
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bool "Support P1010RDB_PA"
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@ -300,6 +304,8 @@ config TARGET_XPEDITE520X
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config TARGET_XPEDITE537X
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bool "Support xpedite537x"
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select ARCH_MPC8572
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# Use DDR3 controller with DDR2 DIMMs on this board
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select SYS_FSL_DDRC_GEN3
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config TARGET_XPEDITE550X
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bool "Support xpedite550x"
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@ -325,6 +331,7 @@ config ARCH_B4420
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bool
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select E500MC
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -333,6 +340,7 @@ config ARCH_B4860
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bool
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select E500MC
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -340,6 +348,7 @@ config ARCH_B4860
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config ARCH_BSC9131
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -347,6 +356,7 @@ config ARCH_BSC9131
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config ARCH_BSC9132
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -355,6 +365,7 @@ config ARCH_BSC9132
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config ARCH_C29X
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_6
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@ -363,6 +374,8 @@ config ARCH_C29X
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config ARCH_MPC8536
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -371,10 +384,12 @@ config ARCH_MPC8536
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config ARCH_MPC8540
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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config ARCH_MPC8541
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -382,6 +397,7 @@ config ARCH_MPC8541
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config ARCH_MPC8544
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -390,6 +406,8 @@ config ARCH_MPC8544
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config ARCH_MPC8548
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -398,6 +416,7 @@ config ARCH_MPC8548
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config ARCH_MPC8555
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -405,10 +424,12 @@ config ARCH_MPC8555
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config ARCH_MPC8560
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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config ARCH_MPC8568
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -416,6 +437,7 @@ config ARCH_MPC8568
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config ARCH_MPC8569
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -423,14 +445,17 @@ config ARCH_MPC8569
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config ARCH_MPC8572
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bool
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select FSL_LAW
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select SYS_PPC_E500_USE_DEBUG_TLB
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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config ARCH_P1010
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -439,6 +464,7 @@ config ARCH_P1010
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config ARCH_P1011
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -447,6 +473,7 @@ config ARCH_P1011
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config ARCH_P1020
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -455,6 +482,7 @@ config ARCH_P1020
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config ARCH_P1021
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -463,6 +491,7 @@ config ARCH_P1021
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config ARCH_P1022
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -471,6 +500,7 @@ config ARCH_P1022
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config ARCH_P1023
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -478,6 +508,7 @@ config ARCH_P1023
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config ARCH_P1024
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -486,6 +517,7 @@ config ARCH_P1024
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config ARCH_P1025
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -494,6 +526,7 @@ config ARCH_P1025
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config ARCH_P2020
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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@ -503,6 +536,7 @@ config ARCH_P2041
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bool
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select E500MC
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select FSL_LAW
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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@ -511,6 +545,7 @@ config ARCH_P3041
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bool
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select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -519,6 +554,7 @@ config ARCH_P4080
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -527,6 +563,7 @@ config ARCH_P5020
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -535,6 +572,7 @@ config ARCH_P5040
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -546,6 +584,8 @@ config ARCH_T1023
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
|
|
@ -554,6 +594,8 @@ config ARCH_T1024
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
|
|
@ -562,6 +604,8 @@ config ARCH_T1040
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
|
|
@ -570,6 +614,8 @@ config ARCH_T1042
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
|
|
@ -578,6 +624,7 @@ config ARCH_T2080
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -586,6 +633,7 @@ config ARCH_T2081
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -594,6 +642,7 @@ config ARCH_T4160
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
@ -602,6 +651,7 @@ config ARCH_T4240
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_BE
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
|
|
|
|||
|
|
@ -29,10 +29,14 @@ endchoice
|
|||
config ARCH_MPC8610
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR1
|
||||
select SYS_FSL_HAS_DDR2
|
||||
|
||||
config ARCH_MPC8641
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_FSL_HAS_DDR1
|
||||
select SYS_FSL_HAS_DDR2
|
||||
|
||||
config FSL_LAW
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -9,16 +9,13 @@
|
|||
|
||||
#ifdef CONFIG_MPC85xx
|
||||
#include <asm/config_mpc85xx.h>
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC86xx
|
||||
#include <asm/config_mpc86xx.h>
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC83xx
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#endif
|
||||
|
||||
#ifndef HWCONFIG_BUFFER_SIZE
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
|
||||
|
||||
#include <fsl_ddrc_version.h>
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
|
||||
/* IP endianness */
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
|
|
@ -28,17 +27,13 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8540)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8541)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8544)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8548)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
|
||||
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
|
||||
#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
|
||||
|
|
@ -52,13 +47,10 @@
|
|||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8555)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8560)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC8568)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define QE_MURAM_SIZE 0x10000UL
|
||||
#define MAX_QE_RISC 2
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
|
@ -544,9 +536,6 @@
|
|||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
|
@ -588,9 +577,6 @@
|
|||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
|
@ -697,13 +683,6 @@
|
|||
#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN4)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN3
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_C29X)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,6 +7,4 @@
|
|||
#ifndef _ASM_MPC86xx_CONFIG_H_
|
||||
#define _ASM_MPC86xx_CONFIG_H_
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_86XX
|
||||
|
||||
#endif /* _ASM_MPC85xx_CONFIG_H_ */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_CMD_USB=y
|
|||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ CONFIG_CMD_USB=y
|
|||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_FIT=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
|
||||
CONFIG_FIT=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
@ -38,6 +37,7 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -27,6 +26,7 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -27,6 +26,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -28,6 +27,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -31,6 +30,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
@ -39,6 +38,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
@ -41,6 +40,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -24,6 +23,7 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043ARDB=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043ARDB=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043ARDB=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043ARDB=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_FSL_DDR4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
|
||||
CONFIG_NAND_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_QSPI_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4,EMMC_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
|
||||
CONFIG_QSPI_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="EMU,LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,LS2080A"
|
||||
CONFIG_QSPI_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_CMD_GREPENV=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -15,5 +15,6 @@ CONFIG_CMD_DHCP=y
|
|||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@ source "drivers/crypto/Kconfig"
|
|||
|
||||
source "drivers/demo/Kconfig"
|
||||
|
||||
source "drivers/ddr/fsl/Kconfig"
|
||||
|
||||
source "drivers/dfu/Kconfig"
|
||||
|
||||
source "drivers/dma/Kconfig"
|
||||
|
|
|
|||
122
drivers/ddr/fsl/Kconfig
Normal file
122
drivers/ddr/fsl/Kconfig
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
config SYS_FSL_DDR
|
||||
bool
|
||||
help
|
||||
Select Freescale General DDR driver, shared between most Freescale
|
||||
PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
|
||||
based Layerscape SoCs (such as ls2080a).
|
||||
|
||||
config SYS_FSL_MMDC
|
||||
bool
|
||||
help
|
||||
Select Freescale Multi Mode DDR controller (MMDC).
|
||||
|
||||
config SYS_FSL_DDR_BE
|
||||
bool
|
||||
help
|
||||
Access DDR registers in big-endian
|
||||
|
||||
config SYS_FSL_DDR_LE
|
||||
bool
|
||||
help
|
||||
Access DDR registers in little-endian
|
||||
|
||||
menu "Freescale DDR controllers"
|
||||
depends on SYS_FSL_DDR
|
||||
|
||||
config SYS_FSL_DDR_VER
|
||||
int
|
||||
default 50 if SYS_FSL_DDR_VER_50
|
||||
default 47 if SYS_FSL_DDR_VER_47
|
||||
default 46 if SYS_FSL_DDR_VER_46
|
||||
default 44 if SYS_FSL_DDR_VER_44
|
||||
|
||||
config SYS_FSL_DDR_VER_50
|
||||
bool
|
||||
|
||||
config SYS_FSL_DDR_VER_47
|
||||
bool
|
||||
|
||||
config SYS_FSL_DDR_VER_46
|
||||
bool
|
||||
|
||||
config SYS_FSL_DDR_VER_44
|
||||
bool
|
||||
|
||||
config SYS_FSL_DDRC_GEN1
|
||||
bool
|
||||
help
|
||||
Enable Freescale DDR controller.
|
||||
|
||||
config SYS_FSL_DDRC_GEN2
|
||||
bool
|
||||
depends on !MPC86xx
|
||||
help
|
||||
Enable Freescale DDR2 controller.
|
||||
|
||||
config SYS_FSL_DDRC_86XX_GEN2
|
||||
bool
|
||||
depends on MPC86xx
|
||||
help
|
||||
Enable Freescale DDR2 controller for MPC86xx SoCs.
|
||||
|
||||
config SYS_FSL_DDRC_GEN3
|
||||
bool
|
||||
depends on PPC
|
||||
help
|
||||
Enable Freescale DDR3 controller for PowerPC SoCs.
|
||||
|
||||
config SYS_FSL_DDRC_ARM_GEN3
|
||||
bool
|
||||
depends on ARM
|
||||
help
|
||||
Enable Freescale DDR3 controller for ARM SoCs.
|
||||
|
||||
config SYS_FSL_DDRC_GEN4
|
||||
bool
|
||||
help
|
||||
Enable Freescale DDR4 controller.
|
||||
|
||||
config SYS_FSL_HAS_DDR4
|
||||
bool
|
||||
|
||||
config SYS_FSL_HAS_DDR3
|
||||
bool
|
||||
|
||||
config SYS_FSL_HAS_DDR2
|
||||
bool
|
||||
|
||||
config SYS_FSL_HAS_DDR1
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "DDR technology"
|
||||
default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
|
||||
default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
|
||||
default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
|
||||
default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
|
||||
|
||||
config SYS_FSL_DDR4
|
||||
bool "Freescale DDR4 controller"
|
||||
depends on SYS_FSL_HAS_DDR4
|
||||
select SYS_FSL_DDRC_GEN4
|
||||
|
||||
config SYS_FSL_DDR3
|
||||
bool "Freescale DDR3 controller"
|
||||
depends on SYS_FSL_HAS_DDR3
|
||||
select SYS_FSL_DDRC_GEN3 if PPC
|
||||
select SYS_FSL_DDRC_ARM_GEN3 if ARM
|
||||
|
||||
config SYS_FSL_DDR2
|
||||
bool "Freescale DDR2 controller"
|
||||
depends on SYS_FSL_HAS_DDR2
|
||||
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
|
||||
select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
|
||||
|
||||
config SYS_FSL_DDR1
|
||||
bool "Freescale DDR1 controller"
|
||||
depends on SYS_FSL_HAS_DDR1
|
||||
select SYS_FSL_DDRC_GEN1
|
||||
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
|
@ -30,7 +30,7 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
|
|||
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
|
||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
|
||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
|
||||
obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
|
||||
obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
|
||||
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
|
||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
|
||||
obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
|
||||
|
|
|
|||
|
|
@ -228,7 +228,6 @@ unsigned long get_board_ddr_clk(void);
|
|||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_FSL_DDR_INTERACTIVE
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -70,7 +70,6 @@
|
|||
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
#undef CONFIG_SYS_DDR_RAW_TIMING
|
||||
#undef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
|
|
|
|||
|
|
@ -125,7 +125,6 @@
|
|||
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
|
||||
#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
|
||||
|
|
|
|||
|
|
@ -126,7 +126,6 @@
|
|||
#define CONFIG_PANIC_HANG
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x50
|
||||
|
|
|
|||
|
|
@ -60,12 +60,9 @@
|
|||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
|
||||
|
||||
/*
|
||||
* define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
|
||||
* undefine it to use old spd_sdram.c
|
||||
* SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
|
||||
* unselect it to use old spd_sdram.c
|
||||
*/
|
||||
#define CONFIG_SYS_FSL_DDR2
|
||||
#ifdef CONFIG_SYS_FSL_DDR2
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS1 0x52
|
||||
#define SPD_EEPROM_ADDRESS2 0x51
|
||||
|
|
@ -74,7 +71,6 @@
|
|||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 32-bit data path mode.
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue