mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
armv7m: add instruction & data cache support
This patch adds armv7m instruction & data cache support. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
This commit is contained in:
Vikas Manocha
Tom Rini
parent
3f66149d9f
commit
bf4d0495d2
4 changed files with 363 additions and 4 deletions
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@ -6,6 +6,5 @@
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#
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extra-y := start.o
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obj-y += cpu.o
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obj-y += cpu.o cache.o
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obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
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336
arch/arm/cpu/armv7m/cache.c
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336
arch/arm/cpu/armv7m/cache.c
Normal file
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@ -0,0 +1,336 @@
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/*
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* (C) Copyright 2017
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/armv7m.h>
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#include <asm/io.h>
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/* Cache maintenance operation registers */
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#define V7M_CACHE_REG_ICIALLU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
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#define INVAL_ICACHE_POU 0
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#define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
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#define V7M_CACHE_REG_DCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
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#define V7M_CACHE_REG_DCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
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#define V7M_CACHE_REG_DCCMVAU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
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#define V7M_CACHE_REG_DCCMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
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#define V7M_CACHE_REG_DCCSW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
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#define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
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#define V7M_CACHE_REG_DCCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
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#define WAYS_SHIFT 30
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#define SETS_SHIFT 5
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/* armv7m processor feature registers */
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#define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
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#define V7M_PROC_REG_CTR ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
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#define V7M_PROC_REG_CCSIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
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#define MASK_NUM_WAYS GENMASK(12, 3)
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#define MASK_NUM_SETS GENMASK(27, 13)
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#define CLINE_SIZE_MASK GENMASK(2, 0)
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#define NUM_WAYS_SHIFT 3
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#define NUM_SETS_SHIFT 13
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#define V7M_PROC_REG_CSSELR ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
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#define SEL_I_OR_D BIT(0)
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enum cache_type {
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DCACHE,
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ICACHE,
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};
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/* PoU : Point of Unification, Poc: Point of Coherency */
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enum cache_action {
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INVALIDATE_POU, /* i-cache invalidate by address */
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INVALIDATE_POC, /* d-cache invalidate by address */
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INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
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FLUSH_POU, /* d-cache clean by address to the PoU */
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FLUSH_POC, /* d-cache clean by address to the PoC */
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FLUSH_SET_WAY, /* d-cache clean by sets/ways */
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FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
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FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
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};
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#ifndef CONFIG_SYS_DCACHE_OFF
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struct dcache_config {
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u32 ways;
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u32 sets;
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};
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static void get_cache_ways_sets(struct dcache_config *cache)
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{
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u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
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cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
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cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
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}
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/*
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* Return the io register to perform required cache action like clean or clean
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* & invalidate by sets/ways.
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*/
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static u32 *get_action_reg_set_ways(enum cache_action action)
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{
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switch (action) {
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case INVALIDATE_SET_WAY:
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return V7M_CACHE_REG_DCISW;
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case FLUSH_SET_WAY:
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return V7M_CACHE_REG_DCCSW;
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case FLUSH_INVAL_SET_WAY:
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return V7M_CACHE_REG_DCCISW;
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default:
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break;
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};
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return NULL;
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}
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/*
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* Return the io register to perform required cache action like clean or clean
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* & invalidate by adddress or range.
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*/
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static u32 *get_action_reg_range(enum cache_action action)
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{
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switch (action) {
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case INVALIDATE_POU:
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return V7M_CACHE_REG_ICIMVALU;
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case INVALIDATE_POC:
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return V7M_CACHE_REG_DCIMVAC;
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case FLUSH_POU:
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return V7M_CACHE_REG_DCCMVAU;
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case FLUSH_POC:
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return V7M_CACHE_REG_DCCMVAC;
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case FLUSH_INVAL_POC:
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return V7M_CACHE_REG_DCCIMVAC;
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default:
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break;
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}
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return NULL;
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}
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static u32 get_cline_size(enum cache_type type)
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{
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u32 size;
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if (type == DCACHE)
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clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
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else if (type == ICACHE)
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setbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
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/* Make sure cache selection is effective for next memory access */
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dsb();
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size = readl(V7M_PROC_REG_CCSIDR) & CLINE_SIZE_MASK;
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/* Size enocoded as 2 less than log(no_of_words_in_cache_line) base 2 */
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size = 1 << (size + 2);
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debug("cache line size is %d\n", size);
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return size;
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}
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/* Perform the action like invalidate/clean on a range of cache addresses */
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static int action_cache_range(enum cache_action action, u32 start_addr,
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int64_t size)
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{
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u32 cline_size;
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u32 *action_reg;
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enum cache_type type;
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action_reg = get_action_reg_range(action);
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if (!action_reg)
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return -EINVAL;
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if (action == INVALIDATE_POU)
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type = ICACHE;
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else
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type = DCACHE;
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/* Cache line size is minium size for the cache action */
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cline_size = get_cline_size(type);
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/* Align start address to cache line boundary */
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start_addr &= ~(cline_size - 1);
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debug("total size for cache action = %llx\n", size);
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do {
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writel(start_addr, action_reg);
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size -= cline_size;
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start_addr += cline_size;
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} while (size > cline_size);
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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debug("cache action on range done\n");
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return 0;
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}
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/* Perform the action like invalidate/clean on all cached addresses */
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static int action_dcache_all(enum cache_action action)
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{
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struct dcache_config cache;
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u32 *action_reg;
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int i, j;
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action_reg = get_action_reg_set_ways(action);
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if (!action_reg)
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return -EINVAL;
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clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
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/* Make sure cache selection is effective for next memory access */
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dsb();
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get_cache_ways_sets(&cache); /* Get number of ways & sets */
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debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1);
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for (i = cache.sets; i >= 0; i--) {
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for (j = cache.ways; j >= 0; j--) {
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writel((j << WAYS_SHIFT) | (i << SETS_SHIFT),
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action_reg);
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}
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}
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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return 0;
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}
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void dcache_enable(void)
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{
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if (dcache_status()) /* return if cache already enabled */
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return;
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if (action_dcache_all(INVALIDATE_SET_WAY)) {
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printf("ERR: D-cache not enabled\n");
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return;
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}
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setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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void dcache_disable(void)
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{
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if (!dcache_status())
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return;
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/* if dcache is enabled-> dcache disable & then flush */
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if (action_dcache_all(FLUSH_SET_WAY)) {
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printf("ERR: D-cache not flushed\n");
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return;
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}
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clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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int dcache_status(void)
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{
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return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (action_cache_range(INVALIDATE_POC, start, stop - start)) {
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printf("ERR: D-cache not invalidated\n");
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return;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (action_cache_range(FLUSH_POC, start, stop - start)) {
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printf("ERR: D-cache not flushed\n");
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return;
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}
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}
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#else
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void dcache_enable(void)
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{
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return;
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}
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void dcache_disable(void)
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{
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return;
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}
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int dcache_status(void)
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{
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return 0;
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}
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#endif
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#ifndef CONFIG_SYS_ICACHE_OFF
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void invalidate_icache_all(void)
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{
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writel(INVAL_ICACHE_POU, V7M_CACHE_REG_ICIALLU);
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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void icache_enable(void)
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{
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if (icache_status())
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return;
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invalidate_icache_all();
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setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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int icache_status(void)
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{
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return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
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}
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void icache_disable(void)
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{
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if (!icache_status())
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return;
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isb(); /* flush pipeline */
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clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
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isb(); /* subsequent instructions fetch see cache disable effect */
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}
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#else
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void icache_enable(void)
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{
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return;
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}
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void icache_disable(void)
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{
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return;
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}
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int icache_status(void)
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{
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return 0;
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}
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#endif
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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@ -16,8 +16,15 @@
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.thumb
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#endif
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#define V7M_SCB_BASE 0xE000ED00
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#define V7M_MPU_BASE 0xE000ED90
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/* armv7m fixed base addresses */
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#define V7M_SCS_BASE 0xE000E000
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#define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100)
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#define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00)
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#define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78)
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#define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90)
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#define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30)
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#define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50)
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#define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90)
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#define V7M_SCB_VTOR 0x08
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@ -27,6 +34,18 @@ struct v7m_scb {
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uint32_t icsr; /* Interrupt Control and State Register */
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uint32_t vtor; /* Vector Table Offset Register */
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uint32_t aircr; /* App Interrupt and Reset Control Register */
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uint32_t scr; /* offset 0x10: System Control Register */
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uint32_t ccr; /* offset 0x14: Config and Control Register */
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uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
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uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
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uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
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uint32_t shcrs; /* offset 0x24: System Handler Control State */
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uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
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uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
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uint32_t res; /* offset 0x30: reserved */
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uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
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uint32_t bfar; /* offset 0x38: BusFault Address Reg */
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uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */
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};
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#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE)
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@ -39,6 +58,9 @@ struct v7m_scb {
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#define V7M_ICSR_VECTACT_MSK 0xFF
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#define V7M_CCR_DCACHE 16
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#define V7M_CCR_ICACHE 17
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struct v7m_mpu {
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uint32_t type; /* Type Register */
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uint32_t ctrl; /* Control Register */
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@ -55,8 +55,10 @@ endif
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obj-y += cache.o
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ifndef CONFIG_ARM64
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ifndef CONFIG_CPU_V7M
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obj-y += cache-cp15.o
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endif
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endif
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obj-y += psci-dt.o
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