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armv8: fsl-layerscape: Add back L3 flushing for all exception levels

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CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
This commit is contained in:
York Sun 2017-09-08 09:33:49 -07:00
parent 4950eb4a48
commit 42f43aa258
1 changed files with 0 additions and 4 deletions
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4
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
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@ -396,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache)
mov x29, lr
mov x8, #0
switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
@ -416,7 +413,6 @@ ENTRY(__asm_flush_l3_dcache)
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
100:
1:
mov x0, x8
mov lr, x29