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https://github.com/AsahiLinux/u-boot
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serial: lpuart: restructure lpuart driver
Drop CONFIG_LPUART_32B_REG. Move the register structure to a common file include/fsl_lpuart.h Define lpuart_serial_platdata structure which includes the reg base and flags. For 32Bit register access, use lpuart_read32/lpuart_write32 which handles big/little endian. For 8Bit register access, still use the orignal code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
7ee3f149fe
commit
c40d612b1a
6 changed files with 153 additions and 240 deletions
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@ -204,6 +204,11 @@ static u32 get_dspi_clk(void)
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return get_ipg_clk();
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}
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u32 get_lpuart_clk(void)
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{
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return get_uart_clk();
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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@ -10,46 +10,4 @@
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#define I2C_QUIRK_REG /* enable 8-bit driver */
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#ifdef CONFIG_FSL_LPUART
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#ifdef CONFIG_LPUART_32B_REG
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struct lpuart_fsl {
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u32 baud;
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u32 stat;
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u32 ctrl;
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u32 data;
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u32 match;
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u32 modir;
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u32 fifo;
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u32 water;
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};
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#else
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struct lpuart_fsl {
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u8 ubdh;
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u8 ubdl;
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u8 uc1;
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u8 uc2;
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u8 us1;
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u8 us2;
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u8 uc3;
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u8 ud;
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u8 uma1;
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u8 uma2;
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u8 uc4;
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u8 uc5;
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u8 ued;
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u8 umodem;
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u8 uir;
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u8 reserved;
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u8 upfifo;
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u8 ucfifo;
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u8 usfifo;
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u8 utwfifo;
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u8 utcfifo;
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u8 urwfifo;
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u8 urcfifo;
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u8 rsvd[28];
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};
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#endif
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#endif /* CONFIG_FSL_LPUART */
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#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
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@ -10,44 +10,4 @@
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#define I2C_QUIRK_REG /* enable 8-bit driver */
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#ifdef CONFIG_LPUART_32B_REG
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struct lpuart_fsl {
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u32 baud;
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u32 stat;
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u32 ctrl;
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u32 data;
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u32 match;
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u32 modir;
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u32 fifo;
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u32 water;
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};
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#else
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struct lpuart_fsl {
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u8 ubdh;
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u8 ubdl;
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u8 uc1;
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u8 uc2;
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u8 us1;
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u8 us2;
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u8 uc3;
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u8 ud;
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u8 uma1;
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u8 uma2;
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u8 uc4;
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u8 uc5;
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u8 ued;
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u8 umodem;
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u8 uir;
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u8 reserved;
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u8 upfifo;
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u8 ucfifo;
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u8 usfifo;
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u8 utwfifo;
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u8 utcfifo;
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u8 urwfifo;
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u8 urcfifo;
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u8 rsvd[28];
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};
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#endif
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#endif /* __ASM_ARCH_IMX_REGS_H__ */
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@ -22,6 +22,7 @@ enum mxc_clock {
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void enable_ocotp_clk(unsigned char enable);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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u32 get_lpuart_clk(void);
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#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
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@ -429,34 +429,6 @@ struct fuse_bank4_regs {
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u32 rsvd7[3];
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};
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/* UART */
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struct lpuart_fsl {
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u8 ubdh;
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u8 ubdl;
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u8 uc1;
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u8 uc2;
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u8 us1;
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u8 us2;
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u8 uc3;
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u8 ud;
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u8 uma1;
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u8 uma2;
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u8 uc4;
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u8 uc5;
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u8 ued;
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u8 umodem;
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u8 uir;
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u8 reserved;
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u8 upfifo;
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u8 ucfifo;
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u8 usfifo;
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u8 utwfifo;
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u8 utcfifo;
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u8 urwfifo;
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u8 urcfifo;
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u8 rsvd[28];
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};
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/* MSCM Interrupt Router */
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struct mscm_ir {
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u32 ircp0ir;
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@ -6,6 +6,7 @@
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#include <common.h>
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#include <dm.h>
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#include <fsl_lpuart.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <serial.h>
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@ -48,14 +49,56 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
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#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
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struct lpuart_serial_platdata {
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struct lpuart_fsl *reg;
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void *reg;
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ulong flags;
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};
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#ifndef CONFIG_LPUART_32B_REG
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static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
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static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
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{
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u32 clk = mxc_get_clock(MXC_UART_CLK);
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if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
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if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
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*(u32 *)val = in_be32(addr);
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else
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*(u32 *)val = in_le32(addr);
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}
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}
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static void lpuart_write32(u32 flags, u32 *addr, u32 val)
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{
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if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
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if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
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out_be32(addr, val);
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else
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out_le32(addr, val);
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}
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}
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 0
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#endif
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u32 __weak get_lpuart_clk(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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static bool is_lpuart32(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
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}
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static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
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int baudrate)
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{
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struct lpuart_fsl *base = plat->reg;
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u32 clk = get_lpuart_clk();
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u16 sbr;
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sbr = (u16)(clk / (16 * baudrate));
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@ -65,8 +108,9 @@ static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
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__raw_writeb(sbr & 0xff, &base->ubdl);
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}
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static int _lpuart_serial_getc(struct lpuart_fsl *base)
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static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl *base = plat->reg;
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while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
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WATCHDOG_RESET();
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@ -75,8 +119,11 @@ static int _lpuart_serial_getc(struct lpuart_fsl *base)
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return __raw_readb(&base->ud);
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}
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static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
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static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
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const char c)
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{
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struct lpuart_fsl *base = plat->reg;
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while (!(__raw_readb(&base->us1) & US1_TDRE))
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WATCHDOG_RESET();
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@ -84,8 +131,10 @@ static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
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}
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/* Test whether a character is in the RX buffer */
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static int _lpuart_serial_tstc(struct lpuart_fsl *base)
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static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl *base = plat->reg;
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if (__raw_readb(&base->urcfifo) == 0)
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return 0;
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@ -96,8 +145,9 @@ static int _lpuart_serial_tstc(struct lpuart_fsl *base)
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int _lpuart_serial_init(struct lpuart_fsl *base)
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static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
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u8 ctrl;
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ctrl = __raw_readb(&base->uc2);
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@ -115,101 +165,71 @@ static int _lpuart_serial_init(struct lpuart_fsl *base)
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__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
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/* provide data bits, parity, stop bit, etc */
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_lpuart_serial_setbrg(base, gd->baudrate);
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_lpuart_serial_setbrg(plat, gd->baudrate);
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__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
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return 0;
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}
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static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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_lpuart_serial_setbrg(reg, baudrate);
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return 0;
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}
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static int lpuart_serial_getc(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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return _lpuart_serial_getc(reg);
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}
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static int lpuart_serial_putc(struct udevice *dev, const char c)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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_lpuart_serial_putc(reg, c);
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return 0;
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}
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static int lpuart_serial_pending(struct udevice *dev, bool input)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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if (input)
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return _lpuart_serial_tstc(reg);
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else
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return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
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}
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static int lpuart_serial_probe(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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return _lpuart_serial_init(reg);
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}
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#else
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u32 __weak get_lpuart_clk(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
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static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
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int baudrate)
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{
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 clk = get_lpuart_clk();
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u32 sbr;
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sbr = (clk / (16 * baudrate));
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/* place adjustment later - n/32 BRFA */
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out_be32(&base->baud, sbr);
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lpuart_write32(plat->flags, &base->baud, sbr);
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}
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static int _lpuart32_serial_getc(struct lpuart_fsl *base)
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static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
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{
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 stat;
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while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
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out_be32(&base->stat, STAT_FLAGS);
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lpuart_read32(plat->flags, &base->stat, &stat);
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while ((stat & STAT_RDRF) == 0) {
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lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
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WATCHDOG_RESET();
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lpuart_read32(plat->flags, &base->stat, &stat);
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}
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/* Reuse stat */
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lpuart_read32(plat->flags, &base->data, &stat);
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return stat & 0x3ff;
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}
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static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
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const char c)
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{
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 stat;
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while (true) {
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lpuart_read32(plat->flags, &base->stat, &stat);
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if ((stat & STAT_TDRE))
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break;
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WATCHDOG_RESET();
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}
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return in_be32(&base->data) & 0x3ff;
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}
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static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
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{
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while (!(in_be32(&base->stat) & STAT_TDRE))
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WATCHDOG_RESET();
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out_be32(&base->data, c);
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lpuart_write32(plat->flags, &base->data, c);
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}
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/* Test whether a character is in the RX buffer */
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static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
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static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
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{
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if ((in_be32(&base->water) >> 24) == 0)
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struct lpuart_fsl_reg32 *base = plat->reg;
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u32 water;
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lpuart_read32(plat->flags, &base->water, &water);
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if ((water >> 24) == 0)
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return 0;
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return 1;
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@ -219,75 +239,94 @@ static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int _lpuart32_serial_init(struct lpuart_fsl *base)
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static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
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{
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u8 ctrl;
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struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
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u32 ctrl;
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ctrl = in_be32(&base->ctrl);
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lpuart_read32(plat->flags, &base->ctrl, &ctrl);
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ctrl &= ~CTRL_RE;
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ctrl &= ~CTRL_TE;
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out_be32(&base->ctrl, ctrl);
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lpuart_write32(plat->flags, &base->ctrl, ctrl);
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out_be32(&base->modir, 0);
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out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
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lpuart_write32(plat->flags, &base->modir, 0);
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lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
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out_be32(&base->match, 0);
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lpuart_write32(plat->flags, &base->match, 0);
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/* provide data bits, parity, stop bit, etc */
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_lpuart32_serial_setbrg(base, gd->baudrate);
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_lpuart32_serial_setbrg(plat, gd->baudrate);
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out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
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lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
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return 0;
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}
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static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
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static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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_lpuart32_serial_setbrg(reg, baudrate);
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if (is_lpuart32(dev))
|
||||
_lpuart32_serial_setbrg(plat, baudrate);
|
||||
else
|
||||
_lpuart_serial_setbrg(plat, baudrate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpuart32_serial_getc(struct udevice *dev)
|
||||
static int lpuart_serial_getc(struct udevice *dev)
|
||||
{
|
||||
struct lpuart_serial_platdata *plat = dev->platdata;
|
||||
struct lpuart_fsl *reg = plat->reg;
|
||||
|
||||
return _lpuart32_serial_getc(reg);
|
||||
if (is_lpuart32(dev))
|
||||
return _lpuart32_serial_getc(plat);
|
||||
|
||||
return _lpuart_serial_getc(plat);
|
||||
}
|
||||
|
||||
static int lpuart32_serial_putc(struct udevice *dev, const char c)
|
||||
static int lpuart_serial_putc(struct udevice *dev, const char c)
|
||||
{
|
||||
struct lpuart_serial_platdata *plat = dev->platdata;
|
||||
struct lpuart_fsl *reg = plat->reg;
|
||||
|
||||
_lpuart32_serial_putc(reg, c);
|
||||
if (is_lpuart32(dev))
|
||||
_lpuart32_serial_putc(plat, c);
|
||||
else
|
||||
_lpuart_serial_putc(plat, c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpuart32_serial_pending(struct udevice *dev, bool input)
|
||||
static int lpuart_serial_pending(struct udevice *dev, bool input)
|
||||
{
|
||||
struct lpuart_serial_platdata *plat = dev->platdata;
|
||||
struct lpuart_fsl *reg = plat->reg;
|
||||
struct lpuart_fsl_reg32 *reg32 = plat->reg;
|
||||
u32 stat;
|
||||
|
||||
if (is_lpuart32(dev)) {
|
||||
if (input) {
|
||||
return _lpuart32_serial_tstc(plat);
|
||||
} else {
|
||||
lpuart_read32(plat->flags, ®32->stat, &stat);
|
||||
return stat & STAT_TDRE ? 0 : 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (input)
|
||||
return _lpuart32_serial_tstc(reg);
|
||||
return _lpuart_serial_tstc(plat);
|
||||
else
|
||||
return in_be32(®->stat) & STAT_TDRE ? 0 : 1;
|
||||
return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
|
||||
}
|
||||
|
||||
static int lpuart32_serial_probe(struct udevice *dev)
|
||||
static int lpuart_serial_probe(struct udevice *dev)
|
||||
{
|
||||
struct lpuart_serial_platdata *plat = dev->platdata;
|
||||
struct lpuart_fsl *reg = plat->reg;
|
||||
|
||||
return _lpuart32_serial_init(reg);
|
||||
if (is_lpuart32(dev))
|
||||
return _lpuart32_serial_init(plat);
|
||||
else
|
||||
return _lpuart_serial_init(plat);
|
||||
}
|
||||
#endif /* CONFIG_LPUART_32B_REG */
|
||||
|
||||
static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
|
|
@ -298,12 +337,12 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
|
|||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
plat->reg = (struct lpuart_fsl *)addr;
|
||||
plat->reg = (void *)addr;
|
||||
plat->flags = dev_get_driver_data(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_LPUART_32B_REG
|
||||
static const struct dm_serial_ops lpuart_serial_ops = {
|
||||
.putc = lpuart_serial_putc,
|
||||
.pending = lpuart_serial_pending,
|
||||
|
|
@ -312,7 +351,9 @@ static const struct dm_serial_ops lpuart_serial_ops = {
|
|||
};
|
||||
|
||||
static const struct udevice_id lpuart_serial_ids[] = {
|
||||
{ .compatible = "fsl,vf610-lpuart" },
|
||||
{ .compatible = "fsl,ls1021a-lpuart", .data =
|
||||
LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
|
||||
{ .compatible = "fsl,vf610-lpuart"},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -326,27 +367,3 @@ U_BOOT_DRIVER(serial_lpuart) = {
|
|||
.ops = &lpuart_serial_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
#else /* CONFIG_LPUART_32B_REG */
|
||||
static const struct dm_serial_ops lpuart32_serial_ops = {
|
||||
.putc = lpuart32_serial_putc,
|
||||
.pending = lpuart32_serial_pending,
|
||||
.getc = lpuart32_serial_getc,
|
||||
.setbrg = lpuart32_serial_setbrg,
|
||||
};
|
||||
|
||||
static const struct udevice_id lpuart32_serial_ids[] = {
|
||||
{ .compatible = "fsl,ls1021a-lpuart" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(serial_lpuart32) = {
|
||||
.name = "serial_lpuart32",
|
||||
.id = UCLASS_SERIAL,
|
||||
.of_match = lpuart32_serial_ids,
|
||||
.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
|
||||
.probe = lpuart32_serial_probe,
|
||||
.ops = &lpuart32_serial_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
#endif /* CONFIG_LPUART_32B_REG */
|
||||
|
|
|
|||
Loading…
Reference in a new issue