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arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support
Boot Log for i.CoreM6 DualLite/Solo Starter Kit: ----------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR DRAM: 256 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device switch to partitions #0, OK mmc0 is current device reading boot.scr ** Unable to read file boot.scr ** reading zImage 6741808 bytes read in 341 ms (18.9 MiB/s) Booting from mmc ... reading imx6dl-icore.dtb 30600 bytes read in 19 ms (1.5 MiB/s) Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800a787 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 Boot Log for i.CoreM6 Quad/Dual Starter Kit: -------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6Q rev1.2 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Reset cause: POR DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
Stefano Babic
parent
d259c00845
commit
f4b7532f82
9 changed files with 620 additions and 0 deletions
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@ -95,6 +95,13 @@ config TARGET_MX6CUBOXI
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config TARGET_MX6QARM2
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bool "mx6qarm2"
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config TARGET_MX6Q_ICORE
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bool "Support Engicam i.Core"
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select MX6QDL
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select DM
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select DM_THERMAL
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select SUPPORT_SPL
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config TARGET_MX6QSABREAUTO
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bool "mx6qsabreauto"
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select DM
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@ -225,6 +232,7 @@ source "board/compulab/cm_fx6/Kconfig"
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source "board/congatec/cgtqmx6eval/Kconfig"
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source "board/el/el6x/Kconfig"
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source "board/embest/mx6boards/Kconfig"
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source "board/engicam/icorem6/Kconfig"
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source "board/freescale/mx6qarm2/Kconfig"
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source "board/freescale/mx6qsabreauto/Kconfig"
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source "board/freescale/mx6sabresd/Kconfig"
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@ -30,8 +30,10 @@
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#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
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#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
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#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
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#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
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#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
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#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
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12
board/engicam/icorem6/Kconfig
Normal file
12
board/engicam/icorem6/Kconfig
Normal file
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@ -0,0 +1,12 @@
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if TARGET_MX6Q_ICORE
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config SYS_BOARD
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default "icorem6"
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config SYS_VENDOR
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default "engicam"
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config SYS_CONFIG_NAME
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default "imx6qdl_icore"
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endif
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6
board/engicam/icorem6/MAINTAINERS
Normal file
6
board/engicam/icorem6/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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ICOREM6QDL BOARD
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M: Jagan Teki <jagan@amarulasolutions.com>
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S: Maintained
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F: board/engicam/icorem6
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F: include/configs/icorem6qdl.h
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F: configs/icorem6qdl_defconfig
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6
board/engicam/icorem6/Makefile
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6
board/engicam/icorem6/Makefile
Normal file
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@ -0,0 +1,6 @@
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# Copyright (C) 2016 Amarula Solutions B.V.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := icorem6.o
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31
board/engicam/icorem6/README
Normal file
31
board/engicam/icorem6/README
Normal file
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@ -0,0 +1,31 @@
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How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
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-----------------------------------------------------------------------------
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- Build U-Boot for Engicam i.CoreM6 QDL:
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$ make mrproper
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$ make icorem6qdl_mmc_defconfig
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$ make
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This will generate the SPL image called SPL and the u-boot.img.
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- Flash the SPL image into the micro SD card:
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sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
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- Flash the u-boot.img image into the micro SD card:
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sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
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- Jumper settings:
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MMC Boot: JM3 Closed
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- Connect the Serial cable between the Starter Kit and the PC for the console.
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(J28 is the Linux Serial console connector)
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- Insert the micro SD card in the board, power it up and U-Boot messages should
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come up.
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- Note: For loading Linux on Quad/Dual modules set the dtb as
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icorem6qdl> setenv fdt_file imx6q-icore.dtb
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400
board/engicam/icorem6/icorem6.c
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400
board/engicam/icorem6/icorem6.c
Normal file
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@ -0,0 +1,400 @@
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/iomux-v3.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart4_pads[] = {
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
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};
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#ifdef CONFIG_FSL_ESDHC
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC1_BASE_ADDR, 0, 4},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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SETUP_IOMUX_PADS(usdhc1_pads);
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gpio_direction_input(USDHC1_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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default:
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printf("Warning - USDHC%d controller not supporting\n",
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i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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SETUP_IOMUX_PADS(uart4_pads);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <libfdt.h>
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#include <spl.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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/*
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* Driving strength:
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* 0x30 == 40 Ohm
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* 0x28 == 48 Ohm
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*/
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_sdqs0 = 0x28,
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.dram_sdqs1 = 0x28,
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.dram_sdqs2 = 0x28,
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.dram_sdqs3 = 0x28,
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.dram_sdqs4 = 0x28,
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.dram_sdqs5 = 0x28,
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.dram_sdqs6 = 0x28,
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.dram_sdqs7 = 0x28,
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.dram_dqm0 = 0x28,
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.dram_dqm1 = 0x28,
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.dram_dqm2 = 0x28,
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.dram_dqm3 = 0x28,
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.dram_dqm4 = 0x28,
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.dram_dqm5 = 0x28,
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.dram_dqm6 = 0x28,
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.dram_dqm7 = 0x28,
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.dram_cas = 0x30,
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.dram_ras = 0x30,
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.dram_sdclk_0 = 0x30,
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.dram_sdclk_1 = 0x30,
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.dram_reset = 0x30,
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.dram_sdcke0 = 0x3000,
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.dram_sdcke1 = 0x3000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x30,
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.dram_sdodt1 = 0x30,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_b0ds = 0x30,
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.grp_b1ds = 0x30,
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.grp_b2ds = 0x30,
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.grp_b3ds = 0x30,
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.grp_b4ds = 0x30,
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.grp_b5ds = 0x30,
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.grp_b6ds = 0x30,
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.grp_b7ds = 0x30,
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.grp_addds = 0x30,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ctlds = 0x30,
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.grp_ddr_type = 0x000c0000,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = 0x30,
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.dram_sdclk_1 = 0x30,
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.dram_cas = 0x30,
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.dram_ras = 0x30,
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.dram_reset = 0x30,
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.dram_sdcke0 = 0x30,
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.dram_sdcke1 = 0x30,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x30,
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.dram_sdodt1 = 0x30,
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.dram_sdqs0 = 0x28,
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.dram_sdqs1 = 0x28,
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.dram_sdqs2 = 0x28,
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.dram_sdqs3 = 0x28,
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.dram_sdqs4 = 0x28,
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.dram_sdqs5 = 0x28,
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.dram_sdqs6 = 0x28,
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.dram_sdqs7 = 0x28,
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.dram_dqm0 = 0x28,
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.dram_dqm1 = 0x28,
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.dram_dqm2 = 0x28,
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.dram_dqm3 = 0x28,
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.dram_dqm4 = 0x28,
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.dram_dqm5 = 0x28,
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.dram_dqm6 = 0x28,
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.dram_dqm7 = 0x28,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x30,
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.grp_ctlds = 0x30,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x28,
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.grp_b1ds = 0x28,
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.grp_b2ds = 0x28,
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.grp_b3ds = 0x28,
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.grp_b4ds = 0x28,
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.grp_b5ds = 0x28,
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.grp_b6ds = 0x28,
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.grp_b7ds = 0x28,
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};
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/* mt41j256 */
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static struct mx6_ddr3_cfg mt41j256 = {
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.mem_speed = 1066,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 0,
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};
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static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
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.p0_mpwldectrl0 = 0x000E0009,
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.p0_mpwldectrl1 = 0x0018000E,
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.p1_mpwldectrl0 = 0x00000007,
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.p1_mpwldectrl1 = 0x00000000,
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.p0_mpdgctrl0 = 0x43280334,
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.p0_mpdgctrl1 = 0x031C0314,
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.p1_mpdgctrl0 = 0x4318031C,
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.p1_mpdgctrl1 = 0x030C0258,
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.p0_mprddlctl = 0x3E343A40,
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.p1_mprddlctl = 0x383C3844,
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.p0_mpwrdlctl = 0x40404440,
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.p1_mpwrdlctl = 0x4C3E4446,
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};
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/* DDR 64bit */
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static struct mx6_ddr_sysinfo mem_q = {
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.ddr_type = DDR_TYPE_DDR3,
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.dsize = 2,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 2,
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.rtt_wr = 2,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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};
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||||
|
||||
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
|
||||
.p0_mpwldectrl0 = 0x001F0024,
|
||||
.p0_mpwldectrl1 = 0x00110018,
|
||||
.p1_mpwldectrl0 = 0x001F0024,
|
||||
.p1_mpwldectrl1 = 0x00110018,
|
||||
.p0_mpdgctrl0 = 0x4230022C,
|
||||
.p0_mpdgctrl1 = 0x02180220,
|
||||
.p1_mpdgctrl0 = 0x42440248,
|
||||
.p1_mpdgctrl1 = 0x02300238,
|
||||
.p0_mprddlctl = 0x44444A48,
|
||||
.p1_mprddlctl = 0x46484A42,
|
||||
.p0_mpwrdlctl = 0x38383234,
|
||||
.p1_mpwrdlctl = 0x3C34362E,
|
||||
};
|
||||
|
||||
/* DDR 64bit 1GB */
|
||||
static struct mx6_ddr_sysinfo mem_dl = {
|
||||
.dsize = 2,
|
||||
.cs1_mirror = 0,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32,
|
||||
.ncs = 1,
|
||||
.bi_on = 1,
|
||||
.rtt_nom = 1,
|
||||
.rtt_wr = 1,
|
||||
.ralat = 5,
|
||||
.walat = 0,
|
||||
.mif3_mode = 3,
|
||||
.rst_to_cke = 0x23,
|
||||
.sde_to_rst = 0x10,
|
||||
};
|
||||
|
||||
/* DDR 32bit 512MB */
|
||||
static struct mx6_ddr_sysinfo mem_s = {
|
||||
.dsize = 1,
|
||||
.cs1_mirror = 0,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32,
|
||||
.ncs = 1,
|
||||
.bi_on = 1,
|
||||
.rtt_nom = 1,
|
||||
.rtt_wr = 1,
|
||||
.ralat = 5,
|
||||
.walat = 0,
|
||||
.mif3_mode = 3,
|
||||
.rst_to_cke = 0x23,
|
||||
.sde_to_rst = 0x10,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0x00003F3F, &ccm->CCGR0);
|
||||
writel(0x0030FC00, &ccm->CCGR1);
|
||||
writel(0x000FC000, &ccm->CCGR2);
|
||||
writel(0x3F300000, &ccm->CCGR3);
|
||||
writel(0xFF00F300, &ccm->CCGR4);
|
||||
writel(0x0F0000C3, &ccm->CCGR5);
|
||||
writel(0x000003CC, &ccm->CCGR6);
|
||||
}
|
||||
|
||||
static void gpr_init(void)
|
||||
{
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
writel(0xF00000CF, &iomux->gpr[4]);
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
writel(0x007F007F, &iomux->gpr[6]);
|
||||
writel(0x007F007F, &iomux->gpr[7]);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
if (is_mx6solo()) {
|
||||
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
||||
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
|
||||
} else if (is_mx6dl()) {
|
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
||||
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
|
||||
} else if (is_mx6dq()) {
|
||||
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
|
||||
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
|
||||
}
|
||||
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
ccgr_init();
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
gpr_init();
|
||||
|
||||
/* iomux */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
||||
35
configs/imx6qdl_icore_mmc_defconfig
Normal file
35
configs/imx6qdl_icore_mmc_defconfig
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6Q_ICORE=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
|
||||
CONFIG_SYS_PROMPT="icorem6qdl> "
|
||||
CONFIG_SPL=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_SPL_EXT_SUPPORT=y
|
||||
120
include/configs/imx6qdl_icore.h
Normal file
120
include/configs/imx6qdl_icore.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
*
|
||||
* Configuration settings for the Engicam i.CoreM6 QDL Starter Kits.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IMX6QLD_ICORE_CONFIG_H
|
||||
#define __IMX6QLD_ICORE_CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
/* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE SZ_128K
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Environment */
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
/* Environment in MMC */
|
||||
# if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
# define CONFIG_ENV_OFFSET 0x100000
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Default environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* UART */
|
||||
#ifdef CONFIG_MXC_UART
|
||||
# define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
# define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL
|
||||
# define CONFIG_SPL_MMC_SUPPORT
|
||||
# include "imx6_spl.h"
|
||||
#endif
|
||||
|
||||
#endif /* __IMX6QLD_ICORE_CONFIG_H */
|
||||
Loading…
Reference in a new issue