mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Merge git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
Tom Rini
commit
0675f992db
123 changed files with 2844 additions and 979 deletions
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@ -844,6 +844,7 @@ config TARGET_LS1046ARDB
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select ARMV8_MULTIENTRY
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select SUPPORT_SPL
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select DM_SPI_FLASH if DM_SPI
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select POWER_MC34VR500
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help
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||||
Support for Freescale LS1046ARDB platform.
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||||
The LS1046A Reference Design Board (RDB) is a high-performance
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||||
|
|
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@ -18,6 +18,14 @@ config ARCH_LS1021A
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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config FSL_PCIE_COMPAT
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string "PCIe compatible of Kernel DT"
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depends on PCIE_LAYERSCAPE
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default "fsl,ls1021a-pcie" if ARCH_LS1021A
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help
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This compatible is used to find pci controller node in Kernel DT
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to complete fixup.
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config LS1_DEEP_SLEEP
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bool "Deep sleep"
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depends on ARCH_LS1021A
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@ -3,6 +3,24 @@ if ARM64
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config ARMV8_MULTIENTRY
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bool "Enable multiple CPUs to enter into U-Boot"
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config ARMV8_SET_SMPEN
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bool "Enable data coherency with other cores in cluster"
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help
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Say Y here if there is not any trust firmware to set
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CPUECTLR_EL1.SMPEN bit before U-Boot.
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For A53, it enables data coherency with other cores in the
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cluster, and for A57/A72, it enables receiving of instruction
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cache and TLB maintenance operations.
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Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
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for single core systems. Unfortunately write access to this
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register may be controlled by EL3/EL2 firmware. To be more
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precise, by default (if there is EL2/EL3 firmware running)
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this register is RO for NS EL1.
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This switch can be used to avoid writing to CPUECTLR_EL1,
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it can be safely enabled when EL2/EL3 initialized SMPEN bit
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or when CPU implementation doesn't include that register.
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config ARMV8_SPIN_TABLE
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bool "Support spin-table enable method"
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depends on ARMV8_MULTIENTRY && OF_LIBFDT
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@ -21,6 +39,47 @@ config ARMV8_SPIN_TABLE
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- Reserve the code for the spin-table and the release address
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via a /memreserve/ region in the Device Tree.
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menu "ARMv8 secure monitor firmware"
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config ARMV8_SEC_FIRMWARE_SUPPORT
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bool "Enable ARMv8 secure monitor firmware framework support"
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select OF_LIBFDT
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select FIT
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help
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This framework is aimed at making secure monitor firmware load
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process brief.
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Note: Only FIT format image is supported.
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You should prepare and provide the below information:
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- Address of secure firmware.
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- Address to hold the return address from secure firmware.
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- Secure firmware FIT image related information.
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Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
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- The target exception level that secure monitor firmware will
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return to.
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config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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bool "Enable ARMv8 secure monitor firmware framework support for SPL"
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select SPL_OF_LIBFDT
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select SPL_FIT
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help
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Say Y here to support this framework in SPL phase.
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config SEC_FIRMWARE_ARMV8_PSCI
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bool "PSCI implementation in secure monitor firmware"
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depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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help
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This config enables the ARMv8 PSCI implementation in secure monitor
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firmware. This is a private PSCI implementation and different from
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those implemented under the common ARMv8 PSCI framework.
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config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
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bool "ARMv8 secure monitor firmware ERET address byteorder swap"
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depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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help
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Say Y here when the endianness of the register or memory holding the
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Secure firmware exception return address is different with core's.
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endmenu
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config PSCI_RESET
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bool "Use PSCI for reset and shutdown"
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default y
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@ -19,7 +19,7 @@ obj-y += cpu-dt.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
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endif
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obj-$(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
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obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
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obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
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obj-$(CONFIG_S32V234) += s32v234/
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@ -14,7 +14,7 @@
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int psci_update_dt(void *fdt)
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{
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#ifdef CONFIG_MP
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#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
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#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
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#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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/*
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@ -1,5 +1,6 @@
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config ARCH_LS1012A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH2
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select SYS_FSL_DDR_BE
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select SYS_FSL_MMDC
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@ -7,6 +8,7 @@ config ARCH_LS1012A
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config ARCH_LS1043A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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@ -23,6 +25,7 @@ config ARCH_LS1043A
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config ARCH_LS1046A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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@ -38,6 +41,7 @@ config ARCH_LS1046A
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config ARCH_LS2080A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH3
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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@ -75,25 +79,60 @@ config FSL_LSCH3
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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config FSL_PCIE_COMPAT
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string "PCIe compatible of Kernel DT"
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depends on PCIE_LAYERSCAPE
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default "fsl,ls1012a-pcie" if ARCH_LS1012A
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default "fsl,ls1043a-pcie" if ARCH_LS1043A
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default "fsl,ls1046a-pcie" if ARCH_LS1046A
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default "fsl,ls2080a-pcie" if ARCH_LS2080A
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help
|
||||
This compatible is used to find pci controller node in Kernel DT
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to complete fixup.
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config HAS_FEATURE_GIC64K_ALIGN
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bool
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default y if ARCH_LS1043A
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config HAS_FEATURE_ENHANCED_MSI
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bool
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default y if ARCH_LS1043A
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menu "Layerscape PPA"
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config FSL_LS_PPA
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bool "FSL Layerscape PPA firmware support"
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depends on !ARMV8_PSCI
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depends on ARCH_LS1043A || ARCH_LS1046A
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select FSL_PPA_ARMV8_PSCI
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select ARMV8_SEC_FIRMWARE_SUPPORT
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select SEC_FIRMWARE_ARMV8_PSCI
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||||
select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
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||||
help
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||||
The FSL Primary Protected Application (PPA) is a software component
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||||
which is loaded during boot stage, and then remains resident in RAM
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||||
and runs in the TrustZone after boot.
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||||
Say y to enable it.
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||||
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||||
config FSL_PPA_ARMV8_PSCI
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bool "PSCI implementation in PPA firmware"
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choice
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prompt "FSL Layerscape PPA firmware loading-media select"
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depends on FSL_LS_PPA
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default SYS_LS_PPA_FW_IN_XIP
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config SYS_LS_PPA_FW_IN_XIP
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bool "XIP"
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help
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||||
This config enables the ARMv8 PSCI implementation in PPA firmware.
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This is a private PSCI implementation and different from those
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implemented under the common ARMv8 PSCI framework.
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Say Y here if the PPA firmware locate at XIP flash, such
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as NOR or QSPI flash.
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endchoice
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config SYS_LS_PPA_FW_ADDR
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hex "Address of PPA firmware loading from"
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depends on FSL_LS_PPA
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default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
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default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
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help
|
||||
If the PPA firmware locate at XIP flash, such as NOR or
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QSPI flash, this address is a directly memory-mapped.
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If it is in a serial accessed flash, such as NAND and SD
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card, it is a byte offset.
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endmenu
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config SYS_FSL_ERRATUM_A010315
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@ -116,7 +155,7 @@ config MAX_CPUS
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in spin table to properly handle all cores.
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||||
config SECURE_BOOT
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bool
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bool "Secure Boot"
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help
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Enable Freescale Secure Boot feature
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@ -148,6 +187,83 @@ config SYS_HAS_SERDES
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|||
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endmenu
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menu "Layerscape clock tree configuration"
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depends on FSL_LSCH2 || FSL_LSCH3
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config SYS_FSL_CLK
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bool "Enable clock tree initialization"
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default y
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config CLUSTER_CLK_FREQ
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int "Reference clock of core cluster"
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depends on ARCH_LS1012A
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default 100000000
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help
|
||||
This number is the reference clock frequency of core PLL.
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||||
For most platforms, the core PLL and Platform PLL have the same
|
||||
reference clock, but for some platforms, LS1012A for instance,
|
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they are provided sepatately.
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||||
config SYS_FSL_PCLK_DIV
|
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int "Platform clock divider"
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default 1 if ARCH_LS1043A
|
||||
default 1 if ARCH_LS1046A
|
||||
default 2
|
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help
|
||||
This is the divider that is used to derive Platform clock from
|
||||
Platform PLL, in another word:
|
||||
Platform_clk = Platform_PLL_freq / this_divider
|
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|
||||
config SYS_FSL_DSPI_CLK_DIV
|
||||
int "DSPI clock divider"
|
||||
default 1 if ARCH_LS1043A
|
||||
default 2
|
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help
|
||||
This is the divider that is used to derive DSPI clock from Platform
|
||||
PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
|
||||
|
||||
config SYS_FSL_DUART_CLK_DIV
|
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int "DUART clock divider"
|
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default 1 if ARCH_LS1043A
|
||||
default 2
|
||||
help
|
||||
This is the divider that is used to derive DUART clock from Platform
|
||||
clock, in another word DUART_clk = Platform_clk / this_divider.
|
||||
|
||||
config SYS_FSL_I2C_CLK_DIV
|
||||
int "I2C clock divider"
|
||||
default 1 if ARCH_LS1043A
|
||||
default 2
|
||||
help
|
||||
This is the divider that is used to derive I2C clock from Platform
|
||||
clock, in another word I2C_clk = Platform_clk / this_divider.
|
||||
|
||||
config SYS_FSL_IFC_CLK_DIV
|
||||
int "IFC clock divider"
|
||||
default 1 if ARCH_LS1043A
|
||||
default 2
|
||||
help
|
||||
This is the divider that is used to derive IFC clock from Platform
|
||||
clock, in another word IFC_clk = Platform_clk / this_divider.
|
||||
|
||||
config SYS_FSL_LPUART_CLK_DIV
|
||||
int "LPUART clock divider"
|
||||
default 1 if ARCH_LS1043A
|
||||
default 2
|
||||
help
|
||||
This is the divider that is used to derive LPUART clock from Platform
|
||||
clock, in another word LPUART_clk = Platform_clk / this_divider.
|
||||
|
||||
config SYS_FSL_SDHC_CLK_DIV
|
||||
int "SDHC clock divider"
|
||||
default 1 if ARCH_LS1043A
|
||||
default 1 if ARCH_LS1012A
|
||||
default 2
|
||||
help
|
||||
This is the divider that is used to derive SDHC clock from Platform
|
||||
clock, in another word SDHC_clk = Platform_clk / this_divider.
|
||||
endmenu
|
||||
|
||||
config SYS_FSL_ERRATUM_A008336
|
||||
bool
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ obj-y += soc.o
|
|||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-$(CONFIG_SPL) += spl.o
|
||||
obj-$(CONFIG_FSL_LS_PPA) += ppa.o
|
||||
obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
|
||||
|
||||
ifneq ($(CONFIG_FSL_LSCH3),)
|
||||
obj-y += fsl_lsch3_speed.o
|
||||
|
|
|
|||
|
|
@ -345,8 +345,9 @@ int print_cpuinfo(void)
|
|||
(type == TY_ITYP_VER_A72 ? "A72" : " "))),
|
||||
strmhz(buf, sysinfo.freq_processor[core]));
|
||||
}
|
||||
/* Display platform clock as Bus frequency. */
|
||||
printf("\n Bus: %-4s MHz ",
|
||||
strmhz(buf, sysinfo.freq_systembus));
|
||||
strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
|
||||
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
|
||||
|
|
@ -411,7 +412,7 @@ int arch_early_init_r(void)
|
|||
#endif
|
||||
#ifdef CONFIG_MP
|
||||
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
|
||||
defined(CONFIG_FSL_PPA_ARMV8_PSCI)
|
||||
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
|
||||
/* Check the psci version to determine if the psci is supported */
|
||||
psci_ver = sec_firmware_support_psci_version();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ void ft_fixup_cpu(void *blob)
|
|||
u64 val, core_id;
|
||||
size_t *boot_code_size = &(__secondary_boot_code_size);
|
||||
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
|
||||
defined(CONFIG_FSL_PPA_ARMV8_PSCI)
|
||||
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
|
||||
int node;
|
||||
u32 psci_ver;
|
||||
|
||||
|
|
@ -133,6 +133,218 @@ void fsl_fdt_disable_usb(void *blob)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
|
||||
static void fdt_fixup_gic(void *blob)
|
||||
{
|
||||
int offset, err;
|
||||
u64 reg[8];
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int val;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
int align_64k = 0;
|
||||
|
||||
val = gur_in32(&gur->svr);
|
||||
|
||||
if (SVR_SOC_VER(val) != SVR_LS1043A) {
|
||||
align_64k = 1;
|
||||
} else if (SVR_REV(val) != REV1_0) {
|
||||
val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
|
||||
if (!val)
|
||||
align_64k = 1;
|
||||
}
|
||||
|
||||
offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000");
|
||||
if (offset < 0) {
|
||||
printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
|
||||
"interrupt-controller@1400000", fdt_strerror(offset));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Fixup gic node align with 64K */
|
||||
if (align_64k) {
|
||||
reg[0] = cpu_to_fdt64(GICD_BASE_64K);
|
||||
reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
|
||||
reg[2] = cpu_to_fdt64(GICC_BASE_64K);
|
||||
reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
|
||||
reg[4] = cpu_to_fdt64(GICH_BASE_64K);
|
||||
reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
|
||||
reg[6] = cpu_to_fdt64(GICV_BASE_64K);
|
||||
reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
|
||||
} else {
|
||||
/* Fixup gic node align with default */
|
||||
reg[0] = cpu_to_fdt64(GICD_BASE);
|
||||
reg[1] = cpu_to_fdt64(GICD_SIZE);
|
||||
reg[2] = cpu_to_fdt64(GICC_BASE);
|
||||
reg[3] = cpu_to_fdt64(GICC_SIZE);
|
||||
reg[4] = cpu_to_fdt64(GICH_BASE);
|
||||
reg[5] = cpu_to_fdt64(GICH_SIZE);
|
||||
reg[6] = cpu_to_fdt64(GICV_BASE);
|
||||
reg[7] = cpu_to_fdt64(GICV_SIZE);
|
||||
}
|
||||
|
||||
err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
|
||||
if (err < 0) {
|
||||
printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
|
||||
"reg", "interrupt-controller@1400000",
|
||||
fdt_strerror(err));
|
||||
return;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
|
||||
static int _fdt_fixup_msi_node(void *blob, const char *name,
|
||||
int irq_0, int irq_1, int rev)
|
||||
{
|
||||
int err, offset, len;
|
||||
u32 tmp[4][3];
|
||||
void *p;
|
||||
|
||||
offset = fdt_path_offset(blob, name);
|
||||
if (offset < 0) {
|
||||
printf("WARNING: fdt_path_offset can't find path %s: %s\n",
|
||||
name, fdt_strerror(offset));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*fixup the property of interrupts*/
|
||||
|
||||
tmp[0][0] = cpu_to_fdt32(0x0);
|
||||
tmp[0][1] = cpu_to_fdt32(irq_0);
|
||||
tmp[0][2] = cpu_to_fdt32(0x4);
|
||||
|
||||
if (rev > REV1_0) {
|
||||
tmp[1][0] = cpu_to_fdt32(0x0);
|
||||
tmp[1][1] = cpu_to_fdt32(irq_1);
|
||||
tmp[1][2] = cpu_to_fdt32(0x4);
|
||||
tmp[2][0] = cpu_to_fdt32(0x0);
|
||||
tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
|
||||
tmp[2][2] = cpu_to_fdt32(0x4);
|
||||
tmp[3][0] = cpu_to_fdt32(0x0);
|
||||
tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
|
||||
tmp[3][2] = cpu_to_fdt32(0x4);
|
||||
len = sizeof(tmp);
|
||||
} else {
|
||||
len = sizeof(tmp[0]);
|
||||
}
|
||||
|
||||
err = fdt_setprop(blob, offset, "interrupts", tmp, len);
|
||||
if (err < 0) {
|
||||
printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
|
||||
"interrupts", name, fdt_strerror(err));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*fixup the property of reg*/
|
||||
p = (char *)fdt_getprop(blob, offset, "reg", &len);
|
||||
if (!p) {
|
||||
printf("WARNING: fdt_getprop can't get %s from node %s\n",
|
||||
"reg", name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
memcpy((char *)tmp, p, len);
|
||||
|
||||
if (rev > REV1_0)
|
||||
*((u32 *)tmp + 3) = cpu_to_fdt32(0x1000);
|
||||
else
|
||||
*((u32 *)tmp + 3) = cpu_to_fdt32(0x8);
|
||||
|
||||
err = fdt_setprop(blob, offset, "reg", tmp, len);
|
||||
if (err < 0) {
|
||||
printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
|
||||
"reg", name, fdt_strerror(err));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*fixup the property of compatible*/
|
||||
if (rev > REV1_0)
|
||||
err = fdt_setprop_string(blob, offset, "compatible",
|
||||
"fsl,ls1043a-v1.1-msi");
|
||||
else
|
||||
err = fdt_setprop_string(blob, offset, "compatible",
|
||||
"fsl,ls1043a-msi");
|
||||
if (err < 0) {
|
||||
printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
|
||||
"compatible", name, fdt_strerror(err));
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
|
||||
{
|
||||
int offset, len, err;
|
||||
void *p;
|
||||
int val;
|
||||
u32 tmp[4][8];
|
||||
|
||||
offset = fdt_path_offset(blob, name);
|
||||
if (offset < 0) {
|
||||
printf("WARNING: fdt_path_offset can't find path %s: %s\n",
|
||||
name, fdt_strerror(offset));
|
||||
return 0;
|
||||
}
|
||||
|
||||
p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len);
|
||||
if (!p || len != sizeof(tmp)) {
|
||||
printf("WARNING: fdt_getprop can't get %s from node %s\n",
|
||||
"interrupt-map", name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
memcpy((char *)tmp, p, len);
|
||||
|
||||
val = fdt32_to_cpu(tmp[0][6]);
|
||||
if (rev > REV1_0) {
|
||||
tmp[1][6] = cpu_to_fdt32(val + 1);
|
||||
tmp[2][6] = cpu_to_fdt32(val + 2);
|
||||
tmp[3][6] = cpu_to_fdt32(val + 3);
|
||||
} else {
|
||||
tmp[1][6] = cpu_to_fdt32(val);
|
||||
tmp[2][6] = cpu_to_fdt32(val);
|
||||
tmp[3][6] = cpu_to_fdt32(val);
|
||||
}
|
||||
|
||||
err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
|
||||
if (err < 0) {
|
||||
printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
|
||||
"interrupt-map", name, fdt_strerror(err));
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Fixup msi node for ls1043a rev1.1*/
|
||||
|
||||
static void fdt_fixup_msi(void *blob)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int rev;
|
||||
|
||||
rev = gur_in32(&gur->svr);
|
||||
|
||||
if (SVR_SOC_VER(rev) != SVR_LS1043A)
|
||||
return;
|
||||
|
||||
rev = SVR_REV(rev);
|
||||
|
||||
_fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000",
|
||||
116, 111, rev);
|
||||
_fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000",
|
||||
126, 121, rev);
|
||||
_fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000",
|
||||
160, 155, rev);
|
||||
|
||||
_fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev);
|
||||
_fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev);
|
||||
_fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev);
|
||||
}
|
||||
#endif
|
||||
|
||||
void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_FSL_LSCH2
|
||||
|
|
@ -177,4 +389,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
#endif
|
||||
fsl_fdt_disable_usb(blob);
|
||||
|
||||
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
|
||||
fdt_fixup_gic(blob);
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
|
||||
fdt_fixup_msi(blob);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -129,6 +129,278 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
|
|||
serdes_prtcl_map[NONE] = 1;
|
||||
}
|
||||
|
||||
__weak int get_serdes_volt(void)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
__weak int set_serdes_volt(int svdd)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int setup_serdes_volt(u32 svdd)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_serdes *serdes1_base;
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
struct ccsr_serdes *serdes2_base;
|
||||
#endif
|
||||
u32 cfg_rcw4 = gur_in32(&gur->rcwsr[4]);
|
||||
u32 cfg_rcw5 = gur_in32(&gur->rcwsr[5]);
|
||||
u32 cfg_tmp, reg = 0;
|
||||
int svdd_cur, svdd_tar;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Only support switch SVDD to 900mV/1000mV */
|
||||
if (svdd != 900 && svdd != 1000)
|
||||
return -EINVAL;
|
||||
|
||||
svdd_tar = svdd;
|
||||
svdd_cur = get_serdes_volt();
|
||||
if (svdd_cur < 0)
|
||||
return -EINVAL;
|
||||
|
||||
debug("%s: current SVDD: %dmV; target SVDD: %dmV\n",
|
||||
__func__, svdd_cur, svdd_tar);
|
||||
if (svdd_cur == svdd_tar)
|
||||
return 0;
|
||||
|
||||
serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes2_base = (void *)serdes1_base + 0x10000;
|
||||
#endif
|
||||
|
||||
/* Put the all enabled lanes in reset */
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
|
||||
reg = in_be32(&serdes1_base->lane[i].gcr0);
|
||||
reg &= 0xFF9FFFFF;
|
||||
out_be32(&serdes1_base->lane[i].gcr0, reg);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
|
||||
cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
|
||||
|
||||
for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
|
||||
reg = in_be32(&serdes2_base->lane[i].gcr0);
|
||||
reg &= 0xFF9FFFFF;
|
||||
out_be32(&serdes2_base->lane[i].gcr0, reg);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Put the all enabled PLL in reset */
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
|
||||
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg &= 0xFFFFFFBF;
|
||||
reg |= 0x10000000;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
udelay(1);
|
||||
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg &= 0xFFFFFF1F;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
}
|
||||
udelay(1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
|
||||
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg &= 0xFFFFFFBF;
|
||||
reg |= 0x10000000;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
udelay(1);
|
||||
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg &= 0xFFFFFF1F;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
}
|
||||
udelay(1);
|
||||
#endif
|
||||
|
||||
/* Put the Rx/Tx calibration into reset */
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
reg = in_be32(&serdes1_base->srdstcalcr);
|
||||
reg &= 0xF7FFFFFF;
|
||||
out_be32(&serdes1_base->srdstcalcr, reg);
|
||||
reg = in_be32(&serdes1_base->srdsrcalcr);
|
||||
reg &= 0xF7FFFFFF;
|
||||
out_be32(&serdes1_base->srdsrcalcr, reg);
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
reg = in_be32(&serdes2_base->srdstcalcr);
|
||||
reg &= 0xF7FFFFFF;
|
||||
out_be32(&serdes2_base->srdstcalcr, reg);
|
||||
reg = in_be32(&serdes2_base->srdsrcalcr);
|
||||
reg &= 0xF7FFFFFF;
|
||||
out_be32(&serdes2_base->srdsrcalcr, reg);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If SVDD set failed, will not return directly, so that the
|
||||
* serdes lanes can complete reseting.
|
||||
*/
|
||||
ret = set_serdes_volt(svdd_tar);
|
||||
if (ret)
|
||||
printf("%s: Failed to set SVDD\n", __func__);
|
||||
|
||||
/* Wait for SVDD to stabilize */
|
||||
udelay(100);
|
||||
|
||||
/* For each PLL that’s not disabled via RCW */
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
|
||||
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg |= 0x00000020;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
udelay(1);
|
||||
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg |= 0x00000080;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
|
||||
/* Take the Rx/Tx calibration out of reset */
|
||||
if (!(cfg_tmp == 0x3 && i == 1)) {
|
||||
udelay(1);
|
||||
reg = in_be32(&serdes1_base->srdstcalcr);
|
||||
reg |= 0x08000000;
|
||||
out_be32(&serdes1_base->srdstcalcr, reg);
|
||||
reg = in_be32(&serdes1_base->srdsrcalcr);
|
||||
reg |= 0x08000000;
|
||||
out_be32(&serdes1_base->srdsrcalcr, reg);
|
||||
}
|
||||
}
|
||||
udelay(1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
|
||||
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg |= 0x00000020;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
udelay(1);
|
||||
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg |= 0x00000080;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
|
||||
/* Take the Rx/Tx calibration out of reset */
|
||||
if (!(cfg_tmp == 0x3 && i == 1)) {
|
||||
udelay(1);
|
||||
reg = in_be32(&serdes2_base->srdstcalcr);
|
||||
reg |= 0x08000000;
|
||||
out_be32(&serdes2_base->srdstcalcr, reg);
|
||||
reg = in_be32(&serdes2_base->srdsrcalcr);
|
||||
reg |= 0x08000000;
|
||||
out_be32(&serdes2_base->srdsrcalcr, reg);
|
||||
}
|
||||
}
|
||||
udelay(1);
|
||||
|
||||
#endif
|
||||
|
||||
/* Wait for at lesat 625us to ensure the PLLs being reset are locked */
|
||||
udelay(800);
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
|
||||
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
|
||||
/* if the PLL is not locked, set RST_ERR */
|
||||
reg = in_be32(&serdes1_base->bank[i].pllcr0);
|
||||
if (!((reg >> 23) & 0x1)) {
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg |= 0x20000000;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
} else {
|
||||
udelay(1);
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg &= 0xFFFFFFEF;
|
||||
reg |= 0x00000040;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
|
||||
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
|
||||
reg = in_be32(&serdes2_base->bank[i].pllcr0);
|
||||
if (!((reg >> 23) & 0x1)) {
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg |= 0x20000000;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
} else {
|
||||
udelay(1);
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg &= 0xFFFFFFEF;
|
||||
reg |= 0x00000040;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Take the all enabled lanes out of reset */
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
|
||||
reg = in_be32(&serdes1_base->lane[i].gcr0);
|
||||
reg |= 0x00600000;
|
||||
out_be32(&serdes1_base->lane[i].gcr0, reg);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
|
||||
cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
|
||||
|
||||
for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
|
||||
reg = in_be32(&serdes2_base->lane[i].gcr0);
|
||||
reg |= 0x00600000;
|
||||
out_be32(&serdes2_base->lane[i].gcr0, reg);
|
||||
}
|
||||
#endif
|
||||
/* For each PLL being reset, and achieved PLL lock set RST_DONE */
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
|
||||
for (i = 0; i < 2; i++) {
|
||||
reg = in_be32(&serdes1_base->bank[i].pllcr0);
|
||||
if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
|
||||
reg = in_be32(&serdes1_base->bank[i].rstctl);
|
||||
reg |= 0x40000000;
|
||||
out_be32(&serdes1_base->bank[i].rstctl, reg);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
|
||||
for (i = 0; i < 2; i++) {
|
||||
reg = in_be32(&serdes2_base->bank[i].pllcr0);
|
||||
if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
|
||||
reg = in_be32(&serdes2_base->bank[i].rstctl);
|
||||
reg |= 0x40000000;
|
||||
out_be32(&serdes2_base->bank[i].rstctl, reg);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
|
|
|
|||
|
|
@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
|
||||
unsigned long cluster_clk;
|
||||
|
||||
sys_info->freq_systembus = sysclk;
|
||||
#ifndef CONFIG_CLUSTER_CLK_FREQ
|
||||
#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#endif
|
||||
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
|
||||
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_LS1012A
|
||||
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
#else
|
||||
/* The freq_systembus is used to record frequency of platform PLL */
|
||||
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
|
||||
#ifdef CONFIG_ARCH_LS1012A
|
||||
sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
|
||||
#else
|
||||
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
|
|
@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
|
||||
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
|
||||
if (ratio[i] > 4)
|
||||
freq_c_pll[i] = sysclk * ratio[i];
|
||||
freq_c_pll[i] = cluster_clk * ratio[i];
|
||||
else
|
||||
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
|
||||
}
|
||||
|
|
@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_LS1012A
|
||||
sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
|
||||
sys_info->freq_ddrbus *= 2;
|
||||
#endif
|
||||
|
||||
#define HWA_CGA_M1_CLK_SEL 0xe0000000
|
||||
#define HWA_CGA_M1_CLK_SHIFT 29
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
|
|
@ -148,7 +149,9 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
break;
|
||||
}
|
||||
#else
|
||||
sys_info->freq_sdhc = sys_info->freq_systembus;
|
||||
sys_info->freq_sdhc = (sys_info->freq_systembus /
|
||||
CONFIG_SYS_FSL_PCLK_DIV) /
|
||||
CONFIG_SYS_FSL_SDHC_CLK_DIV;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
@ -166,7 +169,7 @@ int get_clocks(void)
|
|||
|
||||
get_sys_info(&sys_info);
|
||||
gd->cpu_clk = sys_info.freq_processor[0];
|
||||
gd->bus_clk = sys_info.freq_systembus;
|
||||
gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
|
||||
gd->mem_clk = sys_info.freq_ddrbus;
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
|
|
@ -179,41 +182,73 @@ int get_clocks(void)
|
|||
return 1;
|
||||
}
|
||||
|
||||
/********************************************
|
||||
* get_bus_freq
|
||||
* return platform clock in Hz
|
||||
*********************************************/
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
if (!gd->bus_clk)
|
||||
get_clocks();
|
||||
|
||||
return gd->bus_clk;
|
||||
}
|
||||
|
||||
ulong get_ddr_freq(ulong dummy)
|
||||
{
|
||||
if (!gd->mem_clk)
|
||||
get_clocks();
|
||||
|
||||
return gd->mem_clk;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
int get_sdhc_freq(ulong dummy)
|
||||
{
|
||||
if (!gd->arch.sdhc_clk)
|
||||
get_clocks();
|
||||
|
||||
return gd->arch.sdhc_clk;
|
||||
}
|
||||
#endif
|
||||
|
||||
int get_serial_clock(void)
|
||||
{
|
||||
return gd->bus_clk;
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
|
||||
}
|
||||
|
||||
int get_i2c_freq(ulong dummy)
|
||||
{
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
|
||||
}
|
||||
|
||||
int get_dspi_freq(ulong dummy)
|
||||
{
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_LPUART
|
||||
int get_uart_freq(ulong dummy)
|
||||
{
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
|
||||
}
|
||||
#endif
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case MXC_I2C_CLK:
|
||||
return get_bus_freq(0);
|
||||
return get_i2c_freq(0);
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
case MXC_ESDHC_CLK:
|
||||
return get_sdhc_freq(0);
|
||||
#endif
|
||||
case MXC_DSPI_CLK:
|
||||
return get_bus_freq(0);
|
||||
return get_dspi_freq(0);
|
||||
#ifdef CONFIG_FSL_LPUART
|
||||
case MXC_UART_CLK:
|
||||
return get_bus_freq(0);
|
||||
return get_uart_freq(0);
|
||||
#endif
|
||||
default:
|
||||
printf("Unsupported clock\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/* The freq_systembus is used to record frequency of platform PLL */
|
||||
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
/* Platform clock is half of platform PLL */
|
||||
sys_info->freq_systembus /= 2;
|
||||
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
|
|
@ -142,13 +141,13 @@ int get_clocks(void)
|
|||
struct sys_info sys_info;
|
||||
get_sys_info(&sys_info);
|
||||
gd->cpu_clk = sys_info.freq_processor[0];
|
||||
gd->bus_clk = sys_info.freq_systembus;
|
||||
gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
|
||||
gd->mem_clk = sys_info.freq_ddrbus;
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
|
||||
#endif
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
gd->arch.sdhc_clk = gd->bus_clk / 2;
|
||||
gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
|
||||
#endif /* defined(CONFIG_FSL_ESDHC) */
|
||||
|
||||
if (gd->cpu_clk != 0)
|
||||
|
|
@ -159,7 +158,7 @@ int get_clocks(void)
|
|||
|
||||
/********************************************
|
||||
* get_bus_freq
|
||||
* return system bus freq in Hz
|
||||
* return platform clock in Hz
|
||||
*********************************************/
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
|
|
@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
|
|||
return gd->mem_clk;
|
||||
}
|
||||
|
||||
int get_i2c_freq(ulong dummy)
|
||||
{
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
|
||||
}
|
||||
|
||||
int get_dspi_freq(ulong dummy)
|
||||
{
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
|
||||
}
|
||||
|
||||
int get_serial_clock(void)
|
||||
{
|
||||
return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
|
||||
}
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case MXC_I2C_CLK:
|
||||
return get_bus_freq(0) / 2;
|
||||
return get_i2c_freq(0);
|
||||
case MXC_DSPI_CLK:
|
||||
return get_bus_freq(0) / 2;
|
||||
return get_dspi_freq(0);
|
||||
default:
|
||||
printf("Unsupported clock\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,15 +10,66 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <asm/gic.h>
|
||||
#include <asm/macro.h>
|
||||
#include <asm/arch-fsl-layerscape/soc.h>
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
|
||||
#include <asm/arch-fsl-layerscape/soc.h>
|
||||
#endif
|
||||
#include <asm/u-boot.h>
|
||||
|
||||
/* Get GIC offset
|
||||
* For LS1043a rev1.0, GIC base address align with 4k.
|
||||
* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
|
||||
* is set, GIC base address align with 4K, or else align
|
||||
* with 64k.
|
||||
* output:
|
||||
* x0: the base address of GICD
|
||||
* x1: the base address of GICC
|
||||
*/
|
||||
ENTRY(get_gic_offset)
|
||||
ldr x0, =GICD_BASE
|
||||
#ifdef CONFIG_GICV2
|
||||
ldr x1, =GICC_BASE
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
|
||||
ldr x2, =DCFG_CCSR_SVR
|
||||
ldr w2, [x2]
|
||||
rev w2, w2
|
||||
mov w3, w2
|
||||
ands w3, w3, #SVR_WO_E << 8
|
||||
mov w4, #SVR_LS1043A << 8
|
||||
cmp w3, w4
|
||||
b.ne 1f
|
||||
ands w2, w2, #0xff
|
||||
cmp w2, #REV1_0
|
||||
b.eq 1f
|
||||
ldr x2, =SCFG_GIC400_ALIGN
|
||||
ldr w2, [x2]
|
||||
rev w2, w2
|
||||
tbnz w2, #GIC_ADDR_BIT, 1f
|
||||
ldr x0, =GICD_BASE_64K
|
||||
#ifdef CONFIG_GICV2
|
||||
ldr x1, =GICC_BASE_64K
|
||||
#endif
|
||||
1:
|
||||
#endif
|
||||
ret
|
||||
ENDPROC(get_gic_offset)
|
||||
|
||||
ENTRY(smp_kick_all_cpus)
|
||||
/* Kick secondary cpus up by SGI 0 interrupt */
|
||||
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
|
||||
mov x29, lr /* Save LR */
|
||||
bl get_gic_offset
|
||||
bl gic_kick_secondary_cpus
|
||||
mov lr, x29 /* Restore LR */
|
||||
#endif
|
||||
ret
|
||||
ENDPROC(smp_kick_all_cpus)
|
||||
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
mov x29, lr /* Save LR */
|
||||
|
||||
|
|
@ -29,6 +80,26 @@ ENTRY(lowlevel_init)
|
|||
ldr x0, =CCI_AUX_CONTROL_BASE(20)
|
||||
ldr x1, =0x00000010
|
||||
bl ccn504_set_aux
|
||||
|
||||
/*
|
||||
* Set forced-order mode in RNI-6, RNI-20
|
||||
* This is required for performance optimization on LS2088A
|
||||
* LS2080A family does not support setting forced-order mode,
|
||||
* so skip this operation for LS2080A family
|
||||
*/
|
||||
bl get_svr
|
||||
lsr w0, w0, #16
|
||||
ldr w1, =SVR_DEV_LS2080A
|
||||
cmp w0, w1
|
||||
b.eq 1f
|
||||
|
||||
ldr x0, =CCI_AUX_CONTROL_BASE(6)
|
||||
ldr x1, =0x00000020
|
||||
bl ccn504_set_aux
|
||||
ldr x0, =CCI_AUX_CONTROL_BASE(20)
|
||||
ldr x1, =0x00000020
|
||||
bl ccn504_set_aux
|
||||
1:
|
||||
#endif
|
||||
|
||||
/* Add fully-coherent masters to DVM domain */
|
||||
|
|
@ -110,15 +181,14 @@ ENTRY(lowlevel_init)
|
|||
/* Initialize GIC Secure Bank Status */
|
||||
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
|
||||
branch_if_slave x0, 1f
|
||||
ldr x0, =GICD_BASE
|
||||
bl get_gic_offset
|
||||
bl gic_init_secure
|
||||
1:
|
||||
#ifdef CONFIG_GICV3
|
||||
ldr x0, =GICR_BASE
|
||||
bl gic_init_secure_percpu
|
||||
#elif defined(CONFIG_GICV2)
|
||||
ldr x0, =GICD_BASE
|
||||
ldr x1, =GICC_BASE
|
||||
bl get_gic_offset
|
||||
bl gic_init_secure_percpu
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -209,10 +279,47 @@ ENTRY(lowlevel_init)
|
|||
isb
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
|
||||
bl fsl_ocram_init
|
||||
#endif
|
||||
|
||||
mov lr, x29 /* Restore LR */
|
||||
ret
|
||||
ENDPROC(lowlevel_init)
|
||||
|
||||
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
|
||||
ENTRY(fsl_ocram_init)
|
||||
mov x28, lr /* Save LR */
|
||||
bl fsl_clear_ocram
|
||||
bl fsl_ocram_clear_ecc_err
|
||||
mov lr, x28 /* Restore LR */
|
||||
ret
|
||||
ENDPROC(fsl_ocram_init)
|
||||
|
||||
ENTRY(fsl_clear_ocram)
|
||||
/* Clear OCRAM */
|
||||
ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
|
||||
ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
|
||||
mov x2, #0
|
||||
clear_loop:
|
||||
str x2, [x0]
|
||||
add x0, x0, #8
|
||||
cmp x0, x1
|
||||
b.lo clear_loop
|
||||
ret
|
||||
ENDPROC(fsl_clear_ocram)
|
||||
|
||||
ENTRY(fsl_ocram_clear_ecc_err)
|
||||
/* OCRAM1/2 ECC status bit */
|
||||
mov w1, #0x60
|
||||
ldr x0, =DCSR_DCFG_SBEESR2
|
||||
str w1, [x0]
|
||||
ldr x0, =DCSR_DCFG_MBEESR2
|
||||
str w1, [x0]
|
||||
ret
|
||||
ENDPROC(fsl_ocram_init)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
.globl get_svr
|
||||
get_svr:
|
||||
|
|
@ -356,7 +463,8 @@ ENTRY(secondary_boot_func)
|
|||
#if defined(CONFIG_GICV3)
|
||||
gic_wait_for_interrupt_m x0
|
||||
#elif defined(CONFIG_GICV2)
|
||||
ldr x0, =GICC_BASE
|
||||
bl get_gic_offset
|
||||
mov x0, x1
|
||||
gic_wait_for_interrupt_m x0, w1
|
||||
#endif
|
||||
|
||||
|
|
@ -378,29 +486,29 @@ cpu_is_le:
|
|||
b.eq 1f
|
||||
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
adr x3, secondary_switch_to_el1
|
||||
ldr x4, =ES_TO_AARCH64
|
||||
adr x4, secondary_switch_to_el1
|
||||
ldr x5, =ES_TO_AARCH64
|
||||
#else
|
||||
ldr x3, [x11]
|
||||
ldr x4, =ES_TO_AARCH32
|
||||
ldr x4, [x11]
|
||||
ldr x5, =ES_TO_AARCH32
|
||||
#endif
|
||||
bl secondary_switch_to_el2
|
||||
|
||||
1:
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
adr x3, secondary_switch_to_el1
|
||||
adr x4, secondary_switch_to_el1
|
||||
#else
|
||||
ldr x3, [x11]
|
||||
ldr x4, [x11]
|
||||
#endif
|
||||
ldr x4, =ES_TO_AARCH64
|
||||
ldr x5, =ES_TO_AARCH64
|
||||
bl secondary_switch_to_el2
|
||||
|
||||
ENDPROC(secondary_boot_func)
|
||||
|
||||
ENTRY(secondary_switch_to_el2)
|
||||
switch_el x5, 1f, 0f, 0f
|
||||
switch_el x6, 1f, 0f, 0f
|
||||
0: ret
|
||||
1: armv8_switch_to_el2_m x3, x4, x5
|
||||
1: armv8_switch_to_el2_m x4, x5, x6
|
||||
ENDPROC(secondary_switch_to_el2)
|
||||
|
||||
ENTRY(secondary_switch_to_el1)
|
||||
|
|
@ -414,22 +522,22 @@ ENTRY(secondary_switch_to_el1)
|
|||
/* physical address of this cpus spin table element */
|
||||
add x11, x1, x0
|
||||
|
||||
ldr x3, [x11]
|
||||
ldr x4, [x11]
|
||||
|
||||
ldr x5, [x11, #24]
|
||||
ldr x6, =IH_ARCH_DEFAULT
|
||||
cmp x6, x5
|
||||
b.eq 2f
|
||||
|
||||
ldr x4, =ES_TO_AARCH32
|
||||
ldr x5, =ES_TO_AARCH32
|
||||
bl switch_to_el1
|
||||
|
||||
2: ldr x4, =ES_TO_AARCH64
|
||||
2: ldr x5, =ES_TO_AARCH64
|
||||
|
||||
switch_to_el1:
|
||||
switch_el x5, 0f, 1f, 0f
|
||||
switch_el x6, 0f, 1f, 0f
|
||||
0: ret
|
||||
1: armv8_switch_to_el1_m x3, x4, x5
|
||||
1: armv8_switch_to_el1_m x4, x5, x6
|
||||
ENDPROC(secondary_switch_to_el1)
|
||||
|
||||
/* Ensure that the literals used by the secondary boot code are
|
||||
|
|
|
|||
|
|
@ -213,10 +213,12 @@ int sata_init(void)
|
|||
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
|
||||
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
|
||||
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
|
||||
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
|
||||
|
||||
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
|
||||
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
|
||||
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
|
||||
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
|
||||
|
||||
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
|
||||
scsi_scan(0);
|
||||
|
|
@ -336,6 +338,95 @@ static void erratum_a010539(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* Get VDD in the unit mV from voltage ID */
|
||||
int get_core_volt_from_fuse(void)
|
||||
{
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
int vdd;
|
||||
u32 fusesr;
|
||||
u8 vid;
|
||||
|
||||
fusesr = in_be32(&gur->dcfg_fusesr);
|
||||
debug("%s: fusesr = 0x%x\n", __func__, fusesr);
|
||||
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
|
||||
FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
|
||||
if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
|
||||
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
|
||||
FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
|
||||
}
|
||||
debug("%s: VID = 0x%x\n", __func__, vid);
|
||||
switch (vid) {
|
||||
case 0x00: /* VID isn't supported */
|
||||
vdd = -EINVAL;
|
||||
debug("%s: The VID feature is not supported\n", __func__);
|
||||
break;
|
||||
case 0x08: /* 0.9V silicon */
|
||||
vdd = 900;
|
||||
break;
|
||||
case 0x10: /* 1.0V silicon */
|
||||
vdd = 1000;
|
||||
break;
|
||||
default: /* Other core voltage */
|
||||
vdd = -EINVAL;
|
||||
printf("%s: The VID(%x) isn't supported\n", __func__, vid);
|
||||
break;
|
||||
}
|
||||
debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
|
||||
|
||||
return vdd;
|
||||
}
|
||||
|
||||
__weak int board_switch_core_volt(u32 vdd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_core_volt(u32 vdd)
|
||||
{
|
||||
return board_setup_core_volt(vdd);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DDR
|
||||
static void ddr_enable_0v9_volt(bool en)
|
||||
{
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
u32 tmp;
|
||||
|
||||
tmp = ddr_in32(&ddr->ddr_cdr1);
|
||||
|
||||
if (en)
|
||||
tmp |= DDR_CDR1_V0PT9_EN;
|
||||
else
|
||||
tmp &= ~DDR_CDR1_V0PT9_EN;
|
||||
|
||||
ddr_out32(&ddr->ddr_cdr1, tmp);
|
||||
}
|
||||
#endif
|
||||
|
||||
int setup_chip_volt(void)
|
||||
{
|
||||
int vdd;
|
||||
|
||||
vdd = get_core_volt_from_fuse();
|
||||
/* Nothing to do for silicons doesn't support VID */
|
||||
if (vdd < 0)
|
||||
return vdd;
|
||||
|
||||
if (setup_core_volt(vdd))
|
||||
printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
|
||||
#ifdef CONFIG_SYS_HAS_SERDES
|
||||
if (setup_serdes_volt(vdd))
|
||||
printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DDR
|
||||
if (vdd == 900)
|
||||
ddr_enable_0v9_volt(true);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fsl_lsch2_early_init_f(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
|
|
|
|||
|
|
@ -209,7 +209,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img)
|
|||
return true;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
|
||||
#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
|
||||
/*
|
||||
* The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
|
||||
* v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error
|
||||
|
|
|
|||
|
|
@ -23,12 +23,12 @@ WEAK(_sec_firmware_entry)
|
|||
/* Set exception return address hold pointer */
|
||||
adr x4, 1f
|
||||
mov x3, x4
|
||||
#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
|
||||
rev w3, w3
|
||||
#endif
|
||||
str w3, [x1]
|
||||
lsr x3, x4, #32
|
||||
#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
|
||||
rev w3, w3
|
||||
#endif
|
||||
str w3, [x2]
|
||||
|
|
@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry)
|
|||
ret
|
||||
ENDPROC(_sec_firmware_entry)
|
||||
|
||||
#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
|
||||
#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
|
||||
ENTRY(_sec_firmware_support_psci_version)
|
||||
mov x0, 0x84000000
|
||||
mov x1, 0x0
|
||||
|
|
@ -57,7 +57,8 @@ ENDPROC(_sec_firmware_support_psci_version)
|
|||
* x0: argument, zero
|
||||
* x1: machine nr
|
||||
* x2: fdt address
|
||||
* x3: kernel entry point
|
||||
* x3: input argument
|
||||
* x4: kernel entry point
|
||||
* @param outputs for secure firmware:
|
||||
* x0: function id
|
||||
* x1: kernel entry point
|
||||
|
|
@ -65,10 +66,9 @@ ENDPROC(_sec_firmware_support_psci_version)
|
|||
* x3: fdt address
|
||||
*/
|
||||
ENTRY(armv8_el2_to_aarch32)
|
||||
mov x0, x3
|
||||
mov x3, x2
|
||||
mov x2, x1
|
||||
mov x1, x0
|
||||
mov x1, x4
|
||||
ldr x0, =0xc000ff04
|
||||
smc #0
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -85,6 +85,17 @@ save_boot_params_ret:
|
|||
msr cpacr_el1, x0 /* Enable FP/SIMD */
|
||||
0:
|
||||
|
||||
/*
|
||||
* Enalbe SMPEN bit for coherency.
|
||||
* This register is not architectural but at the moment
|
||||
* this bit should be set for A53/A57/A72.
|
||||
*/
|
||||
#ifdef CONFIG_ARMV8_SET_SMPEN
|
||||
mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
|
||||
orr x0, x0, #0x40
|
||||
msr S3_1_c15_c2_1, x0
|
||||
#endif
|
||||
|
||||
/* Apply ARM core specific erratas */
|
||||
bl apply_core_errata
|
||||
|
||||
|
|
@ -250,14 +261,14 @@ WEAK(lowlevel_init)
|
|||
/*
|
||||
* All slaves will enter EL2 and optionally EL1.
|
||||
*/
|
||||
adr x3, lowlevel_in_el2
|
||||
ldr x4, =ES_TO_AARCH64
|
||||
adr x4, lowlevel_in_el2
|
||||
ldr x5, =ES_TO_AARCH64
|
||||
bl armv8_switch_to_el2
|
||||
|
||||
lowlevel_in_el2:
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
adr x3, lowlevel_in_el1
|
||||
ldr x4, =ES_TO_AARCH64
|
||||
adr x4, lowlevel_in_el1
|
||||
ldr x5, =ES_TO_AARCH64
|
||||
bl armv8_switch_to_el1
|
||||
|
||||
lowlevel_in_el1:
|
||||
|
|
|
|||
|
|
@ -11,9 +11,9 @@
|
|||
#include <asm/macro.h>
|
||||
|
||||
ENTRY(armv8_switch_to_el2)
|
||||
switch_el x5, 1f, 0f, 0f
|
||||
switch_el x6, 1f, 0f, 0f
|
||||
0:
|
||||
cmp x4, #ES_TO_AARCH64
|
||||
cmp x5, #ES_TO_AARCH64
|
||||
b.eq 2f
|
||||
/*
|
||||
* When loading 32-bit kernel, it will jump
|
||||
|
|
@ -22,23 +22,23 @@ ENTRY(armv8_switch_to_el2)
|
|||
bl armv8_el2_to_aarch32
|
||||
2:
|
||||
/*
|
||||
* x3 is kernel entry point or switch_to_el1
|
||||
* x4 is kernel entry point or switch_to_el1
|
||||
* if CONFIG_ARMV8_SWITCH_TO_EL1 is defined.
|
||||
* When running in EL2 now, jump to the
|
||||
* address saved in x3.
|
||||
* address saved in x4.
|
||||
*/
|
||||
br x3
|
||||
1: armv8_switch_to_el2_m x3, x4, x5
|
||||
br x4
|
||||
1: armv8_switch_to_el2_m x4, x5, x6
|
||||
ENDPROC(armv8_switch_to_el2)
|
||||
|
||||
ENTRY(armv8_switch_to_el1)
|
||||
switch_el x5, 0f, 1f, 0f
|
||||
switch_el x6, 0f, 1f, 0f
|
||||
0:
|
||||
/* x3 is kernel entry point. When running in EL1
|
||||
* now, jump to the address saved in x3.
|
||||
/* x4 is kernel entry point. When running in EL1
|
||||
* now, jump to the address saved in x4.
|
||||
*/
|
||||
br x3
|
||||
1: armv8_switch_to_el1_m x3, x4, x5
|
||||
br x4
|
||||
1: armv8_switch_to_el1_m x4, x5, x6
|
||||
ENDPROC(armv8_switch_to_el1)
|
||||
|
||||
WEAK(armv8_el2_to_aarch32)
|
||||
|
|
|
|||
|
|
@ -54,6 +54,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc0: esdhc@1560000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
esdhc1: esdhc@1580000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
interrupts = <0 65 0x4>;
|
||||
big-endian;
|
||||
non-removable;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
|
|
@ -103,5 +119,35 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
||||
0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
|
||||
0x40 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "ctrl", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
usb0: usb2@8600000 {
|
||||
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
|
||||
reg = <0x0 0x8600000 0x0 0x1000>;
|
||||
interrupts = <0 139 0x4>;
|
||||
dr_mode = "host";
|
||||
fsl,usb-erratum-a005697;
|
||||
};
|
||||
|
||||
usb1: usb3@2f00000 {
|
||||
compatible = "fsl,layerscape-dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <0 61 0x4>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -236,5 +236,51 @@
|
|||
interrupts = <0 63 0x4>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
|
||||
0x00 0x03410000 0x0 0x10000 /* lut registers */
|
||||
0x40 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
|
||||
0x00 0x03510000 0x0 0x10000 /* lut registers */
|
||||
0x48 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
|
||||
0x00 0x03610000 0x0 0x10000 /* lut registers */
|
||||
0x50 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -216,5 +216,54 @@
|
|||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
||||
0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
|
||||
0x40 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "ctrl", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03580000 0x0 0x40000 /* lut registers */
|
||||
0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
|
||||
0x48 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "ctrl", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03680000 0x0 0x40000 /* lut registers */
|
||||
0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
|
||||
0x50 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "ctrl", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -89,4 +89,64 @@
|
|||
interrupts = <0 81 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03480000 0x0 0x80000 /* lut registers */
|
||||
0x10 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03580000 0x0 0x80000 /* lut registers */
|
||||
0x12 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03680000 0x0 0x80000 /* lut registers */
|
||||
0x14 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3700000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
|
||||
0x00 0x03780000 0x0 0x80000 /* lut registers */
|
||||
0x16 0x00000000 0x0 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "lut", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -374,5 +374,36 @@
|
|||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x03400000 0x20000 /* dbi registers */
|
||||
0x01570000 0x10000 /* pf controls registers */
|
||||
0x24000000 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "ctrl", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||
reg = <0x03500000 0x10000 /* dbi registers */
|
||||
0x01570000 0x10000 /* pf controls registers */
|
||||
0x34000000 0x20000>; /* configuration space */
|
||||
reg-names = "dbi", "ctrl", "config";
|
||||
big-endian;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,8 +28,9 @@
|
|||
#define CONFIG_FSL_TZASC_400
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
|
|
@ -122,7 +123,11 @@
|
|||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
#define DCSR_DCFG_SBEESR2 0x20140534
|
||||
#define DCSR_DCFG_MBEESR2 0x20140544
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
|
|
@ -158,6 +163,28 @@
|
|||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
#define GICH_BASE 0x01404000
|
||||
#define GICV_BASE 0x01406000
|
||||
#define GICD_SIZE 0x1000
|
||||
#define GICC_SIZE 0x2000
|
||||
#define GICH_SIZE 0x2000
|
||||
#define GICV_SIZE 0x2000
|
||||
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
|
||||
#define GICD_BASE_64K 0x01410000
|
||||
#define GICC_BASE_64K 0x01420000
|
||||
#define GICH_BASE_64K 0x01440000
|
||||
#define GICV_BASE_64K 0x01460000
|
||||
#define GICD_SIZE_64K 0x10000
|
||||
#define GICC_SIZE_64K 0x20000
|
||||
#define GICH_SIZE_64K 0x20000
|
||||
#define GICV_SIZE_64K 0x20000
|
||||
#endif
|
||||
|
||||
#define DCFG_CCSR_SVR 0x1ee00a4
|
||||
#define REV1_0 0x10
|
||||
#define REV1_1 0x11
|
||||
#define GIC_ADDR_BIT 31
|
||||
#define SCFG_GIC400_ALIGN 0x1570188
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static struct mm_region early_map[] = {
|
|||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
|
||||
|
|
@ -140,7 +140,7 @@ static struct mm_region early_map[] = {
|
|||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
|
|
@ -178,7 +178,7 @@ static struct mm_region final_map[] = {
|
|||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
|
|
@ -280,7 +280,7 @@ static struct mm_region final_map[] = {
|
|||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
|
|
|
|||
|
|
@ -7,9 +7,5 @@
|
|||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
|
||||
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
|
||||
void append_mmu_masters(void *blob, const char *smmu_path,
|
||||
const char *master_name, u32 *stream_ids, int count);
|
||||
void fdt_fixup_smmu_pcie(void *blob);
|
||||
void fdt_fixup_board_enet(void *fdt);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
|
||||
|
|
|
|||
|
|
@ -162,6 +162,14 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
|||
#ifdef CONFIG_FSL_LSCH2
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
int get_serdes_protocol(void);
|
||||
#ifdef CONFIG_SYS_HAS_SERDES
|
||||
/* Get the volt of SVDD in unit mV */
|
||||
int get_serdes_volt(void);
|
||||
/* Set the volt of SVDD in unit mV */
|
||||
int set_serdes_volt(int svdd);
|
||||
/* The target volt of SVDD in unit mV */
|
||||
int setup_serdes_volt(u32 svdd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_SERDES_H__ */
|
||||
|
|
|
|||
|
|
@ -137,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
|
|||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
/* frequency of platform PLL */
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
|
|
@ -360,7 +361,8 @@ struct ccsr_scfg {
|
|||
u32 qspi_cfg;
|
||||
u8 res_160[0x180-0x160];
|
||||
u32 dmamcr;
|
||||
u8 res_184[0x18c-0x184];
|
||||
u8 res_184[0x188-0x184];
|
||||
u32 gic_align;
|
||||
u32 debug_icid;
|
||||
u8 res_190[0x1a4-0x190];
|
||||
u32 snpcnfgcr;
|
||||
|
|
|
|||
|
|
@ -107,14 +107,6 @@
|
|||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
/* LUT registers */
|
||||
#define PCIE_LUT_BASE 0x80000
|
||||
#define PCIE_LUT_LCTRL0 0x7F8
|
||||
#define PCIE_LUT_DBG 0x7FC
|
||||
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
|
||||
#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
|
||||
#define PCIE_LUT_ENABLE (1 << 31)
|
||||
#define PCIE_LUT_ENTRY_COUNT 32
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
|
|
@ -159,6 +151,7 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
/* frequency of platform PLL */
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ struct cpu_type {
|
|||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||
#define IS_SVR_REV(svr, maj, min) \
|
||||
|
|
@ -99,6 +100,9 @@ struct ccsr_ahci {
|
|||
void fsl_lsch3_early_init_f(void);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
void fsl_lsch2_early_init_f(void);
|
||||
int setup_chip_volt(void);
|
||||
/* Setup core vdd in unit mV */
|
||||
int board_setup_core_volt(u32 vdd);
|
||||
#endif
|
||||
|
||||
void cpu_name(char *name);
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int sec_firmware_init(const void *, u32 *, u32 *);
|
||||
int _sec_firmware_entry(const void *, u32 *, u32 *);
|
||||
bool sec_firmware_is_valid(const void *);
|
||||
#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
|
||||
#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
|
||||
unsigned int sec_firmware_support_psci_version(void);
|
||||
unsigned int _sec_firmware_support_psci_version(void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -80,18 +80,18 @@
|
|||
|
||||
/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
|
||||
* Non-XIP Memory (Nand/SD)*/
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
|
||||
defined(CONFIG_SD_BOOT)
|
||||
#define CONFIG_BOOTSCRIPT_COPY_RAM
|
||||
#endif
|
||||
/* The address needs to be modified according to NOR, NAND, SD and
|
||||
* DDR memory map
|
||||
*/
|
||||
#ifdef CONFIG_LS2080A
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x583900000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
|
||||
#define CONFIG_BS_ADDR_RAM 0xa3900000
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x580e00000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000
|
||||
#define CONFIG_BS_ADDR_RAM 0xa0e00000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -196,11 +196,12 @@ void __asm_switch_ttbr(u64 new_ttbr);
|
|||
* For loading 32-bit OS, machine nr
|
||||
* @fdt_addr: For loading 64-bit OS, zero.
|
||||
* For loading 32-bit OS, fdt address.
|
||||
* @arg4: Input argument.
|
||||
* @entry_point: kernel entry point
|
||||
* @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
|
||||
*/
|
||||
void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
|
||||
u64 entry_point, u64 es_flag);
|
||||
u64 arg4, u64 entry_point, u64 es_flag);
|
||||
/*
|
||||
* Switch from EL2 to EL1 for ARMv8
|
||||
*
|
||||
|
|
@ -210,13 +211,14 @@ void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
|
|||
* For loading 32-bit OS, machine nr
|
||||
* @fdt_addr: For loading 64-bit OS, zero.
|
||||
* For loading 32-bit OS, fdt address.
|
||||
* @arg4: Input argument.
|
||||
* @entry_point: kernel entry point
|
||||
* @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
|
||||
*/
|
||||
void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
|
||||
u64 entry_point, u64 es_flag);
|
||||
u64 arg4, u64 entry_point, u64 es_flag);
|
||||
void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
|
||||
u64 entry_point);
|
||||
u64 arg4, u64 entry_point);
|
||||
void gic_init(void);
|
||||
void gic_send_sgi(unsigned long sgino);
|
||||
void wait_for_wakeup(void);
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ int arch_fixup_fdt(void *blob)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \
|
||||
defined(CONFIG_FSL_PPA_ARMV8_PSCI)
|
||||
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
|
||||
ret = psci_update_dt(blob);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -287,11 +287,11 @@ static void switch_to_el1(void)
|
|||
if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
|
||||
(images.os.arch == IH_ARCH_ARM))
|
||||
armv8_switch_to_el1(0, (u64)gd->bd->bi_arch_number,
|
||||
(u64)images.ft_addr,
|
||||
(u64)images.ft_addr, 0,
|
||||
(u64)images.ep,
|
||||
ES_TO_AARCH32);
|
||||
else
|
||||
armv8_switch_to_el1((u64)images.ft_addr, 0, 0,
|
||||
armv8_switch_to_el1((u64)images.ft_addr, 0, 0, 0,
|
||||
images.ep,
|
||||
ES_TO_AARCH64);
|
||||
}
|
||||
|
|
@ -324,17 +324,17 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
|||
update_os_arch_secondary_cores(images->os.arch);
|
||||
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
armv8_switch_to_el2((u64)images->ft_addr, 0, 0,
|
||||
armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0,
|
||||
(u64)switch_to_el1, ES_TO_AARCH64);
|
||||
#else
|
||||
if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
|
||||
(images->os.arch == IH_ARCH_ARM))
|
||||
armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number,
|
||||
(u64)images->ft_addr,
|
||||
(u64)images->ft_addr, 0,
|
||||
(u64)images->ep,
|
||||
ES_TO_AARCH32);
|
||||
else
|
||||
armv8_switch_to_el2((u64)images->ft_addr, 0, 0,
|
||||
armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0,
|
||||
images->ep,
|
||||
ES_TO_AARCH64);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
int fdt_psci(void *fdt)
|
||||
{
|
||||
#if defined(CONFIG_ARMV7_PSCI) || defined(CONFIG_ARMV8_PSCI) || \
|
||||
defined(CONFIG_FSL_PPA_ARMV8_PSCI)
|
||||
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
|
||||
int nodeoff;
|
||||
unsigned int psci_ver = 0;
|
||||
int tmp;
|
||||
|
|
|
|||
|
|
@ -61,14 +61,14 @@ ENTRY(lowlevel_init)
|
|||
/*
|
||||
* All slaves will enter EL2 and optionally EL1.
|
||||
*/
|
||||
adr x3, lowlevel_in_el2
|
||||
ldr x4, =ES_TO_AARCH64
|
||||
adr x4, lowlevel_in_el2
|
||||
ldr x5, =ES_TO_AARCH64
|
||||
bl armv8_switch_to_el2
|
||||
|
||||
lowlevel_in_el2:
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
adr x3, lowlevel_in_el1
|
||||
ldr x4, =ES_TO_AARCH64
|
||||
adr x4, lowlevel_in_el1
|
||||
ldr x5, =ES_TO_AARCH64
|
||||
bl armv8_switch_to_el1
|
||||
|
||||
lowlevel_in_el1:
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
|
|||
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
|
||||
obj-$(CONFIG_ZM7300) += zm7300.o
|
||||
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
|
||||
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
|
||||
|
||||
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
|
||||
|
||||
|
|
|
|||
95
board/freescale/common/mc34vr500.c
Normal file
95
board/freescale/common/mc34vr500.c
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
* Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <i2c.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/mc34vr500_pmic.h>
|
||||
|
||||
static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT,
|
||||
MC34VR500_SW2VOLT,
|
||||
MC34VR500_SW3VOLT,
|
||||
MC34VR500_SW4VOLT };
|
||||
|
||||
static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 };
|
||||
|
||||
int mc34vr500_get_sw_volt(uint8_t sw)
|
||||
{
|
||||
struct pmic *p;
|
||||
u32 swxvolt;
|
||||
uint8_t spb;
|
||||
int sw_volt;
|
||||
int ret;
|
||||
|
||||
debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n",
|
||||
__func__, sw + 1, swxvolt_addr[sw]);
|
||||
if (sw > SW4) {
|
||||
printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
p = pmic_get("MC34VR500");
|
||||
if (!p) {
|
||||
printf("%s: Did NOT find PMIC MC34VR500\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = pmic_probe(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt);
|
||||
if (ret) {
|
||||
printf("%s: Failed to get SW%u volt\n", __func__, sw + 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt);
|
||||
spb = swx_set_point_base[sw];
|
||||
/* The base of SW volt is 625mV and increase by step 25mV */
|
||||
sw_volt = 625 + (swxvolt - spb) * 25;
|
||||
|
||||
debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt);
|
||||
return sw_volt;
|
||||
}
|
||||
|
||||
int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt)
|
||||
{
|
||||
struct pmic *p;
|
||||
u32 swxvolt;
|
||||
uint8_t spb;
|
||||
int ret;
|
||||
|
||||
debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt);
|
||||
/* The least SW volt is 625mV, and only 4 SW outputs */
|
||||
if (sw > SW4 || sw_volt < 625)
|
||||
return -EINVAL;
|
||||
|
||||
p = pmic_get("MC34VR500");
|
||||
if (!p) {
|
||||
printf("%s: Did NOT find PMIC MC34VR500\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = pmic_probe(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
spb = swx_set_point_base[sw];
|
||||
/* The base of SW volt is 625mV and increase by step 25mV */
|
||||
swxvolt = (sw_volt - 625) / 25 + spb;
|
||||
debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt);
|
||||
if (swxvolt > 63)
|
||||
return -EINVAL;
|
||||
|
||||
ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -121,6 +121,34 @@ int board_eth_init(bd_t *bis)
|
|||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
int esdhc_status_fixup(void *blob, const char *compat)
|
||||
{
|
||||
char esdhc0_path[] = "/soc/esdhc@1560000";
|
||||
char esdhc1_path[] = "/soc/esdhc@1580000";
|
||||
u8 card_id;
|
||||
|
||||
do_fixup_by_path(blob, esdhc0_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
|
||||
/*
|
||||
* The Presence Detect 2 register detects the installation
|
||||
* of cards in various PCI Express or SGMII slots.
|
||||
*
|
||||
* STAT_PRS2[7:5]: Specifies the type of card installed in the
|
||||
* SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
|
||||
*/
|
||||
card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
|
||||
|
||||
/* If no adapter is installed in SDHC2, disable SDHC2 */
|
||||
if (card_id == 0x7)
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
else
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -113,6 +113,44 @@ int board_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int esdhc_status_fixup(void *blob, const char *compat)
|
||||
{
|
||||
char esdhc0_path[] = "/soc/esdhc@1560000";
|
||||
char esdhc1_path[] = "/soc/esdhc@1580000";
|
||||
u8 io = 0;
|
||||
u8 mux_sdhc2;
|
||||
|
||||
do_fixup_by_path(blob, esdhc0_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
/*
|
||||
* The I2C IO-expander for mux select is used to control the muxing
|
||||
* of various onboard interfaces.
|
||||
*
|
||||
* IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
|
||||
* 00 - SDIO wifi
|
||||
* 01 - GPIO (to Arduino)
|
||||
* 10 - eMMC Memory
|
||||
* 11 - SPI
|
||||
*/
|
||||
if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
|
||||
printf("Error reading i2c boot information!\n");
|
||||
return 0; /* Don't want to hang() on this error */
|
||||
}
|
||||
|
||||
mux_sdhc2 = (io & 0x0c) >> 2;
|
||||
/* Enable SDHC2 only when use SDIO wifi and eMMC */
|
||||
if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
else
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
arch_fixup_fdt(blob);
|
||||
|
|
|
|||
|
|
@ -82,6 +82,15 @@ void cpld_set_sd(void)
|
|||
|
||||
CPLD_WRITE(system_rst, 1);
|
||||
}
|
||||
|
||||
void cpld_select_core_volt(bool en_0v9)
|
||||
{
|
||||
u8 reg17 = en_0v9;
|
||||
|
||||
CPLD_WRITE(vdd_en, 1);
|
||||
CPLD_WRITE(vdd_sel, reg17);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static void cpld_dump_regs(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ struct cpld_data {
|
|||
u8 cpld_read(unsigned int reg);
|
||||
void cpld_write(unsigned int reg, u8 value);
|
||||
void cpld_rev_bit(unsigned char *value);
|
||||
void cpld_select_core_volt(bool en_0v9);
|
||||
|
||||
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
|
||||
#define CPLD_WRITE(reg, value) \
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <fm_eth.h>
|
||||
#include <fsl_csu.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <power/mc34vr500_pmic.h>
|
||||
#include "cpld.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
@ -87,6 +88,39 @@ int board_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int board_setup_core_volt(u32 vdd)
|
||||
{
|
||||
bool en_0v9;
|
||||
|
||||
en_0v9 = (vdd == 900) ? true : false;
|
||||
cpld_select_core_volt(en_0v9);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_serdes_volt(void)
|
||||
{
|
||||
return mc34vr500_get_sw_volt(SW4);
|
||||
}
|
||||
|
||||
int set_serdes_volt(int svdd)
|
||||
{
|
||||
return mc34vr500_set_sw_volt(SW4, svdd);
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = power_mc34vr500_init(0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
setup_chip_volt();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void config_board_mux(void)
|
||||
{
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
|
|
|
|||
|
|
@ -246,7 +246,7 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt)
|
|||
|
||||
/* Move into EL2 and keep running there */
|
||||
armv8_switch_to_el2((ulong)entry, (ulong)&loaded_image_info,
|
||||
(ulong)&systab, (ulong)efi_run_in_el2,
|
||||
(ulong)&systab, 0, (ulong)efi_run_in_el2,
|
||||
ES_TO_AARCH64);
|
||||
|
||||
/* Should never reach here, efi exits with longjmp */
|
||||
|
|
|
|||
|
|
@ -30,9 +30,15 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -31,11 +31,18 @@ CONFIG_DM_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_MMC_OPS=n
|
||||
CONFIG_BLK=n
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -31,11 +31,18 @@ CONFIG_DM_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_MMC_OPS=n
|
||||
CONFIG_BLK=n
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -13,3 +13,7 @@ CONFIG_SYS_NS16550=y
|
|||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -16,3 +16,7 @@ CONFIG_SYS_NS16550=y
|
|||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
|
|
@ -12,6 +13,7 @@ CONFIG_VIDEO=y
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
|
||||
CONFIG_NAND_BOOT=y
|
||||
|
|
@ -38,9 +40,9 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
@ -48,3 +50,7 @@ CONFIG_USB_XHCI_DWC3=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -1,11 +1,13 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
|
|
@ -29,7 +31,6 @@ CONFIG_DM=y
|
|||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
@ -39,3 +40,7 @@ CONFIG_USB_STORAGE=y
|
|||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ CONFIG_DM=y
|
|||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@ CONFIG_DM=y
|
|||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -39,3 +38,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -41,10 +41,13 @@ CONFIG_DM=y
|
|||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -45,7 +45,6 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -55,3 +54,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021ATWR=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
|
|
@ -28,7 +30,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
@ -38,3 +39,7 @@ CONFIG_USB_STORAGE=y
|
|||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -36,3 +35,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@ CONFIG_SPI_FLASH_ATMEL=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021ATWR=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
|
|
@ -13,6 +14,7 @@ CONFIG_VIDEO=y
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
|
||||
CONFIG_BOOTDELAY=0
|
||||
|
|
@ -42,7 +44,6 @@ CONFIG_DM=y
|
|||
CONFIG_SPL_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
@ -52,3 +53,7 @@ CONFIG_USB_STORAGE=y
|
|||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021ATWR=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
|
|
@ -11,6 +12,7 @@ CONFIG_VIDEO=y
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
|
||||
CONFIG_SD_BOOT=y
|
||||
|
|
@ -35,9 +37,9 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
@ -45,3 +47,7 @@ CONFIG_USB_XHCI_DWC3=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -45,7 +45,6 @@ CONFIG_SPI_FLASH_ATMEL=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -55,3 +54,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -32,3 +31,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
@ -34,3 +33,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -46,3 +45,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -33,3 +32,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -35,3 +34,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -46,3 +45,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -47,3 +46,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1043ARDB=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -20,7 +21,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -30,3 +30,9 @@ CONFIG_USB_XHCI_DWC3=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
@ -20,7 +21,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -28,3 +28,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -42,3 +41,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
|
@ -42,3 +41,9 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -25,3 +25,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -30,3 +30,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -28,3 +28,9 @@ CONFIG_SYS_NS16550=y
|
|||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -30,3 +30,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -32,3 +32,9 @@ CONFIG_SYS_NS16550=y
|
|||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -27,3 +27,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_QSPI_BOOT=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
|
|
@ -24,3 +25,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -27,3 +27,9 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS2080AQDS=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -21,7 +22,6 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -33,3 +33,7 @@ CONFIG_USB_STORAGE=y
|
|||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
|
|
@ -40,3 +39,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
|
|
@ -32,3 +31,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS2080ARDB=y
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -21,7 +22,6 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -33,3 +33,7 @@ CONFIG_USB_STORAGE=y
|
|||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@ CONFIG_DM=y
|
|||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
|
|
@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
|
|||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
@ -35,3 +34,7 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
|
|
|
|||
|
|
@ -104,8 +104,10 @@ struct fsl_esdhc_priv {
|
|||
struct udevice *dev;
|
||||
int non_removable;
|
||||
int wp_enable;
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
struct gpio_desc cd_gpio;
|
||||
struct gpio_desc wp_gpio;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Return the XFERTYP flags for a given command and data packet */
|
||||
|
|
@ -688,9 +690,10 @@ static int esdhc_getcd(struct mmc *mmc)
|
|||
#ifdef CONFIG_DM_MMC
|
||||
if (priv->non_removable)
|
||||
return 1;
|
||||
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
if (dm_gpio_is_valid(&priv->cd_gpio))
|
||||
return dm_gpio_get_value(&priv->cd_gpio);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
|
||||
|
|
@ -909,17 +912,26 @@ void mmc_adapter_card_type_ident(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
__weak int esdhc_status_fixup(void *blob, const char *compat)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
||||
if (!hwconfig("esdhc")) {
|
||||
do_fixup_by_compat(blob, compat, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
do_fixup_by_compat(blob, compat, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
||||
{
|
||||
const char *compat = "fsl,esdhc";
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
||||
if (!hwconfig("esdhc")) {
|
||||
do_fixup_by_compat(blob, compat, "status", "disabled",
|
||||
8 + 1, 1);
|
||||
if (esdhc_status_fixup(blob, compat))
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
|
||||
|
|
@ -932,8 +944,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
|||
do_fixup_by_compat_u32(blob, compat, "adapter-type",
|
||||
(u32)(gd->arch.sdhc_adapter), 1);
|
||||
#endif
|
||||
do_fixup_by_compat(blob, compat, "status", "okay",
|
||||
4 + 1, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -968,17 +978,20 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||
priv->non_removable = 1;
|
||||
} else {
|
||||
priv->non_removable = 0;
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
|
||||
&priv->cd_gpio, GPIOD_IS_IN);
|
||||
#endif
|
||||
}
|
||||
|
||||
priv->wp_enable = 1;
|
||||
|
||||
#ifdef CONFIG_DM_GPIO
|
||||
ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
|
||||
&priv->wp_gpio, GPIOD_IS_IN);
|
||||
if (ret)
|
||||
priv->wp_enable = 0;
|
||||
|
||||
#endif
|
||||
/*
|
||||
* TODO:
|
||||
* Because lack of clk driver, if SDHC clk is not enabled,
|
||||
|
|
@ -1022,6 +1035,7 @@ static const struct udevice_id fsl_esdhc_ids[] = {
|
|||
{ .compatible = "fsl,imx6sl-usdhc", },
|
||||
{ .compatible = "fsl,imx6q-usdhc", },
|
||||
{ .compatible = "fsl,imx7d-usdhc", },
|
||||
{ .compatible = "fsl,esdhc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -71,4 +71,12 @@ config PCI_XILINX
|
|||
Enable support for the Xilinx AXI bridge for PCI express, an IP block
|
||||
which can be used on some generations of Xilinx FPGAs.
|
||||
|
||||
config PCIE_LAYERSCAPE
|
||||
bool "Layerscape PCIe support"
|
||||
depends on DM_PCI
|
||||
help
|
||||
Support Layerscape PCIe. The Layerscape SoC may have one or several
|
||||
PCIe controllers. The PCIe may works in RC or EP mode according to
|
||||
RCW[HOST_AGT_PEX] setting.
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -32,4 +32,5 @@ obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
|
|||
obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
|
||||
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
|
||||
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
|
||||
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
|
||||
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
|
||||
|
|
|
|||
|
|
@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
|
|||
return phys_addr;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_PCI
|
||||
/* The root controller has the region information */
|
||||
hose = pci_bus_to_hose(0);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* if PCI_REGION_MEM is set we do a two pass search with preference
|
||||
* on matches that don't have PCI_REGION_SYS_MEMORY set
|
||||
|
|
@ -236,6 +231,13 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
|
|||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* pci_hose_phys_to_bus(): Convert physical address to bus address
|
||||
* @hose: PCI hose of the root PCI controller
|
||||
* @phys_addr: physical address to convert
|
||||
* @flags: flags of pci regions
|
||||
* @return bus address if OK, 0 on error
|
||||
*/
|
||||
pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
|
||||
phys_addr_t phys_addr,
|
||||
unsigned long flags)
|
||||
|
|
@ -248,11 +250,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
|
|||
return bus_addr;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_PCI
|
||||
/* The root controller has the region information */
|
||||
hose = pci_bus_to_hose(0);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* if PCI_REGION_MEM is set we do a two pass search with preference
|
||||
* on matches that don't have PCI_REGION_SYS_MEMORY set
|
||||
|
|
|
|||
|
|
@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
return dev_get_uclass_priv(bus);
|
||||
return dev_get_uclass_priv(pci_get_controller(bus));
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
140
drivers/pci/pcie_layerscape.h
Normal file
140
drivers/pci/pcie_layerscape.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
* Layerscape PCIe driver
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_LAYERSCAPE_H_
|
||||
#define _PCIE_LAYERSCAPE_H_
|
||||
#include <pci.h>
|
||||
#include <dm.h>
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
|
||||
#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
|
||||
#endif
|
||||
|
||||
/* iATU registers */
|
||||
#define PCIE_ATU_VIEWPORT 0x900
|
||||
#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
|
||||
#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
|
||||
#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
|
||||
#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
|
||||
#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
|
||||
#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
|
||||
#define PCIE_ATU_REGION_NUM 6
|
||||
#define PCIE_ATU_CR1 0x904
|
||||
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
|
||||
#define PCIE_ATU_TYPE_IO (0x2 << 0)
|
||||
#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
|
||||
#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
|
||||
#define PCIE_ATU_CR2 0x908
|
||||
#define PCIE_ATU_ENABLE (0x1 << 31)
|
||||
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
|
||||
#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
|
||||
#define PCIE_ATU_LOWER_BASE 0x90C
|
||||
#define PCIE_ATU_UPPER_BASE 0x910
|
||||
#define PCIE_ATU_LIMIT 0x914
|
||||
#define PCIE_ATU_LOWER_TARGET 0x918
|
||||
#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
|
||||
#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
|
||||
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
|
||||
#define PCIE_ATU_UPPER_TARGET 0x91C
|
||||
|
||||
/* DBI registers */
|
||||
#define PCIE_SRIOV 0x178
|
||||
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
|
||||
#define PCIE_DBI_RO_WR_EN 0x8bc
|
||||
|
||||
#define PCIE_LINK_CAP 0x7c
|
||||
#define PCIE_LINK_SPEED_MASK 0xf
|
||||
#define PCIE_LINK_WIDTH_MASK 0x3f0
|
||||
#define PCIE_LINK_STA 0x82
|
||||
|
||||
#define LTSSM_STATE_MASK 0x3f
|
||||
#define LTSSM_PCIE_L0 0x11 /* L0 state */
|
||||
|
||||
#define PCIE_DBI_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
|
||||
#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
|
||||
#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
|
||||
#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
|
||||
#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
|
||||
PCIE_LCTRL0_VF(vf) | \
|
||||
((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
|
||||
PCIE_LCTRL0_CFG2_ENABLE)
|
||||
|
||||
#define PCIE_NO_SRIOV_BAR_BASE 0x1000
|
||||
|
||||
#define PCIE_PF_NUM 2
|
||||
#define PCIE_VF_NUM 64
|
||||
|
||||
#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
|
||||
#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
|
||||
#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
|
||||
#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
|
||||
|
||||
/* LUT registers */
|
||||
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
|
||||
#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
|
||||
#define PCIE_LUT_ENABLE (1 << 31)
|
||||
#define PCIE_LUT_ENTRY_COUNT 32
|
||||
|
||||
/* PF Controll registers */
|
||||
#define PCIE_PF_VF_CTRL 0x7F8
|
||||
#define PCIE_PF_DBG 0x7FC
|
||||
|
||||
#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
|
||||
#define PCIE_SYS_BASE_ADDR 0x3400000
|
||||
#define PCIE_CCSR_SIZE 0x0100000
|
||||
|
||||
/* CS2 */
|
||||
#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
|
||||
|
||||
#define SVR_LS102XA 0
|
||||
#define SVR_VAR_PER_SHIFT 8
|
||||
#define SVR_LS102XA_MASK 0x700
|
||||
|
||||
/* LS1021a PCIE space */
|
||||
#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
|
||||
#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
|
||||
|
||||
/* LS1021a PEX1/2 Misc Ports Status Register */
|
||||
#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
|
||||
#define LS1021_LTSSM_STATE_SHIFT 20
|
||||
|
||||
struct ls_pcie {
|
||||
int idx;
|
||||
struct list_head list;
|
||||
struct udevice *bus;
|
||||
struct fdt_resource dbi_res;
|
||||
struct fdt_resource lut_res;
|
||||
struct fdt_resource ctrl_res;
|
||||
struct fdt_resource cfg_res;
|
||||
void __iomem *dbi;
|
||||
void __iomem *lut;
|
||||
void __iomem *ctrl;
|
||||
void __iomem *cfg0;
|
||||
void __iomem *cfg1;
|
||||
bool big_endian;
|
||||
bool enabled;
|
||||
int next_lut_index;
|
||||
struct pci_controller hose;
|
||||
};
|
||||
|
||||
extern struct list_head ls_pcie_list;
|
||||
|
||||
#endif /* _PCIE_LAYERSCAPE_H_ */
|
||||
187
drivers/pci/pcie_layerscape_fixup.c
Normal file
187
drivers/pci/pcie_layerscape_fixup.c
Normal file
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
* Layerscape PCIe driver
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include "pcie_layerscape.h"
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
/*
|
||||
* Return next available LUT index.
|
||||
*/
|
||||
static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
|
||||
{
|
||||
if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
|
||||
return pcie->next_lut_index++;
|
||||
else
|
||||
return -ENOSPC; /* LUT is full */
|
||||
}
|
||||
|
||||
/* returns the next available streamid for pcie, -errno if failed */
|
||||
static int ls_pcie_next_streamid(void)
|
||||
{
|
||||
static int next_stream_id = FSL_PEX_STREAM_ID_START;
|
||||
|
||||
if (next_stream_id > FSL_PEX_STREAM_ID_END)
|
||||
return -EINVAL;
|
||||
|
||||
return next_stream_id++;
|
||||
}
|
||||
|
||||
static void lut_writel(struct ls_pcie *pcie, unsigned int value,
|
||||
unsigned int offset)
|
||||
{
|
||||
if (pcie->big_endian)
|
||||
out_be32(pcie->lut + offset, value);
|
||||
else
|
||||
out_le32(pcie->lut + offset, value);
|
||||
}
|
||||
|
||||
/*
|
||||
* Program a single LUT entry
|
||||
*/
|
||||
static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
|
||||
u32 streamid)
|
||||
{
|
||||
/* leave mask as all zeroes, want to match all bits */
|
||||
lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
|
||||
lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
|
||||
}
|
||||
|
||||
/*
|
||||
* An msi-map is a property to be added to the pci controller
|
||||
* node. It is a table, where each entry consists of 4 fields
|
||||
* e.g.:
|
||||
*
|
||||
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
|
||||
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
|
||||
*/
|
||||
static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
|
||||
u32 devid, u32 streamid)
|
||||
{
|
||||
u32 *prop;
|
||||
u32 phandle;
|
||||
int nodeoffset;
|
||||
|
||||
/* find pci controller node */
|
||||
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
|
||||
pcie->dbi_res.start);
|
||||
if (nodeoffset < 0) {
|
||||
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
|
||||
nodeoffset = fdt_node_offset_by_compat_reg(blob,
|
||||
CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
|
||||
if (nodeoffset < 0)
|
||||
return;
|
||||
#else
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* get phandle to MSI controller */
|
||||
prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
|
||||
if (prop == NULL) {
|
||||
debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
|
||||
__func__, pcie->idx);
|
||||
return;
|
||||
}
|
||||
phandle = fdt32_to_cpu(*prop);
|
||||
|
||||
/* set one msi-map row */
|
||||
fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
|
||||
fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
|
||||
fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
|
||||
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
|
||||
}
|
||||
|
||||
static void fdt_fixup_pcie(void *blob)
|
||||
{
|
||||
struct udevice *dev, *bus;
|
||||
struct ls_pcie *pcie;
|
||||
int streamid;
|
||||
int index;
|
||||
pci_dev_t bdf;
|
||||
|
||||
/* Scan all known buses */
|
||||
for (pci_find_first_device(&dev);
|
||||
dev;
|
||||
pci_find_next_device(&dev)) {
|
||||
for (bus = dev; device_is_on_pci_bus(bus);)
|
||||
bus = bus->parent;
|
||||
pcie = dev_get_priv(bus);
|
||||
|
||||
streamid = ls_pcie_next_streamid();
|
||||
if (streamid < 0) {
|
||||
debug("ERROR: no stream ids free\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
index = ls_pcie_next_lut_index(pcie);
|
||||
if (index < 0) {
|
||||
debug("ERROR: no LUT indexes free\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
/* the DT fixup must be relative to the hose first_busno */
|
||||
bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
|
||||
/* map PCI b.d.f to streamID in LUT */
|
||||
ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
|
||||
streamid);
|
||||
/* update msi-map in device tree */
|
||||
fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
|
||||
streamid);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
|
||||
{
|
||||
int off;
|
||||
|
||||
off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
|
||||
pcie->dbi_res.start);
|
||||
if (off < 0) {
|
||||
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
|
||||
off = fdt_node_offset_by_compat_reg(blob,
|
||||
CONFIG_FSL_PCIE_COMPAT,
|
||||
pcie->dbi_res.start);
|
||||
if (off < 0)
|
||||
return;
|
||||
#else
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (pcie->enabled)
|
||||
fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
|
||||
else
|
||||
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
|
||||
}
|
||||
|
||||
/* Fixup Kernel DT for PCIe */
|
||||
void ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
struct ls_pcie *pcie;
|
||||
|
||||
list_for_each_entry(pcie, &ls_pcie_list, list)
|
||||
ft_pcie_ls_setup(blob, pcie);
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
fdt_fixup_pcie(blob);
|
||||
#endif
|
||||
}
|
||||
|
||||
#else /* !CONFIG_OF_BOARD_SETUP */
|
||||
void ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
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