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armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3

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Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround
implementing of erratum reusable for more SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Shengzhou Liu 2016-11-11 18:11:05 +08:00 committed by York Sun
parent c3aa1df28d
commit 40836e215a
1 changed files with 4 additions and 3 deletions
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7
arch/arm/cpu/armv8/fsl-layerscape/soc.c
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@ -50,16 +50,16 @@ bool soc_has_aiop(void)
return false;
}
#ifdef CONFIG_LS2080A
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.
*/
static void erratum_a008336(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
@ -79,9 +79,9 @@ static void erratum_a008336(void)
*/
static void erratum_a008514(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
@ -176,6 +176,7 @@ static void erratum_a009203(void)
#endif
#endif
}
void bypass_smmu(void)
{
u32 val;